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8220441: [PPC64] Clobber memory effect missing for memory barriers in atomics

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Reviewed-by: simonis, goetz
This commit is contained in:
Martin Doerr 2019-03-12 11:53:43 +01:00
parent 0f97ac953b
commit bc640addb3
2 changed files with 12 additions and 46 deletions
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28
src/hotspot/os_cpu/aix_ppc/atomic_aix_ppc.hpp
View File

@ -1,6 +1,6 @@
/*
* Copyright (c) 1997, 2019, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2012, 2018 SAP SE. All rights reserved.
* Copyright (c) 2012, 2019 SAP SE. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
@ -70,22 +70,13 @@
// Store|Load
//
#define strasm_sync "\n sync \n"
#define strasm_lwsync "\n lwsync \n"
#define strasm_isync "\n isync \n"
#define strasm_release strasm_lwsync
#define strasm_acquire strasm_lwsync
#define strasm_fence strasm_sync
#define strasm_nobarrier ""
#define strasm_nobarrier_clobber_memory ""
inline void pre_membar(atomic_memory_order order) {
switch (order) {
case memory_order_relaxed:
case memory_order_acquire: break;
case memory_order_release:
case memory_order_acq_rel: __asm__ __volatile__ (strasm_lwsync); break;
default /*conservative*/ : __asm__ __volatile__ (strasm_sync); break;
case memory_order_acq_rel: __asm__ __volatile__ ("lwsync" : : : "memory"); break;
default /*conservative*/ : __asm__ __volatile__ ("sync" : : : "memory"); break;
}
}
@ -94,8 +85,8 @@ inline void post_membar(atomic_memory_order order) {
case memory_order_relaxed:
case memory_order_release: break;
case memory_order_acquire:
case memory_order_acq_rel: __asm__ __volatile__ (strasm_isync); break;
default /*conservative*/ : __asm__ __volatile__ (strasm_sync); break;
case memory_order_acq_rel: __asm__ __volatile__ ("isync" : : : "memory"); break;
default /*conservative*/ : __asm__ __volatile__ ("sync" : : : "memory"); break;
}
}
@ -408,13 +399,4 @@ inline T Atomic::PlatformCmpxchg<8>::operator()(T exchange_value,
return old_value;
}
#undef strasm_sync
#undef strasm_lwsync
#undef strasm_isync
#undef strasm_release
#undef strasm_acquire
#undef strasm_fence
#undef strasm_nobarrier
#undef strasm_nobarrier_clobber_memory
#endif // OS_CPU_AIX_PPC_ATOMIC_AIX_PPC_HPP

30
src/hotspot/os_cpu/linux_ppc/atomic_linux_ppc.hpp
View File

@ -1,6 +1,6 @@
/*
* Copyright (c) 1997, 2019, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2012, 2018 SAP SE. All rights reserved.
* Copyright (c) 2012, 2019 SAP SE. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
@ -30,6 +30,8 @@
#error "Atomic currently only implemented for PPC64"
#endif
#include "utilities/debug.hpp"
// Implementation of class atomic
//
@ -68,22 +70,13 @@
// Store|Load
//
#define strasm_sync "\n sync \n"
#define strasm_lwsync "\n lwsync \n"
#define strasm_isync "\n isync \n"
#define strasm_release strasm_lwsync
#define strasm_acquire strasm_lwsync
#define strasm_fence strasm_sync
#define strasm_nobarrier ""
#define strasm_nobarrier_clobber_memory ""
inline void pre_membar(atomic_memory_order order) {
switch (order) {
case memory_order_relaxed:
case memory_order_acquire: break;
case memory_order_release:
case memory_order_acq_rel: __asm__ __volatile__ (strasm_lwsync); break;
default /*conservative*/ : __asm__ __volatile__ (strasm_sync); break;
case memory_order_acq_rel: __asm__ __volatile__ ("lwsync" : : : "memory"); break;
default /*conservative*/ : __asm__ __volatile__ ("sync" : : : "memory"); break;
}
}
@ -92,8 +85,8 @@ inline void post_membar(atomic_memory_order order) {
case memory_order_relaxed:
case memory_order_release: break;
case memory_order_acquire:
case memory_order_acq_rel: __asm__ __volatile__ (strasm_isync); break;
default /*conservative*/ : __asm__ __volatile__ (strasm_sync); break;
case memory_order_acq_rel: __asm__ __volatile__ ("isync" : : : "memory"); break;
default /*conservative*/ : __asm__ __volatile__ ("sync" : : : "memory"); break;
}
}
@ -406,13 +399,4 @@ inline T Atomic::PlatformCmpxchg<8>::operator()(T exchange_value,
return old_value;
}
#undef strasm_sync
#undef strasm_lwsync
#undef strasm_isync
#undef strasm_release
#undef strasm_acquire
#undef strasm_fence
#undef strasm_nobarrier
#undef strasm_nobarrier_clobber_memory
#endif // OS_CPU_LINUX_PPC_ATOMIC_LINUX_PPC_HPP