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8381988: Fix inconsistency in clearing cpu feature bits

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Reviewed-by: sviswanathan, kvn
This commit is contained in:
Ashutosh Mehra 2026-04-23 21:38:13 +00:00
parent 3bbb0d9f00
commit bfb4c5801e
19 changed files with 203 additions and 223 deletions
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6
src/hotspot/cpu/aarch64/vm_version_aarch64.cpp
View File

@ -305,9 +305,9 @@ void VM_Version::initialize() {
FLAG_SET_DEFAULT(UseSHA, false);
}
CHECK_CPU_FEATURE(supports_crc32, CRC32);
CHECK_CPU_FEATURE(supports_lse, LSE);
CHECK_CPU_FEATURE(supports_aes, AES);
CHECK_CPU_FEATURE(UseCRC32, CRC32, supports_crc32(), MULTI_INST_WARNING_MSG);
CHECK_CPU_FEATURE(UseLSE, LSE, supports_lse(), MULTI_INST_WARNING_MSG);
CHECK_CPU_FEATURE(UseAES, AES, supports_aes(), MULTI_INST_WARNING_MSG);
if (_cpu == CPU_ARM &&
model_is_in({ CPU_MODEL_ARM_NEOVERSE_V1, CPU_MODEL_ARM_NEOVERSE_V2,

48
src/hotspot/cpu/x86/assembler_x86.cpp
View File

@ -1664,14 +1664,14 @@ void Assembler::eandl(Register dst, Register src1, Register src2, bool no_flags)
}
void Assembler::andnl(Register dst, Register src1, Register src2) {
assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
assert(VM_Version::supports_bmi1() && VM_Version::supports_avx(), "bit manipulation instructions not supported");
InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes, true);
emit_int16((unsigned char)0xF2, (0xC0 | encode));
}
void Assembler::andnl(Register dst, Register src1, Address src2) {
assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
assert(VM_Version::supports_bmi1() && VM_Version::supports_avx(), "bit manipulation instructions not supported");
InstructionMark im(this);
InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
attributes.set_address_attributes(/* tuple_type */ EVEX_NOSCALE, /* input_size_in_bits */ EVEX_32bit);
@ -1696,14 +1696,14 @@ void Assembler::bswapl(Register reg) { // bswap
}
void Assembler::blsil(Register dst, Register src) {
assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
assert(VM_Version::supports_bmi1() && VM_Version::supports_avx(), "bit manipulation instructions not supported");
InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
int encode = vex_prefix_and_encode(rbx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes, true);
emit_int16((unsigned char)0xF3, (0xC0 | encode));
}
void Assembler::blsil(Register dst, Address src) {
assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
assert(VM_Version::supports_bmi1() && VM_Version::supports_avx(), "bit manipulation instructions not supported");
InstructionMark im(this);
InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
attributes.set_address_attributes(/* tuple_type */ EVEX_NOSCALE, /* input_size_in_bits */ EVEX_32bit);
@ -1713,7 +1713,7 @@ void Assembler::blsil(Register dst, Address src) {
}
void Assembler::blsmskl(Register dst, Register src) {
assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
assert(VM_Version::supports_bmi1() && VM_Version::supports_avx(), "bit manipulation instructions not supported");
InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
int encode = vex_prefix_and_encode(rdx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes, true);
emit_int16((unsigned char)0xF3,
@ -1721,7 +1721,7 @@ void Assembler::blsmskl(Register dst, Register src) {
}
void Assembler::blsmskl(Register dst, Address src) {
assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
assert(VM_Version::supports_bmi1() && VM_Version::supports_avx(), "bit manipulation instructions not supported");
InstructionMark im(this);
InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
attributes.set_address_attributes(/* tuple_type */ EVEX_NOSCALE, /* input_size_in_bits */ EVEX_32bit);
@ -1731,14 +1731,14 @@ void Assembler::blsmskl(Register dst, Address src) {
}
void Assembler::blsrl(Register dst, Register src) {
assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
assert(VM_Version::supports_bmi1() && VM_Version::supports_avx(), "bit manipulation instructions not supported");
InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
int encode = vex_prefix_and_encode(rcx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes, true);
emit_int16((unsigned char)0xF3, (0xC0 | encode));
}
void Assembler::blsrl(Register dst, Address src) {
assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
assert(VM_Version::supports_bmi1() && VM_Version::supports_avx(), "bit manipulation instructions not supported");
InstructionMark im(this);
InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
attributes.set_address_attributes(/* tuple_type */ EVEX_NOSCALE, /* input_size_in_bits */ EVEX_32bit);
@ -7275,21 +7275,21 @@ void Assembler::testl(Register dst, Address src) {
}
void Assembler::tzcntl(Register dst, Register src) {
assert(VM_Version::supports_bmi1(), "tzcnt instruction not supported");
assert(UseCountTrailingZerosInstruction, "tzcnt instruction not supported");
emit_int8((unsigned char)0xF3);
int encode = prefix_and_encode(dst->encoding(), src->encoding(), true /* is_map1 */);
emit_opcode_prefix_and_encoding((unsigned char)0xBC, 0xC0, encode);
}
void Assembler::etzcntl(Register dst, Register src, bool no_flags) {
assert(VM_Version::supports_bmi1(), "tzcnt instruction not supported");
assert(UseCountTrailingZerosInstruction, "tzcnt instruction not supported");
InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
int encode = eevex_prefix_and_encode_nf(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C /* MAP4 */, &attributes, no_flags);
emit_int16((unsigned char)0xF4, (0xC0 | encode));
}
void Assembler::tzcntl(Register dst, Address src) {
assert(VM_Version::supports_bmi1(), "tzcnt instruction not supported");
assert(UseCountTrailingZerosInstruction, "tzcnt instruction not supported");
InstructionMark im(this);
emit_int8((unsigned char)0xF3);
prefix(src, dst, false, true /* is_map1 */);
@ -7298,7 +7298,7 @@ void Assembler::tzcntl(Register dst, Address src) {
}
void Assembler::etzcntl(Register dst, Address src, bool no_flags) {
assert(VM_Version::supports_bmi1(), "tzcnt instruction not supported");
assert(UseCountTrailingZerosInstruction, "tzcnt instruction not supported");
InstructionMark im(this);
InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
attributes.set_address_attributes(/* tuple_type */ EVEX_NOSCALE, /* input_size_in_bits */ EVEX_32bit);
@ -7308,21 +7308,21 @@ void Assembler::etzcntl(Register dst, Address src, bool no_flags) {
}
void Assembler::tzcntq(Register dst, Register src) {
assert(VM_Version::supports_bmi1(), "tzcnt instruction not supported");
assert(UseCountTrailingZerosInstruction, "tzcnt instruction not supported");
emit_int8((unsigned char)0xF3);
int encode = prefixq_and_encode(dst->encoding(), src->encoding(), true /* is_map1 */);
emit_opcode_prefix_and_encoding((unsigned char)0xBC, 0xC0, encode);
}
void Assembler::etzcntq(Register dst, Register src, bool no_flags) {
assert(VM_Version::supports_bmi1(), "tzcnt instruction not supported");
assert(UseCountTrailingZerosInstruction, "tzcnt instruction not supported");
InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
int encode = eevex_prefix_and_encode_nf(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C /* MAP4 */, &attributes, no_flags);
emit_int16((unsigned char)0xF4, (0xC0 | encode));
}
void Assembler::tzcntq(Register dst, Address src) {
assert(VM_Version::supports_bmi1(), "tzcnt instruction not supported");
assert(UseCountTrailingZerosInstruction, "tzcnt instruction not supported");
InstructionMark im(this);
emit_int8((unsigned char)0xF3);
prefixq(src, dst, true /* is_map1 */);
@ -7331,7 +7331,7 @@ void Assembler::tzcntq(Register dst, Address src) {
}
void Assembler::etzcntq(Register dst, Address src, bool no_flags) {
assert(VM_Version::supports_bmi1(), "tzcnt instruction not supported");
assert(UseCountTrailingZerosInstruction, "tzcnt instruction not supported");
InstructionMark im(this);
InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
attributes.set_address_attributes(/* tuple_type */ EVEX_NOSCALE, /* input_size_in_bits */ EVEX_64bit);
@ -15000,14 +15000,14 @@ void Assembler::eandq(Register dst, Address src1, Register src2, bool no_flags)
}
void Assembler::andnq(Register dst, Register src1, Register src2) {
assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
assert(VM_Version::supports_bmi1() && VM_Version::supports_avx(), "bit manipulation instructions not supported");
InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes, true);
emit_int16((unsigned char)0xF2, (0xC0 | encode));
}
void Assembler::andnq(Register dst, Register src1, Address src2) {
assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
assert(VM_Version::supports_bmi1() && VM_Version::supports_avx(), "bit manipulation instructions not supported");
InstructionMark im(this);
InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
attributes.set_address_attributes(/* tuple_type */ EVEX_NOSCALE, /* input_size_in_bits */ EVEX_64bit);
@ -15032,14 +15032,14 @@ void Assembler::bswapq(Register reg) {
}
void Assembler::blsiq(Register dst, Register src) {
assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
assert(VM_Version::supports_bmi1() && VM_Version::supports_avx(), "bit manipulation instructions not supported");
InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
int encode = vex_prefix_and_encode(rbx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes, true);
emit_int16((unsigned char)0xF3, (0xC0 | encode));
}
void Assembler::blsiq(Register dst, Address src) {
assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
assert(VM_Version::supports_bmi1() && VM_Version::supports_avx(), "bit manipulation instructions not supported");
InstructionMark im(this);
InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
attributes.set_address_attributes(/* tuple_type */ EVEX_NOSCALE, /* input_size_in_bits */ EVEX_64bit);
@ -15049,14 +15049,14 @@ void Assembler::blsiq(Register dst, Address src) {
}
void Assembler::blsmskq(Register dst, Register src) {
assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
assert(VM_Version::supports_bmi1() && VM_Version::supports_avx(), "bit manipulation instructions not supported");
InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
int encode = vex_prefix_and_encode(rdx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes, true);
emit_int16((unsigned char)0xF3, (0xC0 | encode));
}
void Assembler::blsmskq(Register dst, Address src) {
assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
assert(VM_Version::supports_bmi1() && VM_Version::supports_avx(), "bit manipulation instructions not supported");
InstructionMark im(this);
InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
attributes.set_address_attributes(/* tuple_type */ EVEX_NOSCALE, /* input_size_in_bits */ EVEX_64bit);
@ -15066,14 +15066,14 @@ void Assembler::blsmskq(Register dst, Address src) {
}
void Assembler::blsrq(Register dst, Register src) {
assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
assert(VM_Version::supports_bmi1() && VM_Version::supports_avx(), "bit manipulation instructions not supported");
InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
int encode = vex_prefix_and_encode(rcx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes, true);
emit_int16((unsigned char)0xF3, (0xC0 | encode));
}
void Assembler::blsrq(Register dst, Address src) {
assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
assert(VM_Version::supports_bmi1() && VM_Version::supports_avx(), "bit manipulation instructions not supported");
InstructionMark im(this);
InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
attributes.set_address_attributes(/* tuple_type */ EVEX_NOSCALE, /* input_size_in_bits */ EVEX_64bit);

14
src/hotspot/cpu/x86/c2_MacroAssembler_x86.cpp
View File

@ -5558,7 +5558,7 @@ void C2_MacroAssembler::vector_mask_operation_helper(int opc, Register dst, Regi
}
break;
case Op_VectorMaskFirstTrue:
if (VM_Version::supports_bmi1()) {
if (UseCountTrailingZerosInstruction) {
if (masklen < 32) {
orl(tmp, 1 << masklen);
tzcntl(dst, tmp);
@ -6350,7 +6350,7 @@ void C2_MacroAssembler::udivI(Register rax, Register divisor, Register rdx) {
// See Hacker's Delight (2nd ed), section 9.3 which is implemented in java.lang.Long.divideUnsigned()
movl(rdx, rax);
subl(rdx, divisor);
if (VM_Version::supports_bmi1()) {
if (VM_Version::supports_bmi1() && VM_Version::supports_avx()) {
andnl(rax, rdx, rax);
} else {
notl(rdx);
@ -6374,7 +6374,7 @@ void C2_MacroAssembler::umodI(Register rax, Register divisor, Register rdx) {
// See Hacker's Delight (2nd ed), section 9.3 which is implemented in java.lang.Long.remainderUnsigned()
movl(rdx, rax);
subl(rax, divisor);
if (VM_Version::supports_bmi1()) {
if (VM_Version::supports_bmi1() && VM_Version::supports_avx()) {
andnl(rax, rax, rdx);
} else {
notl(rax);
@ -6403,7 +6403,7 @@ void C2_MacroAssembler::udivmodI(Register rax, Register divisor, Register rdx, R
// java.lang.Long.divideUnsigned() and java.lang.Long.remainderUnsigned()
movl(rdx, rax);
subl(rax, divisor);
if (VM_Version::supports_bmi1()) {
if (VM_Version::supports_bmi1() && VM_Version::supports_avx()) {
andnl(rax, rax, rdx);
} else {
notl(rax);
@ -6515,7 +6515,7 @@ void C2_MacroAssembler::udivL(Register rax, Register divisor, Register rdx) {
// See Hacker's Delight (2nd ed), section 9.3 which is implemented in java.lang.Long.divideUnsigned()
movq(rdx, rax);
subq(rdx, divisor);
if (VM_Version::supports_bmi1()) {
if (VM_Version::supports_bmi1() && VM_Version::supports_avx()) {
andnq(rax, rdx, rax);
} else {
notq(rdx);
@ -6539,7 +6539,7 @@ void C2_MacroAssembler::umodL(Register rax, Register divisor, Register rdx) {
// See Hacker's Delight (2nd ed), section 9.3 which is implemented in java.lang.Long.remainderUnsigned()
movq(rdx, rax);
subq(rax, divisor);
if (VM_Version::supports_bmi1()) {
if (VM_Version::supports_bmi1() && VM_Version::supports_avx()) {
andnq(rax, rax, rdx);
} else {
notq(rax);
@ -6567,7 +6567,7 @@ void C2_MacroAssembler::udivmodL(Register rax, Register divisor, Register rdx, R
// java.lang.Long.divideUnsigned() and java.lang.Long.remainderUnsigned()
movq(rdx, rax);
subq(rax, divisor);
if (VM_Version::supports_bmi1()) {
if (VM_Version::supports_bmi1() && VM_Version::supports_avx()) {
andnq(rax, rax, rdx);
} else {
notq(rax);

2
src/hotspot/cpu/x86/macroAssembler_x86.cpp
View File

@ -6967,7 +6967,7 @@ void MacroAssembler::vectorized_mismatch(Register obja, Register objb, Register
xorq(result, result);
if ((AVX3Threshold == 0) && (UseAVX > 2) &&
VM_Version::supports_avx512vlbw()) {
VM_Version::supports_avx512vlbw() && UseCountTrailingZerosInstruction) {
Label VECTOR64_LOOP, VECTOR64_NOT_EQUAL, VECTOR32_TAIL;
cmpq(length, 64);

4
src/hotspot/cpu/x86/stubGenerator_x86_64.cpp
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2003, 2025, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2003, 2026, Oracle and/or its affiliates. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
@ -4891,7 +4891,7 @@ void StubGenerator::generate_compiler_stubs() {
StubRoutines::_data_cache_writeback_sync = generate_data_cache_writeback_sync();
#ifdef COMPILER2
if ((UseAVX == 2) && EnableX86ECoreOpts) {
if ((UseAVX == 2) && EnableX86ECoreOpts && UseCountTrailingZerosInstruction) {
generate_string_indexof(StubRoutines::_string_indexof_array);
}
#endif

216
src/hotspot/cpu/x86/vm_version_x86.cpp
View File

@ -942,21 +942,21 @@ void VM_Version::get_processor_features() {
}
if (UseSSE < 4) {
_features.clear_feature(CPU_SSE4_1);
_features.clear_feature(CPU_SSE4_2);
clear_feature(CPU_SSE4_1);
clear_feature(CPU_SSE4_2);
}
if (UseSSE < 3) {
_features.clear_feature(CPU_SSE3);
_features.clear_feature(CPU_SSSE3);
_features.clear_feature(CPU_SSE4A);
clear_feature(CPU_SSE3);
clear_feature(CPU_SSSE3);
clear_feature(CPU_SSE4A);
}
if (UseSSE < 2)
_features.clear_feature(CPU_SSE2);
clear_feature(CPU_SSE2);
if (UseSSE < 1)
_features.clear_feature(CPU_SSE);
clear_feature(CPU_SSE);
// ZX cpus specific settings
if (is_zx() && FLAG_IS_DEFAULT(UseAVX)) {
@ -1030,102 +1030,119 @@ void VM_Version::get_processor_features() {
}
if (UseAVX < 3) {
_features.clear_feature(CPU_AVX512F);
_features.clear_feature(CPU_AVX512DQ);
_features.clear_feature(CPU_AVX512CD);
_features.clear_feature(CPU_AVX512BW);
_features.clear_feature(CPU_AVX512ER);
_features.clear_feature(CPU_AVX512PF);
_features.clear_feature(CPU_AVX512VL);
_features.clear_feature(CPU_AVX512_VPOPCNTDQ);
_features.clear_feature(CPU_AVX512_VPCLMULQDQ);
_features.clear_feature(CPU_AVX512_VAES);
_features.clear_feature(CPU_AVX512_VNNI);
_features.clear_feature(CPU_AVX512_VBMI);
_features.clear_feature(CPU_AVX512_VBMI2);
_features.clear_feature(CPU_AVX512_BITALG);
_features.clear_feature(CPU_AVX512_IFMA);
_features.clear_feature(CPU_APX_F);
_features.clear_feature(CPU_AVX512_FP16);
_features.clear_feature(CPU_AVX10_1);
_features.clear_feature(CPU_AVX10_2);
clear_feature(CPU_AVX512F);
clear_feature(CPU_AVX512DQ);
clear_feature(CPU_AVX512CD);
clear_feature(CPU_AVX512BW);
clear_feature(CPU_AVX512ER);
clear_feature(CPU_AVX512PF);
clear_feature(CPU_AVX512VL);
clear_feature(CPU_AVX512_VPOPCNTDQ);
clear_feature(CPU_AVX512_VPCLMULQDQ);
clear_feature(CPU_AVX512_VAES);
clear_feature(CPU_AVX512_VNNI);
clear_feature(CPU_AVX512_VBMI);
clear_feature(CPU_AVX512_VBMI2);
clear_feature(CPU_AVX512_BITALG);
clear_feature(CPU_AVX512_IFMA);
clear_feature(CPU_APX_F);
clear_feature(CPU_AVX512_FP16);
clear_feature(CPU_AVX10_1);
clear_feature(CPU_AVX10_2);
}
if (UseAVX < 2) {
_features.clear_feature(CPU_AVX2);
_features.clear_feature(CPU_AVX_IFMA);
clear_feature(CPU_AVX2);
clear_feature(CPU_AVX_IFMA);
}
if (UseAVX < 1) {
_features.clear_feature(CPU_AVX);
_features.clear_feature(CPU_VZEROUPPER);
_features.clear_feature(CPU_F16C);
_features.clear_feature(CPU_SHA512);
clear_feature(CPU_AVX);
clear_feature(CPU_VZEROUPPER);
clear_feature(CPU_F16C);
clear_feature(CPU_SHA512);
}
if (logical_processors_per_package() == 1) {
// HT processor could be installed on a system which doesn't support HT.
_features.clear_feature(CPU_HT);
clear_feature(CPU_HT);
}
if (is_intel()) { // Intel cpus specific settings
if (is_knights_family()) {
_features.clear_feature(CPU_VZEROUPPER);
_features.clear_feature(CPU_AVX512BW);
_features.clear_feature(CPU_AVX512VL);
_features.clear_feature(CPU_APX_F);
_features.clear_feature(CPU_AVX512DQ);
_features.clear_feature(CPU_AVX512_VNNI);
_features.clear_feature(CPU_AVX512_VAES);
_features.clear_feature(CPU_AVX512_VPOPCNTDQ);
_features.clear_feature(CPU_AVX512_VPCLMULQDQ);
_features.clear_feature(CPU_AVX512_VBMI);
_features.clear_feature(CPU_AVX512_VBMI2);
_features.clear_feature(CPU_CLWB);
_features.clear_feature(CPU_FLUSHOPT);
_features.clear_feature(CPU_GFNI);
_features.clear_feature(CPU_AVX512_BITALG);
_features.clear_feature(CPU_AVX512_IFMA);
_features.clear_feature(CPU_AVX_IFMA);
_features.clear_feature(CPU_AVX512_FP16);
_features.clear_feature(CPU_AVX10_1);
_features.clear_feature(CPU_AVX10_2);
clear_feature(CPU_VZEROUPPER);
clear_feature(CPU_AVX512BW);
clear_feature(CPU_AVX512VL);
clear_feature(CPU_APX_F);
clear_feature(CPU_AVX512DQ);
clear_feature(CPU_AVX512_VNNI);
clear_feature(CPU_AVX512_VAES);
clear_feature(CPU_AVX512_VPOPCNTDQ);
clear_feature(CPU_AVX512_VPCLMULQDQ);
clear_feature(CPU_AVX512_VBMI);
clear_feature(CPU_AVX512_VBMI2);
clear_feature(CPU_CLWB);
clear_feature(CPU_FLUSHOPT);
clear_feature(CPU_GFNI);
clear_feature(CPU_AVX512_BITALG);
clear_feature(CPU_AVX512_IFMA);
clear_feature(CPU_AVX_IFMA);
clear_feature(CPU_AVX512_FP16);
clear_feature(CPU_AVX10_1);
clear_feature(CPU_AVX10_2);
}
}
// Currently APX support is only enabled for targets supporting AVX512VL feature.
if (supports_apx_f() && os_supports_apx_egprs() && supports_avx512vl()) {
if (FLAG_IS_DEFAULT(UseAPX)) {
UseAPX = false; // by default UseAPX is false
_features.clear_feature(CPU_APX_F);
FLAG_SET_DEFAULT(UseAPX, false); // by default UseAPX is false
clear_feature(CPU_APX_F);
} else if (!UseAPX) {
_features.clear_feature(CPU_APX_F);
clear_feature(CPU_APX_F);
}
} else if (UseAPX) {
if (!FLAG_IS_DEFAULT(UseAPX)) {
warning("APX is not supported on this CPU, setting it to false)");
} else {
if (!os_supports_apx_egprs() || !supports_avx512vl()) {
clear_feature(CPU_APX_F);
}
if (UseAPX) {
if (!FLAG_IS_DEFAULT(UseAPX)) {
warning("APX is not supported on this CPU, setting it to false)");
}
FLAG_SET_DEFAULT(UseAPX, false);
}
FLAG_SET_DEFAULT(UseAPX, false);
}
CHECK_CPU_FEATURE(supports_clmul, CLMUL);
CHECK_CPU_FEATURE(supports_aes, AES);
CHECK_CPU_FEATURE(supports_fma, FMA);
CHECK_CPU_FEATURE(UseCLMUL, CLMUL, supports_clmul(), MULTI_INST_WARNING_MSG);
CHECK_CPU_FEATURE(UseAES, AES, supports_aes(), MULTI_INST_WARNING_MSG);
CHECK_CPU_FEATURE(UseFMA, FMA, supports_fma(), MULTI_INST_WARNING_MSG);
CHECK_CPU_FEATURE(UseCountLeadingZerosInstruction, LZCNT, supports_lzcnt(), SINGLE_INST_WARNING_MSG);
// BMI instructions (except tzcnt) use an encoding with VEX prefix.
// VEX prefix is generated only when AVX > 0.
CHECK_CPU_FEATURE(UseBMI1Instructions, BMI1, supports_bmi1(), MULTI_INST_WARNING_MSG);
if (supports_sha() || (supports_avx2() && supports_bmi2())) {
if (FLAG_IS_DEFAULT(UseSHA)) {
UseSHA = true;
} else if (!UseSHA) {
_features.clear_feature(CPU_SHA);
if (supports_bmi2() && supports_avx()) {
if (FLAG_IS_DEFAULT(UseBMI2Instructions)) {
FLAG_SET_DEFAULT(UseBMI2Instructions, true);
} else if (!UseBMI2Instructions) {
clear_feature(CPU_BMI2);
}
} else if (UseSHA) {
if (!FLAG_IS_DEFAULT(UseSHA)) {
warning("SHA instructions are not available on this CPU");
} else {
if (!supports_avx()) {
clear_feature(CPU_BMI2);
}
if (UseBMI2Instructions) {
if (!FLAG_IS_DEFAULT(UseBMI2Instructions)) {
warning("BMI2 instructions are not available on this CPU (AVX is also required)");
}
FLAG_SET_DEFAULT(UseBMI2Instructions, false);
}
FLAG_SET_DEFAULT(UseSHA, false);
}
CHECK_CPU_FEATURE(UsePopCountInstruction, POPCNT, supports_popcnt(), SINGLE_INST_WARNING_MSG);
CHECK_CPU_FEATURE(UseSHA, SHA, supports_sha() || (supports_avx2() && supports_bmi2()), MULTI_INST_WARNING_MSG);
if (FLAG_IS_DEFAULT(IntelJccErratumMitigation)) {
_has_intel_jcc_erratum = compute_has_intel_jcc_erratum();
FLAG_SET_ERGO(IntelJccErratumMitigation, _has_intel_jcc_erratum);
@ -1716,28 +1733,11 @@ void VM_Version::get_processor_features() {
FLAG_SET_DEFAULT(UseVectorizedHashCodeIntrinsic, false);
}
// Use count leading zeros count instruction if available.
if (supports_lzcnt()) {
if (FLAG_IS_DEFAULT(UseCountLeadingZerosInstruction)) {
UseCountLeadingZerosInstruction = true;
}
} else if (UseCountLeadingZerosInstruction) {
if (!FLAG_IS_DEFAULT(UseCountLeadingZerosInstruction)) {
warning("lzcnt instruction is not available on this CPU");
}
FLAG_SET_DEFAULT(UseCountLeadingZerosInstruction, false);
}
// Use count trailing zeros instruction if available
if (supports_bmi1()) {
// tzcnt does not require VEX prefix
if (FLAG_IS_DEFAULT(UseCountTrailingZerosInstruction)) {
if (!UseBMI1Instructions && !FLAG_IS_DEFAULT(UseBMI1Instructions)) {
// Don't use tzcnt if BMI1 is switched off on command line.
UseCountTrailingZerosInstruction = false;
} else {
UseCountTrailingZerosInstruction = true;
}
UseCountTrailingZerosInstruction = true;
}
} else if (UseCountTrailingZerosInstruction) {
if (!FLAG_IS_DEFAULT(UseCountTrailingZerosInstruction)) {
@ -1746,42 +1746,6 @@ void VM_Version::get_processor_features() {
FLAG_SET_DEFAULT(UseCountTrailingZerosInstruction, false);
}
// BMI instructions (except tzcnt) use an encoding with VEX prefix.
// VEX prefix is generated only when AVX > 0.
if (supports_bmi1() && supports_avx()) {
if (FLAG_IS_DEFAULT(UseBMI1Instructions)) {
UseBMI1Instructions = true;
}
} else if (UseBMI1Instructions) {
if (!FLAG_IS_DEFAULT(UseBMI1Instructions)) {
warning("BMI1 instructions are not available on this CPU (AVX is also required)");
}
FLAG_SET_DEFAULT(UseBMI1Instructions, false);
}
if (supports_bmi2() && supports_avx()) {
if (FLAG_IS_DEFAULT(UseBMI2Instructions)) {
UseBMI2Instructions = true;
}
} else if (UseBMI2Instructions) {
if (!FLAG_IS_DEFAULT(UseBMI2Instructions)) {
warning("BMI2 instructions are not available on this CPU (AVX is also required)");
}
FLAG_SET_DEFAULT(UseBMI2Instructions, false);
}
// Use population count instruction if available.
if (supports_popcnt()) {
if (FLAG_IS_DEFAULT(UsePopCountInstruction)) {
UsePopCountInstruction = true;
}
} else if (UsePopCountInstruction) {
if (!FLAG_IS_DEFAULT(UsePopCountInstruction)) {
warning("POPCNT instruction is not available on this CPU");
}
FLAG_SET_DEFAULT(UsePopCountInstruction, false);
}
// Use fast-string operations if available.
if (supports_erms()) {
if (FLAG_IS_DEFAULT(UseFastStosb)) {

36
src/hotspot/cpu/x86/x86.ad
View File

@ -4048,7 +4048,7 @@ class FusedPatternMatcher {
};
static bool is_bmi_pattern(Node* n, Node* m) {
assert(UseBMI1Instructions, "sanity");
assert(VM_Version::supports_bmi1() && VM_Version::supports_avx(), "sanity");
if (n != nullptr && m != nullptr) {
if (m->Opcode() == Op_LoadI) {
FusedPatternMatcher<TypeInt> bmii(n, m, Op_ConI);
@ -4068,7 +4068,7 @@ static bool is_bmi_pattern(Node* n, Node* m) {
// Should the matcher clone input 'm' of node 'n'?
bool Matcher::pd_clone_node(Node* n, Node* m, Matcher::MStack& mstack) {
// If 'n' and 'm' are part of a graph for BMI instruction, clone the input 'm'.
if (UseBMI1Instructions && is_bmi_pattern(n, m)) {
if (VM_Version::supports_bmi1() && VM_Version::supports_avx() && is_bmi_pattern(n, m)) {
mstack.push(m, Visit);
return true;
}
@ -13165,7 +13165,7 @@ instruct andI_mem_imm(memory dst, immI src, rFlagsReg cr)
// BMI1 instructions
instruct andnI_rReg_rReg_mem(rRegI dst, rRegI src1, memory src2, immI_M1 minus_1, rFlagsReg cr) %{
match(Set dst (AndI (XorI src1 minus_1) (LoadI src2)));
predicate(UseBMI1Instructions);
predicate(VM_Version::supports_bmi1() && VM_Version::supports_avx());
effect(KILL cr);
flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
@ -13180,7 +13180,7 @@ instruct andnI_rReg_rReg_mem(rRegI dst, rRegI src1, memory src2, immI_M1 minus_1
instruct andnI_rReg_rReg_rReg(rRegI dst, rRegI src1, rRegI src2, immI_M1 minus_1, rFlagsReg cr) %{
match(Set dst (AndI (XorI src1 minus_1) src2));
predicate(UseBMI1Instructions);
predicate(VM_Version::supports_bmi1() && VM_Version::supports_avx());
effect(KILL cr);
flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
@ -13194,7 +13194,7 @@ instruct andnI_rReg_rReg_rReg(rRegI dst, rRegI src1, rRegI src2, immI_M1 minus_1
instruct blsiI_rReg_rReg(rRegI dst, rRegI src, immI_0 imm_zero, rFlagsReg cr) %{
match(Set dst (AndI (SubI imm_zero src) src));
predicate(UseBMI1Instructions);
predicate(VM_Version::supports_bmi1() && VM_Version::supports_avx());
effect(KILL cr);
flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_clears_overflow_flag);
@ -13208,7 +13208,7 @@ instruct blsiI_rReg_rReg(rRegI dst, rRegI src, immI_0 imm_zero, rFlagsReg cr) %{
instruct blsiI_rReg_mem(rRegI dst, memory src, immI_0 imm_zero, rFlagsReg cr) %{
match(Set dst (AndI (SubI imm_zero (LoadI src) ) (LoadI src) ));
predicate(UseBMI1Instructions);
predicate(VM_Version::supports_bmi1() && VM_Version::supports_avx());
effect(KILL cr);
flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_clears_overflow_flag);
@ -13224,7 +13224,7 @@ instruct blsiI_rReg_mem(rRegI dst, memory src, immI_0 imm_zero, rFlagsReg cr) %{
instruct blsmskI_rReg_mem(rRegI dst, memory src, immI_M1 minus_1, rFlagsReg cr)
%{
match(Set dst (XorI (AddI (LoadI src) minus_1) (LoadI src) ) );
predicate(UseBMI1Instructions);
predicate(VM_Version::supports_bmi1() && VM_Version::supports_avx());
effect(KILL cr);
flag(PD::Flag_sets_sign_flag, PD::Flag_clears_zero_flag, PD::Flag_clears_overflow_flag);
@ -13240,7 +13240,7 @@ instruct blsmskI_rReg_mem(rRegI dst, memory src, immI_M1 minus_1, rFlagsReg cr)
instruct blsmskI_rReg_rReg(rRegI dst, rRegI src, immI_M1 minus_1, rFlagsReg cr)
%{
match(Set dst (XorI (AddI src minus_1) src));
predicate(UseBMI1Instructions);
predicate(VM_Version::supports_bmi1() && VM_Version::supports_avx());
effect(KILL cr);
flag(PD::Flag_sets_sign_flag, PD::Flag_clears_zero_flag, PD::Flag_clears_overflow_flag);
@ -13256,7 +13256,7 @@ instruct blsmskI_rReg_rReg(rRegI dst, rRegI src, immI_M1 minus_1, rFlagsReg cr)
instruct blsrI_rReg_rReg(rRegI dst, rRegI src, immI_M1 minus_1, rFlagsReg cr)
%{
match(Set dst (AndI (AddI src minus_1) src) );
predicate(UseBMI1Instructions);
predicate(VM_Version::supports_bmi1() && VM_Version::supports_avx());
effect(KILL cr);
flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_clears_overflow_flag);
@ -13272,7 +13272,7 @@ instruct blsrI_rReg_rReg(rRegI dst, rRegI src, immI_M1 minus_1, rFlagsReg cr)
instruct blsrI_rReg_mem(rRegI dst, memory src, immI_M1 minus_1, rFlagsReg cr)
%{
match(Set dst (AndI (AddI (LoadI src) minus_1) (LoadI src) ) );
predicate(UseBMI1Instructions);
predicate(VM_Version::supports_bmi1() && VM_Version::supports_avx());
effect(KILL cr);
flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_clears_overflow_flag);
@ -13813,7 +13813,7 @@ instruct btrL_mem_imm(memory dst, immL_NotPow2 con, rFlagsReg cr)
// BMI1 instructions
instruct andnL_rReg_rReg_mem(rRegL dst, rRegL src1, memory src2, immL_M1 minus_1, rFlagsReg cr) %{
match(Set dst (AndL (XorL src1 minus_1) (LoadL src2)));
predicate(UseBMI1Instructions);
predicate(VM_Version::supports_bmi1() && VM_Version::supports_avx());
effect(KILL cr);
flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
@ -13828,7 +13828,7 @@ instruct andnL_rReg_rReg_mem(rRegL dst, rRegL src1, memory src2, immL_M1 minus_1
instruct andnL_rReg_rReg_rReg(rRegL dst, rRegL src1, rRegL src2, immL_M1 minus_1, rFlagsReg cr) %{
match(Set dst (AndL (XorL src1 minus_1) src2));
predicate(UseBMI1Instructions);
predicate(VM_Version::supports_bmi1() && VM_Version::supports_avx());
effect(KILL cr);
flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
@ -13842,7 +13842,7 @@ instruct andnL_rReg_rReg_rReg(rRegL dst, rRegL src1, rRegL src2, immL_M1 minus_1
instruct blsiL_rReg_rReg(rRegL dst, rRegL src, immL0 imm_zero, rFlagsReg cr) %{
match(Set dst (AndL (SubL imm_zero src) src));
predicate(UseBMI1Instructions);
predicate(VM_Version::supports_bmi1() && VM_Version::supports_avx());
effect(KILL cr);
flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_clears_overflow_flag);
@ -13856,7 +13856,7 @@ instruct blsiL_rReg_rReg(rRegL dst, rRegL src, immL0 imm_zero, rFlagsReg cr) %{
instruct blsiL_rReg_mem(rRegL dst, memory src, immL0 imm_zero, rFlagsReg cr) %{
match(Set dst (AndL (SubL imm_zero (LoadL src) ) (LoadL src) ));
predicate(UseBMI1Instructions);
predicate(VM_Version::supports_bmi1() && VM_Version::supports_avx());
effect(KILL cr);
flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_clears_overflow_flag);
@ -13872,7 +13872,7 @@ instruct blsiL_rReg_mem(rRegL dst, memory src, immL0 imm_zero, rFlagsReg cr) %{
instruct blsmskL_rReg_mem(rRegL dst, memory src, immL_M1 minus_1, rFlagsReg cr)
%{
match(Set dst (XorL (AddL (LoadL src) minus_1) (LoadL src) ) );
predicate(UseBMI1Instructions);
predicate(VM_Version::supports_bmi1() && VM_Version::supports_avx());
effect(KILL cr);
flag(PD::Flag_sets_sign_flag, PD::Flag_clears_zero_flag, PD::Flag_clears_overflow_flag);
@ -13888,7 +13888,7 @@ instruct blsmskL_rReg_mem(rRegL dst, memory src, immL_M1 minus_1, rFlagsReg cr)
instruct blsmskL_rReg_rReg(rRegL dst, rRegL src, immL_M1 minus_1, rFlagsReg cr)
%{
match(Set dst (XorL (AddL src minus_1) src));
predicate(UseBMI1Instructions);
predicate(VM_Version::supports_bmi1() && VM_Version::supports_avx());
effect(KILL cr);
flag(PD::Flag_sets_sign_flag, PD::Flag_clears_zero_flag, PD::Flag_clears_overflow_flag);
@ -13904,7 +13904,7 @@ instruct blsmskL_rReg_rReg(rRegL dst, rRegL src, immL_M1 minus_1, rFlagsReg cr)
instruct blsrL_rReg_rReg(rRegL dst, rRegL src, immL_M1 minus_1, rFlagsReg cr)
%{
match(Set dst (AndL (AddL src minus_1) src) );
predicate(UseBMI1Instructions);
predicate(VM_Version::supports_bmi1() && VM_Version::supports_avx());
effect(KILL cr);
flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_clears_overflow_flag);
@ -13920,7 +13920,7 @@ instruct blsrL_rReg_rReg(rRegL dst, rRegL src, immL_M1 minus_1, rFlagsReg cr)
instruct blsrL_rReg_mem(rRegL dst, memory src, immL_M1 minus_1, rFlagsReg cr)
%{
match(Set dst (AndL (AddL (LoadL src) minus_1) (LoadL src)) );
predicate(UseBMI1Instructions);
predicate(VM_Version::supports_bmi1() && VM_Version::supports_avx());
effect(KILL cr);
flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_clears_overflow_flag);

23
src/hotspot/share/runtime/abstract_vm_version.hpp
View File

@ -45,19 +45,22 @@ class outputStream;
class stringStream;
enum class vmIntrinsicID;
#define SINGLE_INST_WARNING_MSG " instruction is not available on this CPU"
#define MULTI_INST_WARNING_MSG " instructions are not available on this CPU"
// Helper macro to test and set VM flag and corresponding cpu feature
#define CHECK_CPU_FEATURE(feature_test_fn, feature) \
if (feature_test_fn()) { \
if (FLAG_IS_DEFAULT(Use##feature)) { \
FLAG_SET_DEFAULT(Use##feature, true); \
} else if (!Use##feature) { \
clear_feature(CPU_##feature); \
#define CHECK_CPU_FEATURE(vmflag, feature_id, predicate, warning_msg) \
if (predicate) { \
if (FLAG_IS_DEFAULT(vmflag)) { \
FLAG_SET_DEFAULT(vmflag, true); \
} else if (!vmflag) { \
clear_feature(CPU_##feature_id); \
} \
} else if (Use##feature) { \
if (!FLAG_IS_DEFAULT(Use##feature)) { \
warning(#feature " instructions are not available on this CPU"); \
} else if (vmflag) { \
if (!FLAG_IS_DEFAULT(vmflag)) { \
warning(#feature_id warning_msg); \
} \
FLAG_SET_DEFAULT(Use##feature, false); \
FLAG_SET_DEFAULT(vmflag, false); \
}
// Abstract_VM_Version provides information about the VM.

12
test/hotspot/jtreg/compiler/arguments/TestUseCountTrailingZerosInstructionOnSupportedCPU.java
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2014, 2022, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2014, 2026, Oracle and/or its affiliates. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
@ -67,14 +67,14 @@ public class TestUseCountTrailingZerosInstructionOnSupportedCPU
TestUseCountTrailingZerosInstructionOnSupportedCPU.DISABLE_BMI);
/*
Verify that option could be turned on even if other BMI1
instructions were turned off. VM will be launched with following
Verify that option cannot be turned on when BMI1 instructions
are explicitly turned off. VM will be launched with following
options: -XX:-UseBMI1Instructions
-XX:+UseCountTrailingZerosInstruction -version
*/
CommandLineOptionTest.verifyOptionValueForSameVM(optionName, "true",
"Option 'UseCountTrailingZerosInstruction' should be able to "
+ "be turned on even if all BMI1 instructions are "
CommandLineOptionTest.verifyOptionValueForSameVM(optionName, "false",
"Option 'UseCountTrailingZerosInstruction' should have "
+ "'false' value if all BMI1 instructions are "
+ "disabled (-XX:-UseBMI1Instructions flag used)",
TestUseCountTrailingZerosInstructionOnSupportedCPU.DISABLE_BMI,
CommandLineOptionTest.prepareBooleanFlag(optionName, true));

48
test/hotspot/jtreg/compiler/cpuflags/CPUFeaturesClearTest.java
View File

@ -23,6 +23,7 @@
/*
* @test
* @bug 8364584 8381988
* @library /test/lib /
* @modules java.base/jdk.internal.misc
* java.management
@ -38,6 +39,7 @@
package compiler.cpuflags;
import java.util.List;
import java.util.Map;
import jdk.test.lib.process.OutputAnalyzer;
import jdk.test.lib.Platform;
@ -62,15 +64,23 @@ public class CPUFeaturesClearTest {
}
public void testX86Flags() throws Throwable {
Map<String, String> vmFlagToCpuFeatureMap = Map.of("UseCLMUL", "clmul",
"UseAES", "aes",
"UseFMA", "fma",
"UseCountLeadingZerosInstruction", "lzcnt",
"UseBMI1Instructions", "bmi1",
"UseBMI2Instructions", "bmi2",
"UsePopCountInstruction", "popcnt",
"UseSHA", "sha");
vmFlagToCpuFeatureMap.forEach((vmFlag, cpuFeature) -> {
try {
OutputAnalyzer outputAnalyzer = ProcessTools.executeTestJava(generateArgs(prepareBooleanFlag(vmFlag, false)));
outputAnalyzer.shouldNotMatch("[os,cpu] CPU: .* " + cpuFeature + ".*");
} catch (Exception e) {
throw new RuntimeException (e);
}
});
OutputAnalyzer outputAnalyzer;
String vmFlagsToTest[] = {"UseCLMUL", "UseAES", "UseFMA", "UseSHA"};
String cpuFeatures[] = {"clmul", "aes", "fma", "sha"};
for (int i = 0; i < vmFlagsToTest.length; i++) {
String vmFlag = vmFlagsToTest[i];
String cpuFeature = cpuFeatures[i];
outputAnalyzer = ProcessTools.executeTestJava(generateArgs(prepareBooleanFlag(vmFlag, false)));
outputAnalyzer.shouldNotMatch("[os,cpu] CPU: .* " + cpuFeatures[i] + ".*");
}
if (isCpuFeatureSupported("sse4")) {
outputAnalyzer = ProcessTools.executeTestJava(generateArgs(prepareNumericFlag("UseSSE", 3)));
outputAnalyzer.shouldNotMatch("[os,cpu] CPU: .* sse4.*");
@ -103,18 +113,20 @@ public class CPUFeaturesClearTest {
}
public void testAArch64Flags() throws Throwable {
OutputAnalyzer outputAnalyzer;
String vmFlagsToTest[] = {"UseCRC32", "UseLSE", "UseAES"};
String cpuFeatures[] = {"crc32", "lse", "aes"};
for (int i = 0; i < vmFlagsToTest.length; i++) {
String vmFlag = vmFlagsToTest[i];
String cpuFeature = cpuFeatures[i];
outputAnalyzer = ProcessTools.executeTestJava(generateArgs(prepareBooleanFlag(vmFlag, false)));
outputAnalyzer.shouldNotMatch("[os,cpu] CPU: .* " + cpuFeatures[i] + ".*");
}
Map<String, String> vmFlagToCpuFeatureMap = Map.of("UseCRC32", "crc32",
"UseLSE", "lse",
"UseAES", "aes");
vmFlagToCpuFeatureMap.forEach((vmFlag, cpuFeature) -> {
try {
OutputAnalyzer outputAnalyzer = ProcessTools.executeTestJava(generateArgs(prepareBooleanFlag(vmFlag, false)));
outputAnalyzer.shouldNotMatch("[os,cpu] CPU: .* " + cpuFeature + ".*");
} catch (Exception e) {
throw new RuntimeException(e);
}
});
// Disabling UseSHA should clear all shaXXX cpu features
outputAnalyzer = ProcessTools.executeTestJava(generateArgs(prepareBooleanFlag("UseSHA", false)));
OutputAnalyzer outputAnalyzer = ProcessTools.executeTestJava(generateArgs(prepareBooleanFlag("UseSHA", false)));
outputAnalyzer.shouldNotMatch("[os,cpu] CPU: .* sha1.*");
outputAnalyzer.shouldNotMatch("[os,cpu] CPU: .* sha256.*");
outputAnalyzer.shouldNotMatch("[os,cpu] CPU: .* sha3.*");

2
test/hotspot/jtreg/compiler/intrinsics/bmi/verifycode/AndnTestI.java
View File

@ -24,7 +24,7 @@
/*
* @test
* @bug 8031321
* @requires vm.flavor == "server" & !vm.graal.enabled
* @requires vm.flavor == "server" & !vm.graal.enabled & vm.cpu.features ~= ".*avx.*"
* @library /test/lib /
* @modules java.base/jdk.internal.misc
* java.management

2
test/hotspot/jtreg/compiler/intrinsics/bmi/verifycode/AndnTestL.java
View File

@ -24,7 +24,7 @@
/*
* @test
* @bug 8031321
* @requires vm.flavor == "server" & !vm.graal.enabled
* @requires vm.flavor == "server" & !vm.graal.enabled & vm.cpu.features ~= ".*avx.*"
* @library /test/lib /
* @modules java.base/jdk.internal.misc
* java.management

2
test/hotspot/jtreg/compiler/intrinsics/bmi/verifycode/BlsiTestI.java
View File

@ -24,7 +24,7 @@
/*
* @test
* @bug 8031321
* @requires vm.flavor == "server" & !vm.graal.enabled
* @requires vm.flavor == "server" & !vm.graal.enabled & vm.cpu.features ~= ".*avx.*"
* @library /test/lib /
* @modules java.base/jdk.internal.misc
* java.management

2
test/hotspot/jtreg/compiler/intrinsics/bmi/verifycode/BlsiTestL.java
View File

@ -24,7 +24,7 @@
/*
* @test
* @bug 8031321
* @requires vm.flavor == "server" & !vm.graal.enabled
* @requires vm.flavor == "server" & !vm.graal.enabled & vm.cpu.features ~= ".*avx.*"
* @library /test/lib /
* @modules java.base/jdk.internal.misc
* java.management

2
test/hotspot/jtreg/compiler/intrinsics/bmi/verifycode/BlsmskTestI.java
View File

@ -24,7 +24,7 @@
/*
* @test
* @bug 8031321
* @requires vm.flavor == "server" & !vm.graal.enabled
* @requires vm.flavor == "server" & !vm.graal.enabled & vm.cpu.features ~= ".*avx.*"
* @library /test/lib /
* @modules java.base/jdk.internal.misc
* java.management

2
test/hotspot/jtreg/compiler/intrinsics/bmi/verifycode/BlsmskTestL.java
View File

@ -24,7 +24,7 @@
/*
* @test
* @bug 8031321
* @requires vm.flavor == "server" & !vm.graal.enabled
* @requires vm.flavor == "server" & !vm.graal.enabled & vm.cpu.features ~= ".*avx.*"
* @library /test/lib /
* @modules java.base/jdk.internal.misc
* java.management

2
test/hotspot/jtreg/compiler/intrinsics/bmi/verifycode/BlsrTestI.java
View File

@ -24,7 +24,7 @@
/*
* @test
* @bug 8031321
* @requires vm.flavor == "server" & !vm.graal.enabled
* @requires vm.flavor == "server" & !vm.graal.enabled & vm.cpu.features ~= ".*avx.*"
* @library /test/lib /
* @modules java.base/jdk.internal.misc
* java.management

2
test/hotspot/jtreg/compiler/intrinsics/bmi/verifycode/BlsrTestL.java
View File

@ -24,7 +24,7 @@
/*
* @test
* @bug 8031321
* @requires vm.flavor == "server" & !vm.graal.enabled
* @requires vm.flavor == "server" & !vm.graal.enabled & vm.cpu.features ~= ".*avx.*"
* @library /test/lib /
* @modules java.base/jdk.internal.misc
* java.management

1
test/hotspot/jtreg/compiler/intrinsics/bmi/verifycode/BmiIntrinsicBase.java
View File

@ -36,6 +36,7 @@ import java.lang.reflect.Executable;
import java.lang.reflect.Method;
import java.util.concurrent.Callable;
import java.util.function.Function;
import java.util.List;
public class BmiIntrinsicBase extends CompilerWhiteBoxTest {