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8384963: C2: Incorrect uint constant match mishandles negative values in vectors
Reviewed-by: shade, epeter, erfang
This commit is contained in:
Jatin Bhateja
parent
52c76a2a59
commit
c690bfa36b
@ -2800,18 +2800,20 @@ static bool is_replicate_uint_constant(const Node* n) {
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return n->Opcode() == Op_Replicate &&
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n->in(1)->is_Con() &&
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n->in(1)->bottom_type()->isa_long() &&
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n->in(1)->bottom_type()->is_long()->get_con() <= 0xFFFFFFFFL;
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(julong)n->in(1)->bottom_type()->is_long()->get_con() <= 0xFFFFFFFFUL;
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}
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static bool has_vector_elements_fit_uint(Node* n) {
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auto is_lower_doubleword_mask_pattern = [](const Node* n) {
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return n->Opcode() == Op_AndV &&
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!n->is_predicated_vector() &&
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(is_replicate_uint_constant(n->in(1)) ||
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is_replicate_uint_constant(n->in(2)));
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};
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auto is_clear_upper_doubleword_uright_shift_pattern = [](const Node* n) {
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return n->Opcode() == Op_URShiftVL &&
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!n->is_predicated_vector() &&
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n->in(2)->Opcode() == Op_RShiftCntV && n->in(2)->in(1)->is_Con() &&
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n->in(2)->in(1)->bottom_type()->isa_int() &&
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n->in(2)->in(1)->bottom_type()->is_int()->get_con() >= 32;
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@ -2827,6 +2829,7 @@ static bool has_vector_elements_fit_int(Node* n) {
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auto is_clear_upper_doubleword_right_shift_pattern = [](const Node* n) {
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return n->Opcode() == Op_RShiftVL &&
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!n->is_predicated_vector() &&
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n->in(2)->Opcode() == Op_RShiftCntV && n->in(2)->in(1)->is_Con() &&
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n->in(2)->in(1)->bottom_type()->isa_int() &&
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n->in(2)->in(1)->bottom_type()->is_int()->get_con() >= 32;
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@ -2847,6 +2847,16 @@ public class IRNode {
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machOnlyNameRegex(VSTOREMASK_TRUECOUNT, "vstoremask_truecount_neon");
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}
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public static final String X86_VMULUDQ_REG = PREFIX + "X86_VMULUDQ_REG" + POSTFIX;
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static {
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machOnlyNameRegex(X86_VMULUDQ_REG, "vmuludq_reg");
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}
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public static final String X86_VMULDQ_REG = PREFIX + "X86_VMULDQ_REG" + POSTFIX;
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static {
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machOnlyNameRegex(X86_VMULDQ_REG, "vmuldq_reg");
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}
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public static final String X86_SCONV_D2I = PREFIX + "X86_SCONV_D2I" + POSTFIX;
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static {
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machOnlyNameRegex(X86_SCONV_D2I, "convD2I_reg_reg");
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@ -0,0 +1,352 @@
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/*
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* Copyright (c) 2026, Oracle and/or its affiliates. All rights reserved.
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* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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*
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* This code is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 only, as
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* published by the Free Software Foundation.
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*
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* This code is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* version 2 for more details (a copy is included in the LICENSE file that
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* accompanied this code).
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*
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* You should have received a copy of the GNU General Public License version
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* 2 along with this work; if not, write to the Free Software Foundation,
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* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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*
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* Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
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* or visit www.oracle.com if you need additional information or have any
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* questions.
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*/
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package compiler.vectorapi;
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import jdk.incubator.vector.*;
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import static jdk.incubator.vector.VectorOperators.AND;
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import static jdk.incubator.vector.VectorOperators.MUL;
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import static jdk.incubator.vector.VectorOperators.LSHR;
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import static jdk.incubator.vector.VectorOperators.ASHR;
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import compiler.lib.generators.Generators;
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import compiler.lib.ir_framework.*;
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import compiler.lib.verify.*;
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/*
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* @test
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* @bug 8384963
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* @key randomness
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* @summary C2: Incorrect uint constant match mishandles negative values in vectors
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* @modules jdk.incubator.vector
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* @library /test/lib /
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* @run driver compiler.vectorapi.TestVectorMulLongToSignedUnsignedInt
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*/
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public class TestVectorMulLongToSignedUnsignedInt {
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static final VectorSpecies<Long> SPECIES = LongVector.SPECIES_PREFERRED;
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static final int SIZE = SPECIES.length();
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private static final Generators RD = Generators.G;
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static final long[] src1 = new long[SIZE];
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static final long[] src2 = new long[SIZE];
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static long[] res = new long[SIZE];
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static final boolean[] mask_arr = new boolean[SIZE];
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static final VectorMask<Long> MASK;
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// Random compile-time-constant masks.
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static final long RAND_MASK1 = RD.longs().next();
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static final long RAND_MASK2 = RD.longs().next();
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// Random compile-time-constant shift count in [0, 63]. A shift >= 32 clears
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// the upper doubleword (fits uint); a smaller shift may not.
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static final int RAND_SHIFT1 = RD.ints().next() & 0x3F;
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// Random input arrays for the random-mask correctness cases.
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static final long[] rsrc1 = new long[SIZE];
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static final long[] rsrc2 = new long[SIZE];
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static {
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for (int i = 0; i < SIZE; i++) {
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src1[i] = 0x1_0000_0001L;
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src2[i] = 0x2_0000_0002L;
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mask_arr[i] = (i % 2) == 0;
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}
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MASK = VectorMask.fromArray(SPECIES, mask_arr, 0);
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RD.fill(RD.longs(), rsrc1);
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RD.fill(RD.longs(), rsrc2);
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}
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public static void main(String[] args) {
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TestFramework testFramework = new TestFramework();
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testFramework.setDefaultWarmup(10000)
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.addFlags("--add-modules=jdk.incubator.vector")
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.start();
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}
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// Case 1: Negative mask (-2L = 0xFFFF_FFFF_FFFF_FFFE).
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@Test
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@IR(counts = {IRNode.AND_VL, " >0 ", IRNode.MUL_VL, " >0 "}, applyIfCPUFeature = {"avx", "true"})
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@IR(failOn = {IRNode.X86_VMULUDQ_REG}, phase = CompilePhase.MATCHING, applyIfCPUFeature = {"avx", "true"})
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public static void testNegativeMask() {
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LongVector v1 = LongVector.fromArray(SPECIES, src1, 0);
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LongVector v2 = LongVector.fromArray(SPECIES, src2, 0);
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v1.lanewise(AND, -2L).lanewise(MUL, v2.lanewise(AND, -2L)).intoArray(res, 0);
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}
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@Run(test = "testNegativeMask")
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public void runNegativeMask() {
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testNegativeMask();
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long[] expected = new long[SPECIES.length()];
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for (int i = 0; i < SPECIES.length(); i++) {
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expected[i] = (src1[i] & -2L) * (src2[i] & -2L);
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}
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Verify.checkEQ(res, expected);
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}
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// Case 3: Mask = 0x1_0000_0000L (bit 32 set, exceeds uint range).
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@Test
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@IR(counts = {IRNode.AND_VL, " >0 ", IRNode.MUL_VL, " >0 "}, applyIfCPUFeature = {"avx", "true"})
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@IR(failOn = {IRNode.X86_VMULUDQ_REG}, phase = CompilePhase.MATCHING, applyIfCPUFeature = {"avx", "true"})
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public static void testBit32SetMask() {
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LongVector v1 = LongVector.fromArray(SPECIES, src1, 0);
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LongVector v2 = LongVector.fromArray(SPECIES, src2, 0);
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v1.lanewise(AND, 0x1_0000_0000L).lanewise(MUL, v2.lanewise(AND, 0x1_0000_0000L)).intoArray(res, 0);
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}
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@Run(test = "testBit32SetMask")
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public void runBit32SetMask() {
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testBit32SetMask();
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long[] expected = new long[SPECIES.length()];
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for (int i = 0; i < SPECIES.length(); i++) {
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expected[i] = (src1[i] & 0x1_0000_0000L) * (src2[i] & 0x1_0000_0000L);
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}
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Verify.checkEQ(res, expected);
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}
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// Case 4: Mask = Long.MIN_VALUE (0x8000_0000_0000_0000).
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@Test
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@IR(counts = {IRNode.AND_VL, " >0 ", IRNode.MUL_VL, " >0 "}, applyIfCPUFeature = {"avx", "true"})
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@IR(failOn = {IRNode.X86_VMULUDQ_REG}, phase = CompilePhase.MATCHING, applyIfCPUFeature = {"avx", "true"})
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public static void testMinValueMask() {
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LongVector v1 = LongVector.fromArray(SPECIES, src1, 0);
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LongVector v2 = LongVector.fromArray(SPECIES, src2, 0);
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v1.lanewise(AND, Long.MIN_VALUE).lanewise(MUL, v2.lanewise(AND, Long.MIN_VALUE)).intoArray(res, 0);
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}
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@Run(test = "testMinValueMask")
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public void runMinValueMask() {
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testMinValueMask();
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long[] expected = new long[SPECIES.length()];
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for (int i = 0; i < SPECIES.length(); i++) {
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expected[i] = (src1[i] & Long.MIN_VALUE) * (src2[i] & Long.MIN_VALUE);
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}
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Verify.checkEQ(res, expected);
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}
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// Case 5: Mask = 0xFFFF_FFFFL (exactly uint max, boundary valid case).
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@Test
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@IR(counts = {IRNode.MUL_VL, " >0 "}, applyIfCPUFeature = {"avx", "true"})
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@IR(counts = {IRNode.X86_VMULUDQ_REG, " >0 "}, phase = CompilePhase.MATCHING, applyIfCPUFeature = {"avx", "true"})
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public static void testUintMaxMask() {
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LongVector v1 = LongVector.fromArray(SPECIES, src1, 0);
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LongVector v2 = LongVector.fromArray(SPECIES, src2, 0);
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v1.lanewise(AND, 0xFFFF_FFFFL).lanewise(MUL, v2.lanewise(AND, 0xFFFF_FFFFL)).intoArray(res, 0);
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}
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@Run(test = "testUintMaxMask")
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public void runUintMaxMask() {
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testUintMaxMask();
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long[] expected = new long[SPECIES.length()];
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for (int i = 0; i < SPECIES.length(); i++) {
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expected[i] = (src1[i] & 0xFFFF_FFFFL) * (src2[i] & 0xFFFF_FFFFL);
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}
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Verify.checkEQ(res, expected);
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}
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// Case 6: Small mask (0xFFFFL), clearly fits in uint.
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@Test
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@IR(counts = {IRNode.MUL_VL, " >0 "}, applyIfCPUFeature = {"avx", "true"})
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@IR(counts = {IRNode.X86_VMULUDQ_REG, " >0 "}, phase = CompilePhase.MATCHING, applyIfCPUFeature = {"avx", "true"})
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public static void testSmallMask() {
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LongVector v1 = LongVector.fromArray(SPECIES, src1, 0);
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LongVector v2 = LongVector.fromArray(SPECIES, src2, 0);
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v1.lanewise(AND, 0xFFFFL).lanewise(MUL, v2.lanewise(AND, 0xFFFFL)).intoArray(res, 0);
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}
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@Run(test = "testSmallMask")
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public void runSmallMask() {
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testSmallMask();
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long[] expected = new long[SPECIES.length()];
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for (int i = 0; i < SPECIES.length(); i++) {
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expected[i] = (src1[i] & 0xFFFFL) * (src2[i] & 0xFFFFL);
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}
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Verify.checkEQ(res, expected);
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}
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// Case 7: URShift by 32 clears upper doubleword.
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@Test
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@IR(counts = {IRNode.MUL_VL, " >0 ", IRNode.URSHIFT_VL, " >0 "}, applyIfCPUFeature = {"avx", "true"})
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@IR(counts = {IRNode.X86_VMULUDQ_REG, " >0 "}, phase = CompilePhase.MATCHING, applyIfCPUFeature = {"avx", "true"})
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public static void testURShift32() {
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LongVector v1 = LongVector.fromArray(SPECIES, src1, 0);
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LongVector v2 = LongVector.fromArray(SPECIES, src2, 0);
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v1.lanewise(LSHR, 32).lanewise(MUL, v2.lanewise(LSHR, 32)).intoArray(res, 0);
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}
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@Run(test = "testURShift32")
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public void runURShift32() {
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testURShift32();
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long[] expected = new long[SPECIES.length()];
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for (int i = 0; i < SPECIES.length(); i++) {
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expected[i] = (src1[i] >>> 32) * (src2[i] >>> 32);
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}
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Verify.checkEQ(res, expected);
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}
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// Case 8: Asymmetric — one input valid uint mask, other negative mask.
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@Test
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@IR(counts = {IRNode.AND_VL, " >0 ", IRNode.MUL_VL, " >0 "}, applyIfCPUFeature = {"avx", "true"})
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@IR(failOn = {IRNode.X86_VMULUDQ_REG}, phase = CompilePhase.MATCHING, applyIfCPUFeature = {"avx", "true"})
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public static void testAsymmetricMask() {
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LongVector v1 = LongVector.fromArray(SPECIES, src1, 0);
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LongVector v2 = LongVector.fromArray(SPECIES, src2, 0);
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v1.lanewise(AND, 0xFFFF_FFFFL).lanewise(MUL, v2.lanewise(AND, -2L)).intoArray(res, 0);
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}
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@Run(test = "testAsymmetricMask")
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public void runAsymmetricMask() {
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testAsymmetricMask();
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long[] expected = new long[SPECIES.length()];
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for (int i = 0; i < SPECIES.length(); i++) {
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expected[i] = (src1[i] & 0xFFFF_FFFFL) * (src2[i] & -2L);
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}
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Verify.checkEQ(res, expected);
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}
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// Case 9: Mixed — one input URShift (valid), other negative mask (invalid).
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// Note: -2L is used (not -1L) since AND with -1L is identity and gets folded.
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@Test
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@IR(counts = {IRNode.URSHIFT_VL, " >0 ", IRNode.AND_VL, " >0 ", IRNode.MUL_VL, " >0 "}, applyIfCPUFeature = {"avx", "true"})
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@IR(failOn = {IRNode.X86_VMULUDQ_REG}, phase = CompilePhase.MATCHING, applyIfCPUFeature = {"avx", "true"})
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public static void testMixedURShiftAndNegMask() {
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LongVector v1 = LongVector.fromArray(SPECIES, src1, 0);
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LongVector v2 = LongVector.fromArray(SPECIES, src2, 0);
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v1.lanewise(LSHR, 32).lanewise(MUL, v2.lanewise(AND, -2L)).intoArray(res, 0);
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}
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@Run(test = "testMixedURShiftAndNegMask")
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public void runMixedURShiftAndNegMask() {
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testMixedURShiftAndNegMask();
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long[] expected = new long[SPECIES.length()];
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for (int i = 0; i < SPECIES.length(); i++) {
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expected[i] = (src1[i] >>> 32) * (src2[i] & -2L);
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}
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Verify.checkEQ(res, expected);
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}
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// Case 10: Predicated AndV (uint path). Inactive lanes preserves destination with non-zero upper 32 bits.
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@Test
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@IR(counts = {IRNode.AND_VL, " >0 ", IRNode.MUL_VL, " >0 "}, applyIfCPUFeature = {"avx512f", "true"})
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@IR(failOn = {IRNode.X86_VMULUDQ_REG}, phase = CompilePhase.MATCHING, applyIfCPUFeature = {"avx512f", "true"})
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public static void testPredicatedAndMask() {
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LongVector v1 = LongVector.fromArray(SPECIES, src1, 0);
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LongVector v2 = LongVector.fromArray(SPECIES, src2, 0);
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v1.lanewise(AND, 0xFFFF_FFFFL, MASK).lanewise(MUL, v2.lanewise(AND, 0xFFFF_FFFFL, MASK)).intoArray(res, 0);
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}
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@Run(test = "testPredicatedAndMask")
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public void runPredicatedAndMask() {
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testPredicatedAndMask();
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long[] expected = new long[SIZE];
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for (int i = 0; i < SIZE; i++) {
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long a = mask_arr[i] ? (src1[i] & 0xFFFF_FFFFL) : src1[i];
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long b = mask_arr[i] ? (src2[i] & 0xFFFF_FFFFL) : src2[i];
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expected[i] = a * b;
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}
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Verify.checkEQ(res, expected);
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}
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// Case 11: Predicated URShiftVL by 32 (uint path). Inactive lanes preserves destination with non-zero upper 32 bits.
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@Test
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@IR(counts = {IRNode.URSHIFT_VL, " >0 ", IRNode.MUL_VL, " >0 "}, applyIfCPUFeature = {"avx512f", "true"})
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@IR(failOn = {IRNode.X86_VMULUDQ_REG}, phase = CompilePhase.MATCHING, applyIfCPUFeature = {"avx512f", "true"})
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public static void testPredicatedURShift32() {
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LongVector v1 = LongVector.fromArray(SPECIES, src1, 0);
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LongVector v2 = LongVector.fromArray(SPECIES, src2, 0);
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v1.lanewise(LSHR, 32, MASK).lanewise(MUL, v2.lanewise(LSHR, 32, MASK)).intoArray(res, 0);
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}
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@Run(test = "testPredicatedURShift32")
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public void runPredicatedURShift32() {
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testPredicatedURShift32();
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long[] expected = new long[SIZE];
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for (int i = 0; i < SIZE; i++) {
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long a = mask_arr[i] ? (src1[i] >>> 32) : src1[i];
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long b = mask_arr[i] ? (src2[i] >>> 32) : src2[i];
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expected[i] = a * b;
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}
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Verify.checkEQ(res, expected);
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}
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// Case 12: Predicated RShiftVL (arithmetic) by 32.
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@Test
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@IR(counts = {IRNode.RSHIFT_VL, " >0 ", IRNode.MUL_VL, " >0 "}, applyIfCPUFeature = {"avx512f", "true"})
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@IR(failOn = {IRNode.X86_VMULDQ_REG}, phase = CompilePhase.MATCHING, applyIfCPUFeature = {"avx512f", "true"})
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public static void testPredicatedRShift32() {
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LongVector v1 = LongVector.fromArray(SPECIES, src1, 0);
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LongVector v2 = LongVector.fromArray(SPECIES, src2, 0);
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v1.lanewise(ASHR, 32, MASK).lanewise(MUL, v2.lanewise(ASHR, 32, MASK)).intoArray(res, 0);
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}
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@Run(test = "testPredicatedRShift32")
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public void runPredicatedRShift32() {
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testPredicatedRShift32();
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long[] expected = new long[SIZE];
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for (int i = 0; i < SIZE; i++) {
|
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long a = mask_arr[i] ? (src1[i] >> 32) : src1[i];
|
||||
long b = mask_arr[i] ? (src2[i] >> 32) : src2[i];
|
||||
expected[i] = a * b;
|
||||
}
|
||||
Verify.checkEQ(res, expected);
|
||||
}
|
||||
|
||||
// Random-constant correctness cases with no IR rules.
|
||||
|
||||
// Case 13: AND pattern with random masks on both inputs.
|
||||
@Test
|
||||
public static void testRandomAndMasks() {
|
||||
LongVector v1 = LongVector.fromArray(SPECIES, rsrc1, 0);
|
||||
LongVector v2 = LongVector.fromArray(SPECIES, rsrc2, 0);
|
||||
v1.lanewise(AND, RAND_MASK1).lanewise(MUL, v2.lanewise(AND, RAND_MASK2)).intoArray(res, 0);
|
||||
}
|
||||
|
||||
@Run(test = "testRandomAndMasks")
|
||||
public void runRandomAndMasks() {
|
||||
testRandomAndMasks();
|
||||
long[] expected = new long[SIZE];
|
||||
for (int i = 0; i < SIZE; i++) {
|
||||
expected[i] = (rsrc1[i] & RAND_MASK1) * (rsrc2[i] & RAND_MASK2);
|
||||
}
|
||||
Verify.checkEQ(res, expected);
|
||||
}
|
||||
|
||||
// Case 14: URShiftV pattern with a random shift count on both inputs.
|
||||
@Test
|
||||
public static void testRandomURShift() {
|
||||
LongVector v1 = LongVector.fromArray(SPECIES, rsrc1, 0);
|
||||
LongVector v2 = LongVector.fromArray(SPECIES, rsrc2, 0);
|
||||
v1.lanewise(LSHR, RAND_SHIFT1).lanewise(MUL, v2.lanewise(LSHR, RAND_SHIFT1)).intoArray(res, 0);
|
||||
}
|
||||
|
||||
@Run(test = "testRandomURShift")
|
||||
public void runRandomURShift() {
|
||||
testRandomURShift();
|
||||
long[] expected = new long[SIZE];
|
||||
for (int i = 0; i < SIZE; i++) {
|
||||
expected[i] = (rsrc1[i] >>> RAND_SHIFT1) * (rsrc2[i] >>> RAND_SHIFT1);
|
||||
}
|
||||
Verify.checkEQ(res, expected);
|
||||
}
|
||||
}
|
||||
Loading…
x
Reference in New Issue
Block a user