mirror of
https://github.com/openjdk/jdk.git
synced 2026-05-11 14:11:36 +00:00
8248414: AArch64: Remove uses of long and unsigned long ints
Reviewed-by: adinn, dholmes
This commit is contained in:
Andrew Haley
parent
ec074011a4
commit
c7d84850bf
@ -1,8 +1,8 @@
|
||||
import random
|
||||
|
||||
AARCH64_AS = "<PATH-TO-AS>"
|
||||
AARCH64_OBJDUMP = "<PATH-TO-OBJDUMP>"
|
||||
AARCH64_OBJCOPY = "<PATH-TO-OBJCOPY>"
|
||||
AARCH64_AS = "as"
|
||||
AARCH64_OBJDUMP = "objdump"
|
||||
AARCH64_OBJCOPY = "objcopy"
|
||||
|
||||
class Operand(object):
|
||||
|
||||
@ -348,7 +348,7 @@ class LogicalImmOp(AddSubImmOp):
|
||||
+ ', #0x%x' % self.immed)
|
||||
|
||||
def cstr(self):
|
||||
return super(AddSubImmOp, self).cstr() + "l);"
|
||||
return super(AddSubImmOp, self).cstr() + "ll);"
|
||||
|
||||
class MultiOp():
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -1,4 +1,4 @@
|
||||
dnl Copyright (c) 2014, Red Hat Inc. All rights reserved.
|
||||
dnl Copyright (c) 2014, 2020, Red Hat Inc. All rights reserved.
|
||||
dnl DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
|
||||
dnl
|
||||
dnl This code is free software; you can redistribute it and/or modify it
|
||||
@ -23,12 +23,12 @@ dnl
|
||||
dnl Process this file with m4 aarch64_ad.m4 to generate the arithmetic
|
||||
dnl and shift patterns patterns used in aarch64.ad.
|
||||
dnl
|
||||
// BEGIN This section of the file is automatically generated. Do not edit --------------
|
||||
dnl
|
||||
define(`ORL2I', `ifelse($1,I,orL2I)')
|
||||
dnl
|
||||
define(`BASE_SHIFT_INSN',
|
||||
`
|
||||
`// This pattern is automatically generated from aarch64_ad.m4
|
||||
// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
|
||||
instruct $2$1_reg_$4_reg(iReg$1NoSp dst,
|
||||
iReg$1`'ORL2I($1) src1, iReg$1`'ORL2I($1) src2,
|
||||
immI src3, rFlagsReg cr) %{
|
||||
@ -46,9 +46,11 @@ instruct $2$1_reg_$4_reg(iReg$1NoSp dst,
|
||||
%}
|
||||
|
||||
ins_pipe(ialu_reg_reg_shift);
|
||||
%}')dnl
|
||||
%}
|
||||
')dnl
|
||||
define(`BASE_INVERTED_INSN',
|
||||
`
|
||||
`// This pattern is automatically generated from aarch64_ad.m4
|
||||
// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
|
||||
instruct $2$1_reg_not_reg(iReg$1NoSp dst,
|
||||
iReg$1`'ORL2I($1) src1, iReg$1`'ORL2I($1) src2, imm$1_M1 m1,
|
||||
rFlagsReg cr) %{
|
||||
@ -68,9 +70,11 @@ dnl into this canonical form.
|
||||
%}
|
||||
|
||||
ins_pipe(ialu_reg_reg);
|
||||
%}')dnl
|
||||
%}
|
||||
')dnl
|
||||
define(`INVERTED_SHIFT_INSN',
|
||||
`
|
||||
`// This pattern is automatically generated from aarch64_ad.m4
|
||||
// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
|
||||
instruct $2$1_reg_$4_not_reg(iReg$1NoSp dst,
|
||||
iReg$1`'ORL2I($1) src1, iReg$1`'ORL2I($1) src2,
|
||||
immI src3, imm$1_M1 src4, rFlagsReg cr) %{
|
||||
@ -91,9 +95,12 @@ dnl into this canonical form.
|
||||
%}
|
||||
|
||||
ins_pipe(ialu_reg_reg_shift);
|
||||
%}')dnl
|
||||
%}
|
||||
')dnl
|
||||
define(`NOT_INSN',
|
||||
`instruct reg$1_not_reg(iReg$1NoSp dst,
|
||||
`// This pattern is automatically generated from aarch64_ad.m4
|
||||
// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
|
||||
instruct reg$1_not_reg(iReg$1NoSp dst,
|
||||
iReg$1`'ORL2I($1) src1, imm$1_M1 m1,
|
||||
rFlagsReg cr) %{
|
||||
match(Set dst (Xor$1 src1 m1));
|
||||
@ -108,7 +115,8 @@ define(`NOT_INSN',
|
||||
%}
|
||||
|
||||
ins_pipe(ialu_reg);
|
||||
%}')dnl
|
||||
%}
|
||||
')dnl
|
||||
dnl
|
||||
define(`BOTH_SHIFT_INSNS',
|
||||
`BASE_SHIFT_INSN(I, $1, ifelse($2,andr,andw,$2w), $3, $4)
|
||||
@ -120,7 +128,7 @@ BASE_INVERTED_INSN(L, $1, $2, $3, $4)')dnl
|
||||
dnl
|
||||
define(`BOTH_INVERTED_SHIFT_INSNS',
|
||||
`INVERTED_SHIFT_INSN(I, $1, $2w, $3, $4, ~0, int)
|
||||
INVERTED_SHIFT_INSN(L, $1, $2, $3, $4, ~0l, long)')dnl
|
||||
INVERTED_SHIFT_INSN(L, $1, $2, $3, $4, ~0l, jlong)')dnl
|
||||
dnl
|
||||
define(`ALL_SHIFT_KINDS',
|
||||
`BOTH_SHIFT_INSNS($1, $2, URShift, LSR)
|
||||
@ -147,8 +155,10 @@ ALL_SHIFT_KINDS(Add, add)
|
||||
ALL_SHIFT_KINDS(Sub, sub)
|
||||
dnl
|
||||
dnl EXTEND mode, rshift_op, src, lshift_count, rshift_count
|
||||
define(`EXTEND', `($2$1 (LShift$1 $3 $4) $5)')
|
||||
define(`BFM_INSN',`
|
||||
define(`EXTEND', `($2$1 (LShift$1 $3 $4) $5)') dnl
|
||||
define(`BFM_INSN',`// This pattern is automatically generated from aarch64_ad.m4
|
||||
// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
|
||||
|
||||
// Shift Left followed by Shift Right.
|
||||
// This idiom is used by the compiler for the i2b bytecode etc.
|
||||
instruct $4$1(iReg$1NoSp dst, iReg$1`'ORL2I($1) src, immI lshift_count, immI rshift_count)
|
||||
@ -167,7 +177,8 @@ instruct $4$1(iReg$1NoSp dst, iReg$1`'ORL2I($1) src, immI lshift_count, immI rsh
|
||||
%}
|
||||
|
||||
ins_pipe(ialu_reg_shift);
|
||||
%}')
|
||||
%}
|
||||
')
|
||||
BFM_INSN(L, 63, RShift, sbfm)
|
||||
BFM_INSN(I, 31, RShift, sbfmw)
|
||||
BFM_INSN(L, 63, URShift, ubfm)
|
||||
@ -175,7 +186,9 @@ BFM_INSN(I, 31, URShift, ubfmw)
|
||||
dnl
|
||||
// Bitfield extract with shift & mask
|
||||
define(`BFX_INSN',
|
||||
`instruct $3$1(iReg$1NoSp dst, iReg$1`'ORL2I($1) src, immI rshift, imm$1_bitmask mask)
|
||||
`// This pattern is automatically generated from aarch64_ad.m4
|
||||
// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
|
||||
instruct $3$1(iReg$1NoSp dst, iReg$1`'ORL2I($1) src, immI rshift, imm$1_bitmask mask)
|
||||
%{
|
||||
match(Set dst (And$1 ($2$1 src rshift) mask));
|
||||
// Make sure we are not going to exceed what $3 can do.
|
||||
@ -185,16 +198,20 @@ define(`BFX_INSN',
|
||||
format %{ "$3 $dst, $src, $rshift, $mask" %}
|
||||
ins_encode %{
|
||||
int rshift = $rshift$$constant & $4;
|
||||
long mask = $mask$$constant;
|
||||
intptr_t mask = $mask$$constant;
|
||||
int width = exact_log2$6(mask+1);
|
||||
__ $3(as_Register($dst$$reg),
|
||||
as_Register($src$$reg), rshift, width);
|
||||
%}
|
||||
ins_pipe(ialu_reg_shift);
|
||||
%}')
|
||||
%}
|
||||
')
|
||||
BFX_INSN(I, URShift, ubfxw, 31, int)
|
||||
BFX_INSN(L, URShift, ubfx, 63, long, _long)
|
||||
|
||||
// This pattern is automatically generated from aarch64_ad.m4
|
||||
// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
|
||||
|
||||
// We can use ubfx when extending an And with a mask when we know mask
|
||||
// is positive. We know that because immI_bitmask guarantees it.
|
||||
instruct ubfxIConvI2L(iRegLNoSp dst, iRegIorL2I src, immI rshift, immI_bitmask mask)
|
||||
@ -207,7 +224,7 @@ instruct ubfxIConvI2L(iRegLNoSp dst, iRegIorL2I src, immI rshift, immI_bitmask m
|
||||
format %{ "ubfx $dst, $src, $rshift, $mask" %}
|
||||
ins_encode %{
|
||||
int rshift = $rshift$$constant & 31;
|
||||
long mask = $mask$$constant;
|
||||
intptr_t mask = $mask$$constant;
|
||||
int width = exact_log2(mask+1);
|
||||
__ ubfx(as_Register($dst$$reg),
|
||||
as_Register($src$$reg), rshift, width);
|
||||
@ -215,10 +232,12 @@ instruct ubfxIConvI2L(iRegLNoSp dst, iRegIorL2I src, immI rshift, immI_bitmask m
|
||||
ins_pipe(ialu_reg_shift);
|
||||
%}
|
||||
|
||||
define(`UBFIZ_INSN',
|
||||
define(`UBFIZ_INSN', `// This pattern is automatically generated from aarch64_ad.m4
|
||||
// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
|
||||
|
||||
// We can use ubfiz when masking by a positive number and then left shifting the result.
|
||||
// We know that the mask is positive because imm$1_bitmask guarantees it.
|
||||
`instruct $2$1(iReg$1NoSp dst, iReg$1`'ORL2I($1) src, immI lshift, imm$1_bitmask mask)
|
||||
instruct $2$1(iReg$1NoSp dst, iReg$1`'ORL2I($1) src, immI lshift, imm$1_bitmask mask)
|
||||
%{
|
||||
match(Set dst (LShift$1 (And$1 src mask) lshift));
|
||||
predicate((exact_log2$5(n->in(1)->in(2)->get_$4() + 1) + (n->in(2)->get_int() & $3)) <= ($3 + 1));
|
||||
@ -227,16 +246,20 @@ define(`UBFIZ_INSN',
|
||||
format %{ "$2 $dst, $src, $lshift, $mask" %}
|
||||
ins_encode %{
|
||||
int lshift = $lshift$$constant & $3;
|
||||
long mask = $mask$$constant;
|
||||
intptr_t mask = $mask$$constant;
|
||||
int width = exact_log2$5(mask+1);
|
||||
__ $2(as_Register($dst$$reg),
|
||||
as_Register($src$$reg), lshift, width);
|
||||
%}
|
||||
ins_pipe(ialu_reg_shift);
|
||||
%}')
|
||||
%}
|
||||
')
|
||||
UBFIZ_INSN(I, ubfizw, 31, int)
|
||||
UBFIZ_INSN(L, ubfiz, 63, long, _long)
|
||||
|
||||
// This pattern is automatically generated from aarch64_ad.m4
|
||||
// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
|
||||
|
||||
// If there is a convert I to L block between and AndI and a LShiftL, we can also match ubfiz
|
||||
instruct ubfizIConvI2L(iRegLNoSp dst, iRegIorL2I src, immI lshift, immI_bitmask mask)
|
||||
%{
|
||||
@ -247,7 +270,7 @@ instruct ubfizIConvI2L(iRegLNoSp dst, iRegIorL2I src, immI lshift, immI_bitmask
|
||||
format %{ "ubfiz $dst, $src, $lshift, $mask" %}
|
||||
ins_encode %{
|
||||
int lshift = $lshift$$constant & 63;
|
||||
long mask = $mask$$constant;
|
||||
intptr_t mask = $mask$$constant;
|
||||
int width = exact_log2(mask+1);
|
||||
__ ubfiz(as_Register($dst$$reg),
|
||||
as_Register($src$$reg), lshift, width);
|
||||
@ -255,10 +278,12 @@ instruct ubfizIConvI2L(iRegLNoSp dst, iRegIorL2I src, immI lshift, immI_bitmask
|
||||
ins_pipe(ialu_reg_shift);
|
||||
%}
|
||||
|
||||
// Rotations
|
||||
|
||||
define(`EXTRACT_INSN',
|
||||
`instruct extr$3$1(iReg$1NoSp dst, iReg$1`'ORL2I($1) src1, iReg$1`'ORL2I($1) src2, immI lshift, immI rshift, rFlagsReg cr)
|
||||
// Rotations dnl
|
||||
define(`EXTRACT_INSN',`
|
||||
// This pattern is automatically generated from aarch64_ad.m4
|
||||
// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
|
||||
instruct extr$3$1(iReg$1NoSp dst, iReg$1`'ORL2I($1) src1, iReg$1`'ORL2I($1) src2, immI lshift, immI rshift, rFlagsReg cr)
|
||||
%{
|
||||
match(Set dst ($3$1 (LShift$1 src1 lshift) (URShift$1 src2 rshift)));
|
||||
predicate(0 == (((n->in(1)->in(2)->get_int() & $2) + (n->in(2)->in(2)->get_int() & $2)) & $2));
|
||||
@ -277,9 +302,10 @@ EXTRACT_INSN(L, 63, Or, extr)
|
||||
EXTRACT_INSN(I, 31, Or, extrw)
|
||||
EXTRACT_INSN(L, 63, Add, extr)
|
||||
EXTRACT_INSN(I, 31, Add, extrw)
|
||||
define(`ROL_EXPAND', `
|
||||
// $2 expander
|
||||
define(`ROL_EXPAND', `// This pattern is automatically generated from aarch64_ad.m4
|
||||
// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
|
||||
|
||||
// $2 expander
|
||||
instruct $2$1_rReg(iReg$1NoSp dst, iReg$1 src, iRegI shift, rFlagsReg cr)
|
||||
%{
|
||||
effect(DEF dst, USE src, USE shift);
|
||||
@ -292,10 +318,12 @@ instruct $2$1_rReg(iReg$1NoSp dst, iReg$1 src, iRegI shift, rFlagsReg cr)
|
||||
rscratch1);
|
||||
%}
|
||||
ins_pipe(ialu_reg_reg_vshift);
|
||||
%}')dnl
|
||||
define(`ROR_EXPAND', `
|
||||
// $2 expander
|
||||
%}
|
||||
')
|
||||
define(`ROR_EXPAND', `// This pattern is automatically generated from aarch64_ad.m4
|
||||
// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
|
||||
|
||||
// $2 expander
|
||||
instruct $2$1_rReg(iReg$1NoSp dst, iReg$1 src, iRegI shift, rFlagsReg cr)
|
||||
%{
|
||||
effect(DEF dst, USE src, USE shift);
|
||||
@ -307,8 +335,10 @@ instruct $2$1_rReg(iReg$1NoSp dst, iReg$1 src, iRegI shift, rFlagsReg cr)
|
||||
as_Register($shift$$reg));
|
||||
%}
|
||||
ins_pipe(ialu_reg_reg_vshift);
|
||||
%}')dnl
|
||||
define(ROL_INSN, `
|
||||
%}
|
||||
')dnl
|
||||
define(ROL_INSN, `// This pattern is automatically generated from aarch64_ad.m4
|
||||
// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
|
||||
instruct $3$1_rReg_Var_C$2(iReg$1NoSp dst, iReg$1 src, iRegI shift, immI$2 c$2, rFlagsReg cr)
|
||||
%{
|
||||
match(Set dst (Or$1 (LShift$1 src shift) (URShift$1 src (SubI c$2 shift))));
|
||||
@ -316,8 +346,10 @@ instruct $3$1_rReg_Var_C$2(iReg$1NoSp dst, iReg$1 src, iRegI shift, immI$2 c$2,
|
||||
expand %{
|
||||
$3$1_rReg(dst, src, shift, cr);
|
||||
%}
|
||||
%}')dnl
|
||||
define(ROR_INSN, `
|
||||
%}
|
||||
')dnl
|
||||
define(ROR_INSN, `// This pattern is automatically generated from aarch64_ad.m4
|
||||
// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
|
||||
instruct $3$1_rReg_Var_C$2(iReg$1NoSp dst, iReg$1 src, iRegI shift, immI$2 c$2, rFlagsReg cr)
|
||||
%{
|
||||
match(Set dst (Or$1 (URShift$1 src shift) (LShift$1 src (SubI c$2 shift))));
|
||||
@ -325,7 +357,8 @@ instruct $3$1_rReg_Var_C$2(iReg$1NoSp dst, iReg$1 src, iRegI shift, immI$2 c$2,
|
||||
expand %{
|
||||
$3$1_rReg(dst, src, shift, cr);
|
||||
%}
|
||||
%}')dnl
|
||||
%}
|
||||
')dnl
|
||||
ROL_EXPAND(L, rol, rorv)
|
||||
ROL_EXPAND(I, rol, rorvw)
|
||||
ROL_INSN(L, _64, rol)
|
||||
@ -342,6 +375,8 @@ ROR_INSN(I, 0, ror)
|
||||
// Add/subtract (extended)
|
||||
dnl ADD_SUB_EXTENDED(mode, size, add node, shift node, insn, shift type, wordsize
|
||||
define(`ADD_SUB_CONV', `
|
||||
// This pattern is automatically generated from aarch64_ad.m4
|
||||
// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
|
||||
instruct $3Ext$1(iReg$2NoSp dst, iReg$2`'ORL2I($2) src1, iReg$1`'ORL2I($1) src2, rFlagsReg cr)
|
||||
%{
|
||||
match(Set dst ($3$2 src1 (ConvI2L src2)));
|
||||
@ -354,10 +389,12 @@ instruct $3Ext$1(iReg$2NoSp dst, iReg$2`'ORL2I($2) src1, iReg$1`'ORL2I($1) src2,
|
||||
%}
|
||||
ins_pipe(ialu_reg_reg);
|
||||
%}')dnl
|
||||
ADD_SUB_CONV(I,L,Add,add,sxtw);
|
||||
ADD_SUB_CONV(I,L,Sub,sub,sxtw);
|
||||
ADD_SUB_CONV(I,L,Add,add,sxtw)
|
||||
ADD_SUB_CONV(I,L,Sub,sub,sxtw)
|
||||
dnl
|
||||
define(`ADD_SUB_EXTENDED', `
|
||||
// This pattern is automatically generated from aarch64_ad.m4
|
||||
// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
|
||||
instruct $3Ext$1_$6(iReg$1NoSp dst, iReg$1`'ORL2I($1) src1, iReg$1`'ORL2I($1) src2, immI_`'eval($7-$2) lshift, immI_`'eval($7-$2) rshift, rFlagsReg cr)
|
||||
%{
|
||||
match(Set dst ($3$1 src1 EXTEND($1, $4, src2, lshift, rshift)));
|
||||
@ -369,7 +406,7 @@ instruct $3Ext$1_$6(iReg$1NoSp dst, iReg$1`'ORL2I($1) src1, iReg$1`'ORL2I($1) sr
|
||||
as_Register($src2$$reg), ext::$6);
|
||||
%}
|
||||
ins_pipe(ialu_reg_reg);
|
||||
%}')
|
||||
%}')dnl
|
||||
ADD_SUB_EXTENDED(I,16,Add,RShift,add,sxth,32)
|
||||
ADD_SUB_EXTENDED(I,8,Add,RShift,add,sxtb,32)
|
||||
ADD_SUB_EXTENDED(I,8,Add,URShift,add,uxtb,32)
|
||||
@ -379,7 +416,8 @@ ADD_SUB_EXTENDED(L,8,Add,RShift,add,sxtb,64)
|
||||
ADD_SUB_EXTENDED(L,8,Add,URShift,add,uxtb,64)
|
||||
dnl
|
||||
dnl ADD_SUB_ZERO_EXTEND(mode, size, add node, insn, shift type)
|
||||
define(`ADD_SUB_ZERO_EXTEND', `
|
||||
define(`ADD_SUB_ZERO_EXTEND', `// This pattern is automatically generated from aarch64_ad.m4
|
||||
// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
|
||||
instruct $3Ext$1_$5_and(iReg$1NoSp dst, iReg$1`'ORL2I($1) src1, iReg$1`'ORL2I($1) src2, imm$1_$2 mask, rFlagsReg cr)
|
||||
%{
|
||||
match(Set dst ($3$1 src1 (And$1 src2 mask)));
|
||||
@ -391,7 +429,8 @@ instruct $3Ext$1_$5_and(iReg$1NoSp dst, iReg$1`'ORL2I($1) src1, iReg$1`'ORL2I($1
|
||||
as_Register($src2$$reg), ext::$5);
|
||||
%}
|
||||
ins_pipe(ialu_reg_reg);
|
||||
%}')
|
||||
%}
|
||||
')
|
||||
dnl
|
||||
ADD_SUB_ZERO_EXTEND(I,255,Add,addw,uxtb)
|
||||
ADD_SUB_ZERO_EXTEND(I,65535,Add,addw,uxth)
|
||||
@ -406,7 +445,8 @@ ADD_SUB_ZERO_EXTEND(L,65535,Sub,sub,uxth)
|
||||
ADD_SUB_ZERO_EXTEND(L,4294967295,Sub,sub,uxtw)
|
||||
dnl
|
||||
dnl ADD_SUB_ZERO_EXTEND_SHIFT(mode, size, add node, insn, ext type)
|
||||
define(`ADD_SUB_EXTENDED_SHIFT', `
|
||||
define(`ADD_SUB_EXTENDED_SHIFT', `// This pattern is automatically generated from aarch64_ad.m4
|
||||
// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
|
||||
instruct $3Ext$1_$6_shift(iReg$1NoSp dst, iReg$1`'ORL2I($1) src1, iReg$1`'ORL2I($1) src2, immIExt lshift2, immI_`'eval($7-$2) lshift1, immI_`'eval($7-$2) rshift1, rFlagsReg cr)
|
||||
%{
|
||||
match(Set dst ($3$1 src1 (LShift$1 EXTEND($1, $4, src2, lshift1, rshift1) lshift2)));
|
||||
@ -418,7 +458,8 @@ instruct $3Ext$1_$6_shift(iReg$1NoSp dst, iReg$1`'ORL2I($1) src1, iReg$1`'ORL2I(
|
||||
as_Register($src2$$reg), ext::$6, ($lshift2$$constant));
|
||||
%}
|
||||
ins_pipe(ialu_reg_reg_shift);
|
||||
%}')
|
||||
%}
|
||||
')
|
||||
dnl $1 $2 $3 $4 $5 $6 $7
|
||||
ADD_SUB_EXTENDED_SHIFT(L,8,Add,RShift,add,sxtb,64)
|
||||
ADD_SUB_EXTENDED_SHIFT(L,16,Add,RShift,add,sxth,64)
|
||||
@ -435,7 +476,8 @@ ADD_SUB_EXTENDED_SHIFT(I,8,Sub,RShift,subw,sxtb,32)
|
||||
ADD_SUB_EXTENDED_SHIFT(I,16,Sub,RShift,subw,sxth,32)
|
||||
dnl
|
||||
dnl ADD_SUB_CONV_SHIFT(mode, add node, insn, ext type)
|
||||
define(`ADD_SUB_CONV_SHIFT', `
|
||||
define(`ADD_SUB_CONV_SHIFT', `// This pattern is automatically generated from aarch64_ad.m4
|
||||
// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
|
||||
instruct $2ExtI_shift(iReg$1NoSp dst, iReg$1`'ORL2I($1) src1, iRegIorL2I src2, immIExt lshift, rFlagsReg cr)
|
||||
%{
|
||||
match(Set dst ($2$1 src1 (LShiftL (ConvI2L src2) lshift)));
|
||||
@ -447,13 +489,14 @@ instruct $2ExtI_shift(iReg$1NoSp dst, iReg$1`'ORL2I($1) src1, iRegIorL2I src2, i
|
||||
as_Register($src2$$reg), ext::$4, ($lshift$$constant));
|
||||
%}
|
||||
ins_pipe(ialu_reg_reg_shift);
|
||||
%}')
|
||||
dnl
|
||||
ADD_SUB_CONV_SHIFT(L,Add,add,sxtw);
|
||||
ADD_SUB_CONV_SHIFT(L,Sub,sub,sxtw);
|
||||
%}
|
||||
')dnl
|
||||
ADD_SUB_CONV_SHIFT(L,Add,add,sxtw)
|
||||
ADD_SUB_CONV_SHIFT(L,Sub,sub,sxtw)
|
||||
dnl
|
||||
dnl ADD_SUB_ZERO_EXTEND(mode, size, add node, insn, ext type)
|
||||
define(`ADD_SUB_ZERO_EXTEND_SHIFT', `
|
||||
define(`ADD_SUB_ZERO_EXTEND_SHIFT', `// This pattern is automatically generated from aarch64_ad.m4
|
||||
// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
|
||||
instruct $3Ext$1_$5_and_shift(iReg$1NoSp dst, iReg$1`'ORL2I($1) src1, iReg$1`'ORL2I($1) src2, imm$1_$2 mask, immIExt lshift, rFlagsReg cr)
|
||||
%{
|
||||
match(Set dst ($3$1 src1 (LShift$1 (And$1 src2 mask) lshift)));
|
||||
@ -465,8 +508,8 @@ instruct $3Ext$1_$5_and_shift(iReg$1NoSp dst, iReg$1`'ORL2I($1) src1, iReg$1`'OR
|
||||
as_Register($src2$$reg), ext::$5, ($lshift$$constant));
|
||||
%}
|
||||
ins_pipe(ialu_reg_reg_shift);
|
||||
%}')
|
||||
dnl
|
||||
%}
|
||||
')dnl
|
||||
dnl $1 $2 $3 $4 $5
|
||||
ADD_SUB_ZERO_EXTEND_SHIFT(L,255,Add,add,uxtb)
|
||||
ADD_SUB_ZERO_EXTEND_SHIFT(L,65535,Add,add,uxth)
|
||||
@ -482,4 +525,4 @@ dnl
|
||||
ADD_SUB_ZERO_EXTEND_SHIFT(I,255,Sub,subw,uxtb)
|
||||
ADD_SUB_ZERO_EXTEND_SHIFT(I,65535,Sub,subw,uxth)
|
||||
dnl
|
||||
// END This section of the file is automatically generated. Do not edit --------------
|
||||
|
||||
|
||||
@ -31,7 +31,7 @@
|
||||
#include "interpreter/interpreter.hpp"
|
||||
|
||||
#ifndef PRODUCT
|
||||
const unsigned long Assembler::asm_bp = 0x00007fffee09ac88;
|
||||
const uintptr_t Assembler::asm_bp = 0x00007fffee09ac88;
|
||||
#endif
|
||||
|
||||
#include "compiler/disassembler.hpp"
|
||||
@ -132,14 +132,14 @@ void entry(CodeBuffer *cb) {
|
||||
__ subs(r4, r1, 698u); // subs x4, x1, #698
|
||||
|
||||
// LogicalImmOp
|
||||
__ andw(r28, r19, 4294709247ul); // and w28, w19, #0xfffc0fff
|
||||
__ orrw(r27, r5, 536870910ul); // orr w27, w5, #0x1ffffffe
|
||||
__ eorw(r30, r20, 4294840319ul); // eor w30, w20, #0xfffe0fff
|
||||
__ andsw(r22, r26, 4294959615ul); // ands w22, w26, #0xffffe1ff
|
||||
__ andr(r5, r7, 4194300ul); // and x5, x7, #0x3ffffc
|
||||
__ orr(r13, r7, 18014398509481728ul); // orr x13, x7, #0x3fffffffffff00
|
||||
__ eor(r7, r9, 18442240474082197503ul); // eor x7, x9, #0xfff0000000003fff
|
||||
__ ands(r3, r0, 18374686479671656447ul); // ands x3, x0, #0xff00000000007fff
|
||||
__ andw(r28, r19, 4294709247ull); // and w28, w19, #0xfffc0fff
|
||||
__ orrw(r27, r5, 536870910ull); // orr w27, w5, #0x1ffffffe
|
||||
__ eorw(r30, r20, 4294840319ull); // eor w30, w20, #0xfffe0fff
|
||||
__ andsw(r22, r26, 4294959615ull); // ands w22, w26, #0xffffe1ff
|
||||
__ andr(r5, r7, 4194300ull); // and x5, x7, #0x3ffffc
|
||||
__ orr(r13, r7, 18014398509481728ull); // orr x13, x7, #0x3fffffffffff00
|
||||
__ eor(r7, r9, 18442240474082197503ull); // eor x7, x9, #0xfff0000000003fff
|
||||
__ ands(r3, r0, 18374686479671656447ull); // ands x3, x0, #0xff00000000007fff
|
||||
|
||||
// AbsOp
|
||||
__ b(__ pc()); // b .
|
||||
@ -1493,7 +1493,7 @@ extern "C" {
|
||||
Disassembler::decode((address)start, (address)start + len);
|
||||
}
|
||||
|
||||
JNIEXPORT void das1(unsigned long insn) {
|
||||
JNIEXPORT void das1(uintptr_t insn) {
|
||||
das(insn, 1);
|
||||
}
|
||||
}
|
||||
@ -1532,7 +1532,7 @@ void Address::lea(MacroAssembler *as, Register r) const {
|
||||
}
|
||||
}
|
||||
|
||||
void Assembler::adrp(Register reg1, const Address &dest, unsigned long &byte_offset) {
|
||||
void Assembler::adrp(Register reg1, const Address &dest, uintptr_t &byte_offset) {
|
||||
ShouldNotReachHere();
|
||||
}
|
||||
|
||||
@ -1541,7 +1541,7 @@ void Assembler::adrp(Register reg1, const Address &dest, unsigned long &byte_off
|
||||
#define starti Instruction_aarch64 do_not_use(this); set_current(&do_not_use)
|
||||
|
||||
void Assembler::adr(Register Rd, address adr) {
|
||||
long offset = adr - pc();
|
||||
intptr_t offset = adr - pc();
|
||||
int offset_lo = offset & 3;
|
||||
offset >>= 2;
|
||||
starti;
|
||||
@ -1552,7 +1552,7 @@ void Assembler::adrp(Register reg1, const Address &dest, unsigned long &byte_off
|
||||
void Assembler::_adrp(Register Rd, address adr) {
|
||||
uint64_t pc_page = (uint64_t)pc() >> 12;
|
||||
uint64_t adr_page = (uint64_t)adr >> 12;
|
||||
long offset = adr_page - pc_page;
|
||||
intptr_t offset = adr_page - pc_page;
|
||||
int offset_lo = offset & 3;
|
||||
offset >>= 2;
|
||||
starti;
|
||||
@ -1701,9 +1701,9 @@ void Assembler::add_sub_immediate(Register Rd, Register Rn, unsigned uimm, int o
|
||||
srf(Rn, 5);
|
||||
}
|
||||
|
||||
bool Assembler::operand_valid_for_add_sub_immediate(long imm) {
|
||||
bool Assembler::operand_valid_for_add_sub_immediate(int64_t imm) {
|
||||
bool shift = false;
|
||||
unsigned long uimm = uabs(imm);
|
||||
uint64_t uimm = (uint64_t)uabs(imm);
|
||||
if (uimm < (1 << 12))
|
||||
return true;
|
||||
if (uimm < (1 << 24)
|
||||
|
||||
@ -199,7 +199,7 @@ public:
|
||||
return extend(uval, msb - lsb);
|
||||
}
|
||||
|
||||
static void patch(address a, int msb, int lsb, unsigned long val) {
|
||||
static void patch(address a, int msb, int lsb, uint64_t val) {
|
||||
int nbits = msb - lsb + 1;
|
||||
guarantee(val < (1U << nbits), "Field too big for insn");
|
||||
assert_cond(msb >= lsb);
|
||||
@ -212,9 +212,9 @@ public:
|
||||
*(unsigned *)a = target;
|
||||
}
|
||||
|
||||
static void spatch(address a, int msb, int lsb, long val) {
|
||||
static void spatch(address a, int msb, int lsb, int64_t val) {
|
||||
int nbits = msb - lsb + 1;
|
||||
long chk = val >> (nbits - 1);
|
||||
int64_t chk = val >> (nbits - 1);
|
||||
guarantee (chk == -1 || chk == 0, "Field too big for insn");
|
||||
unsigned uval = val;
|
||||
unsigned mask = (1U << nbits) - 1;
|
||||
@ -245,9 +245,9 @@ public:
|
||||
f(val, bit, bit);
|
||||
}
|
||||
|
||||
void sf(long val, int msb, int lsb) {
|
||||
void sf(int64_t val, int msb, int lsb) {
|
||||
int nbits = msb - lsb + 1;
|
||||
long chk = val >> (nbits - 1);
|
||||
int64_t chk = val >> (nbits - 1);
|
||||
guarantee (chk == -1 || chk == 0, "Field too big for insn");
|
||||
unsigned uval = val;
|
||||
unsigned mask = (1U << nbits) - 1;
|
||||
@ -357,7 +357,7 @@ class Address {
|
||||
private:
|
||||
Register _base;
|
||||
Register _index;
|
||||
long _offset;
|
||||
int64_t _offset;
|
||||
enum mode _mode;
|
||||
extend _ext;
|
||||
|
||||
@ -380,9 +380,9 @@ class Address {
|
||||
: _base(r), _index(noreg), _offset(0), _mode(base_plus_offset), _target(0) { }
|
||||
Address(Register r, int o)
|
||||
: _base(r), _index(noreg), _offset(o), _mode(base_plus_offset), _target(0) { }
|
||||
Address(Register r, long o)
|
||||
Address(Register r, int64_t o)
|
||||
: _base(r), _index(noreg), _offset(o), _mode(base_plus_offset), _target(0) { }
|
||||
Address(Register r, unsigned long o)
|
||||
Address(Register r, uint64_t o)
|
||||
: _base(r), _index(noreg), _offset(o), _mode(base_plus_offset), _target(0) { }
|
||||
#ifdef ASSERT
|
||||
Address(Register r, ByteSize disp)
|
||||
@ -422,7 +422,7 @@ class Address {
|
||||
"wrong mode");
|
||||
return _base;
|
||||
}
|
||||
long offset() const {
|
||||
int64_t offset() const {
|
||||
return _offset;
|
||||
}
|
||||
Register index() const {
|
||||
@ -554,7 +554,7 @@ class Address {
|
||||
|
||||
void lea(MacroAssembler *, Register) const;
|
||||
|
||||
static bool offset_ok_for_immed(long offset, int shift) {
|
||||
static bool offset_ok_for_immed(int64_t offset, int shift) {
|
||||
unsigned mask = (1 << shift) - 1;
|
||||
if (offset < 0 || offset & mask) {
|
||||
return (uabs(offset) < (1 << (20 - 12))); // Unscaled offset
|
||||
@ -616,10 +616,10 @@ typedef enum {
|
||||
class Assembler : public AbstractAssembler {
|
||||
|
||||
#ifndef PRODUCT
|
||||
static const unsigned long asm_bp;
|
||||
static const uintptr_t asm_bp;
|
||||
|
||||
void emit_long(jint x) {
|
||||
if ((unsigned long)pc() == asm_bp)
|
||||
if ((uintptr_t)pc() == asm_bp)
|
||||
asm volatile ("nop");
|
||||
AbstractAssembler::emit_int32(x);
|
||||
}
|
||||
@ -670,7 +670,7 @@ public:
|
||||
void f(unsigned val, int msb) {
|
||||
current->f(val, msb, msb);
|
||||
}
|
||||
void sf(long val, int msb, int lsb) {
|
||||
void sf(int64_t val, int msb, int lsb) {
|
||||
current->sf(val, msb, lsb);
|
||||
}
|
||||
void rf(Register reg, int lsb) {
|
||||
@ -720,7 +720,7 @@ public:
|
||||
wrap_label(Rd, L, &Assembler::_adrp);
|
||||
}
|
||||
|
||||
void adrp(Register Rd, const Address &dest, unsigned long &offset);
|
||||
void adrp(Register Rd, const Address &dest, uint64_t &offset);
|
||||
|
||||
#undef INSN
|
||||
|
||||
@ -846,7 +846,7 @@ public:
|
||||
// architecture. In debug mode we shrink it in order to test
|
||||
// trampolines, but not so small that branches in the interpreter
|
||||
// are out of range.
|
||||
static const unsigned long branch_range = NOT_DEBUG(128 * M) DEBUG_ONLY(2 * M);
|
||||
static const uint64_t branch_range = NOT_DEBUG(128 * M) DEBUG_ONLY(2 * M);
|
||||
|
||||
static bool reachable_from_branch_at(address branch, address target) {
|
||||
return uabs(target - branch) < branch_range;
|
||||
@ -856,7 +856,7 @@ public:
|
||||
#define INSN(NAME, opcode) \
|
||||
void NAME(address dest) { \
|
||||
starti; \
|
||||
long offset = (dest - pc()) >> 2; \
|
||||
int64_t offset = (dest - pc()) >> 2; \
|
||||
DEBUG_ONLY(assert(reachable_from_branch_at(pc(), dest), "debug only")); \
|
||||
f(opcode, 31), f(0b00101, 30, 26), sf(offset, 25, 0); \
|
||||
} \
|
||||
@ -873,7 +873,7 @@ public:
|
||||
// Compare & branch (immediate)
|
||||
#define INSN(NAME, opcode) \
|
||||
void NAME(Register Rt, address dest) { \
|
||||
long offset = (dest - pc()) >> 2; \
|
||||
int64_t offset = (dest - pc()) >> 2; \
|
||||
starti; \
|
||||
f(opcode, 31, 24), sf(offset, 23, 5), rf(Rt, 0); \
|
||||
} \
|
||||
@ -891,7 +891,7 @@ public:
|
||||
// Test & branch (immediate)
|
||||
#define INSN(NAME, opcode) \
|
||||
void NAME(Register Rt, int bitpos, address dest) { \
|
||||
long offset = (dest - pc()) >> 2; \
|
||||
int64_t offset = (dest - pc()) >> 2; \
|
||||
int b5 = bitpos >> 5; \
|
||||
bitpos &= 0x1f; \
|
||||
starti; \
|
||||
@ -912,7 +912,7 @@ public:
|
||||
{EQ, NE, HS, CS=HS, LO, CC=LO, MI, PL, VS, VC, HI, LS, GE, LT, GT, LE, AL, NV};
|
||||
|
||||
void br(Condition cond, address dest) {
|
||||
long offset = (dest - pc()) >> 2;
|
||||
int64_t offset = (dest - pc()) >> 2;
|
||||
starti;
|
||||
f(0b0101010, 31, 25), f(0, 24), sf(offset, 23, 5), f(0, 4), f(cond, 3, 0);
|
||||
}
|
||||
@ -1292,7 +1292,7 @@ public:
|
||||
// Load register (literal)
|
||||
#define INSN(NAME, opc, V) \
|
||||
void NAME(Register Rt, address dest) { \
|
||||
long offset = (dest - pc()) >> 2; \
|
||||
int64_t offset = (dest - pc()) >> 2; \
|
||||
starti; \
|
||||
f(opc, 31, 30), f(0b011, 29, 27), f(V, 26), f(0b00, 25, 24), \
|
||||
sf(offset, 23, 5); \
|
||||
@ -1317,7 +1317,7 @@ public:
|
||||
|
||||
#define INSN(NAME, opc, V) \
|
||||
void NAME(FloatRegister Rt, address dest) { \
|
||||
long offset = (dest - pc()) >> 2; \
|
||||
int64_t offset = (dest - pc()) >> 2; \
|
||||
starti; \
|
||||
f(opc, 31, 30), f(0b011, 29, 27), f(V, 26), f(0b00, 25, 24), \
|
||||
sf(offset, 23, 5); \
|
||||
@ -1332,7 +1332,7 @@ public:
|
||||
|
||||
#define INSN(NAME, opc, V) \
|
||||
void NAME(address dest, prfop op = PLDL1KEEP) { \
|
||||
long offset = (dest - pc()) >> 2; \
|
||||
int64_t offset = (dest - pc()) >> 2; \
|
||||
starti; \
|
||||
f(opc, 31, 30), f(0b011, 29, 27), f(V, 26), f(0b00, 25, 24), \
|
||||
sf(offset, 23, 5); \
|
||||
@ -1408,7 +1408,7 @@ public:
|
||||
assert(size == 0b10 || size == 0b11, "bad operand size in ldr");
|
||||
assert(op == 0b01, "literal form can only be used with loads");
|
||||
f(size & 0b01, 31, 30), f(0b011, 29, 27), f(0b00, 25, 24);
|
||||
long offset = (adr.target() - pc()) >> 2;
|
||||
int64_t offset = (adr.target() - pc()) >> 2;
|
||||
sf(offset, 23, 5);
|
||||
code_section()->relocate(pc(), adr.rspec());
|
||||
return;
|
||||
@ -2683,7 +2683,7 @@ void ext(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister V
|
||||
virtual void bang_stack_with_offset(int offset);
|
||||
|
||||
static bool operand_valid_for_logical_immediate(bool is32, uint64_t imm);
|
||||
static bool operand_valid_for_add_sub_immediate(long imm);
|
||||
static bool operand_valid_for_add_sub_immediate(int64_t imm);
|
||||
static bool operand_valid_for_float_immediate(double imm);
|
||||
|
||||
void emit_data64(jlong data, relocInfo::relocType rtype, int format = 0);
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
/*
|
||||
* Copyright (c) 2000, 2020, Oracle and/or its affiliates. All rights reserved.
|
||||
* Copyright (c) 2014, Red Hat Inc. All rights reserved.
|
||||
* Copyright (c) 2014, 2020, Red Hat Inc. All rights reserved.
|
||||
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
|
||||
*
|
||||
* This code is free software; you can redistribute it and/or modify it
|
||||
@ -1352,7 +1352,7 @@ void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, L
|
||||
__ load_klass(klass_RInfo, obj);
|
||||
if (k->is_loaded()) {
|
||||
// See if we get an immediate positive hit
|
||||
__ ldr(rscratch1, Address(klass_RInfo, long(k->super_check_offset())));
|
||||
__ ldr(rscratch1, Address(klass_RInfo, int64_t(k->super_check_offset())));
|
||||
__ cmp(k_RInfo, rscratch1);
|
||||
if ((juint)in_bytes(Klass::secondary_super_cache_offset()) != k->super_check_offset()) {
|
||||
__ br(Assembler::NE, *failure_target);
|
||||
@ -2675,7 +2675,7 @@ void LIR_Assembler::emit_updatecrc32(LIR_OpUpdateCRC32* op) {
|
||||
Register res = op->result_opr()->as_register();
|
||||
|
||||
assert_different_registers(val, crc, res);
|
||||
unsigned long offset;
|
||||
uint64_t offset;
|
||||
__ adrp(res, ExternalAddress(StubRoutines::crc_table_addr()), offset);
|
||||
if (offset) __ add(res, res, offset);
|
||||
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
/*
|
||||
* Copyright (c) 1997, 2020, Oracle and/or its affiliates. All rights reserved.
|
||||
* Copyright (c) 2014, Red Hat Inc. All rights reserved.
|
||||
* Copyright (c) 2014, 2020, Red Hat Inc. All rights reserved.
|
||||
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
|
||||
*
|
||||
* This code is free software; you can redistribute it and/or modify it
|
||||
@ -653,14 +653,14 @@ intptr_t* frame::real_fp() const {
|
||||
|
||||
#define DESCRIBE_FP_OFFSET(name) \
|
||||
{ \
|
||||
unsigned long *p = (unsigned long *)fp; \
|
||||
printf("0x%016lx 0x%016lx %s\n", (unsigned long)(p + frame::name##_offset), \
|
||||
uintptr_t *p = (uintptr_t *)fp; \
|
||||
printf("0x%016lx 0x%016lx %s\n", (uintptr_t)(p + frame::name##_offset), \
|
||||
p[frame::name##_offset], #name); \
|
||||
}
|
||||
|
||||
static __thread unsigned long nextfp;
|
||||
static __thread unsigned long nextpc;
|
||||
static __thread unsigned long nextsp;
|
||||
static __thread uintptr_t nextfp;
|
||||
static __thread uintptr_t nextpc;
|
||||
static __thread uintptr_t nextsp;
|
||||
static __thread RegisterMap *reg_map;
|
||||
|
||||
static void printbc(Method *m, intptr_t bcx) {
|
||||
@ -679,7 +679,7 @@ static void printbc(Method *m, intptr_t bcx) {
|
||||
printf("%s : %s ==> %s\n", m->name_and_sig_as_C_string(), buf, name);
|
||||
}
|
||||
|
||||
void internal_pf(unsigned long sp, unsigned long fp, unsigned long pc, unsigned long bcx) {
|
||||
void internal_pf(uintptr_t sp, uintptr_t fp, uintptr_t pc, uintptr_t bcx) {
|
||||
if (! fp)
|
||||
return;
|
||||
|
||||
@ -693,7 +693,7 @@ void internal_pf(unsigned long sp, unsigned long fp, unsigned long pc, unsigned
|
||||
DESCRIBE_FP_OFFSET(interpreter_frame_locals);
|
||||
DESCRIBE_FP_OFFSET(interpreter_frame_bcp);
|
||||
DESCRIBE_FP_OFFSET(interpreter_frame_initial_sp);
|
||||
unsigned long *p = (unsigned long *)fp;
|
||||
uintptr_t *p = (uintptr_t *)fp;
|
||||
|
||||
// We want to see all frames, native and Java. For compiled and
|
||||
// interpreted frames we have special information that allows us to
|
||||
@ -703,16 +703,16 @@ void internal_pf(unsigned long sp, unsigned long fp, unsigned long pc, unsigned
|
||||
if (this_frame.is_compiled_frame() ||
|
||||
this_frame.is_interpreted_frame()) {
|
||||
frame sender = this_frame.sender(reg_map);
|
||||
nextfp = (unsigned long)sender.fp();
|
||||
nextpc = (unsigned long)sender.pc();
|
||||
nextsp = (unsigned long)sender.unextended_sp();
|
||||
nextfp = (uintptr_t)sender.fp();
|
||||
nextpc = (uintptr_t)sender.pc();
|
||||
nextsp = (uintptr_t)sender.unextended_sp();
|
||||
} else {
|
||||
nextfp = p[frame::link_offset];
|
||||
nextpc = p[frame::return_addr_offset];
|
||||
nextsp = (unsigned long)&p[frame::sender_sp_offset];
|
||||
nextsp = (uintptr_t)&p[frame::sender_sp_offset];
|
||||
}
|
||||
|
||||
if (bcx == -1ul)
|
||||
if (bcx == -1ULL)
|
||||
bcx = p[frame::interpreter_frame_bcp_offset];
|
||||
|
||||
if (Interpreter::contains((address)pc)) {
|
||||
@ -746,8 +746,8 @@ extern "C" void npf() {
|
||||
internal_pf (nextsp, nextfp, nextpc, -1);
|
||||
}
|
||||
|
||||
extern "C" void pf(unsigned long sp, unsigned long fp, unsigned long pc,
|
||||
unsigned long bcx, unsigned long thread) {
|
||||
extern "C" void pf(uintptr_t sp, uintptr_t fp, uintptr_t pc,
|
||||
uintptr_t bcx, uintptr_t thread) {
|
||||
if (!reg_map) {
|
||||
reg_map = NEW_C_HEAP_OBJ(RegisterMap, mtInternal);
|
||||
::new (reg_map) RegisterMap((JavaThread*)thread, false);
|
||||
@ -766,9 +766,9 @@ extern "C" void pf(unsigned long sp, unsigned long fp, unsigned long pc,
|
||||
// support for printing out where we are in a Java method
|
||||
// needs to be passed current fp and bcp register values
|
||||
// prints method name, bc index and bytecode name
|
||||
extern "C" void pm(unsigned long fp, unsigned long bcx) {
|
||||
extern "C" void pm(uintptr_t fp, uintptr_t bcx) {
|
||||
DESCRIBE_FP_OFFSET(interpreter_frame_method);
|
||||
unsigned long *p = (unsigned long *)fp;
|
||||
uintptr_t *p = (uintptr_t *)fp;
|
||||
Method* m = (Method*)p[frame::interpreter_frame_method_offset];
|
||||
printbc(m, bcx);
|
||||
}
|
||||
|
||||
@ -178,7 +178,7 @@ void BarrierSetAssembler::eden_allocate(MacroAssembler* masm, Register obj,
|
||||
Label retry;
|
||||
__ bind(retry);
|
||||
{
|
||||
unsigned long offset;
|
||||
uint64_t offset;
|
||||
__ adrp(rscratch1, ExternalAddress((address) Universe::heap()->end_addr()), offset);
|
||||
__ ldr(heap_end, Address(rscratch1, offset));
|
||||
}
|
||||
@ -187,7 +187,7 @@ void BarrierSetAssembler::eden_allocate(MacroAssembler* masm, Register obj,
|
||||
|
||||
// Get the current top of the heap
|
||||
{
|
||||
unsigned long offset;
|
||||
uint64_t offset;
|
||||
__ adrp(rscratch1, heap_top, offset);
|
||||
// Use add() here after ARDP, rather than lea().
|
||||
// lea() does not generate anything if its offset is zero.
|
||||
|
||||
@ -206,7 +206,7 @@ void ZBarrierSetAssembler::try_resolve_jobject_in_native(MacroAssembler* masm,
|
||||
BarrierSetAssembler::try_resolve_jobject_in_native(masm, jni_env, robj, tmp, slowpath);
|
||||
|
||||
// The Address offset is too large to direct load - -784. Our range is +127, -128.
|
||||
__ mov(tmp, (long int)(in_bytes(ZThreadLocalData::address_bad_mask_offset()) -
|
||||
__ mov(tmp, (int64_t)(in_bytes(ZThreadLocalData::address_bad_mask_offset()) -
|
||||
in_bytes(JavaThread::jni_environment_offset())));
|
||||
|
||||
// Load address bad mask
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/*
|
||||
* Copyright (c) 2014, Red Hat Inc. All rights reserved.
|
||||
* Copyright (c) 2014, 2020, Red Hat Inc. All rights reserved.
|
||||
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
|
||||
*
|
||||
* This code is free software; you can redistribute it and/or modify it
|
||||
@ -66,7 +66,7 @@ int compare_immediate_pair(const void *i1, const void *i2)
|
||||
// for i = 1, ... N result<i-1> = 1 other bits are zero
|
||||
static inline uint64_t ones(int N)
|
||||
{
|
||||
return (N == 64 ? (uint64_t)-1UL : ((1UL << N) - 1));
|
||||
return (N == 64 ? -1ULL : (1ULL << N) - 1);
|
||||
}
|
||||
|
||||
/*
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
/*
|
||||
* Copyright (c) 2003, 2020, Oracle and/or its affiliates. All rights reserved.
|
||||
* Copyright (c) 2014, Red Hat Inc. All rights reserved.
|
||||
* Copyright (c) 2014, 2020, Red Hat Inc. All rights reserved.
|
||||
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
|
||||
*
|
||||
* This code is free software; you can redistribute it and/or modify it
|
||||
@ -168,7 +168,7 @@ void InterpreterMacroAssembler::get_unsigned_2_byte_index_at_bcp(
|
||||
}
|
||||
|
||||
void InterpreterMacroAssembler::get_dispatch() {
|
||||
unsigned long offset;
|
||||
uint64_t offset;
|
||||
adrp(rdispatch, ExternalAddress((address)Interpreter::dispatch_table()), offset);
|
||||
lea(rdispatch, Address(rdispatch, offset));
|
||||
}
|
||||
@ -765,7 +765,7 @@ void InterpreterMacroAssembler::lock_object(Register lock_reg)
|
||||
// copy
|
||||
mov(rscratch1, sp);
|
||||
sub(swap_reg, swap_reg, rscratch1);
|
||||
ands(swap_reg, swap_reg, (unsigned long)(7 - os::vm_page_size()));
|
||||
ands(swap_reg, swap_reg, (uint64_t)(7 - os::vm_page_size()));
|
||||
|
||||
// Save the test result, for recursive case, the result is zero
|
||||
str(swap_reg, Address(lock_reg, mark_offset));
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
/*
|
||||
* Copyright (c) 2003, 2019, Oracle and/or its affiliates. All rights reserved.
|
||||
* Copyright (c) 2014, Red Hat Inc. All rights reserved.
|
||||
* Copyright (c) 2003, 2020, Oracle and/or its affiliates. All rights reserved.
|
||||
* Copyright (c) 2014, 2020, Red Hat Inc. All rights reserved.
|
||||
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
|
||||
*
|
||||
* This code is free software; you can redistribute it and/or modify it
|
||||
@ -346,7 +346,7 @@ class SlowSignatureHandler
|
||||
|
||||
if (_num_fp_args < Argument::n_float_register_parameters_c) {
|
||||
*_fp_args++ = from_obj;
|
||||
*_fp_identifiers |= (1 << _num_fp_args); // mark as double
|
||||
*_fp_identifiers |= (1ull << _num_fp_args); // mark as double
|
||||
_num_fp_args++;
|
||||
} else {
|
||||
*_to++ = from_obj;
|
||||
@ -382,7 +382,7 @@ JRT_ENTRY(address,
|
||||
|
||||
// handle arguments
|
||||
SlowSignatureHandler ssh(m, (address)from, to);
|
||||
ssh.iterate(UCONST64(-1));
|
||||
ssh.iterate((uint64_t)CONST64(-1));
|
||||
|
||||
// return result handler
|
||||
return Interpreter::result_handler(m->result_type());
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
/*
|
||||
* Copyright (c) 2004, 2020, Oracle and/or its affiliates. All rights reserved.
|
||||
* Copyright (c) 2014, Red Hat Inc. All rights reserved.
|
||||
* Copyright (c) 2014, 2020, Red Hat Inc. All rights reserved.
|
||||
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
|
||||
*
|
||||
* This code is free software; you can redistribute it and/or modify it
|
||||
@ -73,7 +73,7 @@ address JNI_FastGetField::generate_fast_get_int_field0(BasicType type) {
|
||||
|
||||
Label slow;
|
||||
|
||||
unsigned long offset;
|
||||
uint64_t offset;
|
||||
__ adrp(rcounter_addr,
|
||||
SafepointSynchronize::safepoint_counter_addr(), offset);
|
||||
Address safepoint_counter_addr(rcounter_addr, offset);
|
||||
@ -88,7 +88,7 @@ address JNI_FastGetField::generate_fast_get_int_field0(BasicType type) {
|
||||
|
||||
// Check to see if a field access watch has been set before we
|
||||
// take the fast path.
|
||||
unsigned long offset2;
|
||||
uint64_t offset2;
|
||||
__ adrp(result,
|
||||
ExternalAddress((address) JvmtiExport::get_field_access_count_addr()),
|
||||
offset2);
|
||||
|
||||
@ -70,8 +70,8 @@
|
||||
// Return the total length (in bytes) of the instructions.
|
||||
int MacroAssembler::pd_patch_instruction_size(address branch, address target) {
|
||||
int instructions = 1;
|
||||
assert((uint64_t)target < (1ul << 48), "48-bit overflow in address constant");
|
||||
long offset = (target - branch) >> 2;
|
||||
assert((uint64_t)target < (1ull << 48), "48-bit overflow in address constant");
|
||||
intptr_t offset = (target - branch) >> 2;
|
||||
unsigned insn = *(unsigned*)branch;
|
||||
if ((Instruction_aarch64::extract(insn, 29, 24) & 0b111011) == 0b011000) {
|
||||
// Load register (literal)
|
||||
@ -134,9 +134,9 @@ int MacroAssembler::pd_patch_instruction_size(address branch, address target) {
|
||||
Instruction_aarch64::extract(insn2, 4, 0)) {
|
||||
// movk #imm16<<32
|
||||
Instruction_aarch64::patch(branch + 4, 20, 5, (uint64_t)target >> 32);
|
||||
long dest = ((long)target & 0xffffffffL) | ((long)branch & 0xffff00000000L);
|
||||
long pc_page = (long)branch >> 12;
|
||||
long adr_page = (long)dest >> 12;
|
||||
uintptr_t dest = ((uintptr_t)target & 0xffffffffULL) | ((uintptr_t)branch & 0xffff00000000ULL);
|
||||
uintptr_t pc_page = (uintptr_t)branch >> 12;
|
||||
uintptr_t adr_page = (uintptr_t)dest >> 12;
|
||||
offset = adr_page - pc_page;
|
||||
instructions = 2;
|
||||
}
|
||||
@ -205,7 +205,7 @@ int MacroAssembler::patch_narrow_klass(address insn_addr, narrowKlass n) {
|
||||
}
|
||||
|
||||
address MacroAssembler::target_addr_for_insn(address insn_addr, unsigned insn) {
|
||||
long offset = 0;
|
||||
intptr_t offset = 0;
|
||||
if ((Instruction_aarch64::extract(insn, 29, 24) & 0b011011) == 0b00011000) {
|
||||
// Load register (literal)
|
||||
offset = Instruction_aarch64::sextract(insn, 23, 5);
|
||||
@ -389,7 +389,7 @@ void MacroAssembler::far_call(Address entry, CodeBuffer *cbuf, Register tmp) {
|
||||
assert(CodeCache::find_blob(entry.target()) != NULL,
|
||||
"destination of far call not found in code cache");
|
||||
if (far_branches()) {
|
||||
unsigned long offset;
|
||||
uintptr_t offset;
|
||||
// We can use ADRP here because we know that the total size of
|
||||
// the code cache cannot exceed 2Gb.
|
||||
adrp(tmp, entry, offset);
|
||||
@ -407,7 +407,7 @@ void MacroAssembler::far_jump(Address entry, CodeBuffer *cbuf, Register tmp) {
|
||||
assert(CodeCache::find_blob(entry.target()) != NULL,
|
||||
"destination of far call not found in code cache");
|
||||
if (far_branches()) {
|
||||
unsigned long offset;
|
||||
uintptr_t offset;
|
||||
// We can use ADRP here because we know that the total size of
|
||||
// the code cache cannot exceed 2Gb.
|
||||
adrp(tmp, entry, offset);
|
||||
@ -824,7 +824,7 @@ void MacroAssembler::c2bool(Register x) {
|
||||
address MacroAssembler::ic_call(address entry, jint method_index) {
|
||||
RelocationHolder rh = virtual_call_Relocation::spec(pc(), method_index);
|
||||
// address const_ptr = long_constant((jlong)Universe::non_oop_word());
|
||||
// unsigned long offset;
|
||||
// uintptr_t offset;
|
||||
// ldr_constant(rscratch2, const_ptr);
|
||||
movptr(rscratch2, (uintptr_t)Universe::non_oop_word());
|
||||
return trampoline_call(Address(entry, rh));
|
||||
@ -1711,7 +1711,7 @@ void MacroAssembler::mov_immediate32(Register dst, uint32_t imm32)
|
||||
// not actually be used: you must use the Address that is returned.
|
||||
// It is up to you to ensure that the shift provided matches the size
|
||||
// of your data.
|
||||
Address MacroAssembler::form_address(Register Rd, Register base, long byte_offset, int shift) {
|
||||
Address MacroAssembler::form_address(Register Rd, Register base, int64_t byte_offset, int shift) {
|
||||
if (Address::offset_ok_for_immed(byte_offset, shift))
|
||||
// It fits; no need for any heroics
|
||||
return Address(base, byte_offset);
|
||||
@ -1726,8 +1726,8 @@ Address MacroAssembler::form_address(Register Rd, Register base, long byte_offse
|
||||
|
||||
// See if we can do this with two 12-bit offsets
|
||||
{
|
||||
unsigned long word_offset = byte_offset >> shift;
|
||||
unsigned long masked_offset = word_offset & 0xfff000;
|
||||
uint64_t word_offset = byte_offset >> shift;
|
||||
uint64_t masked_offset = word_offset & 0xfff000;
|
||||
if (Address::offset_ok_for_immed(word_offset - masked_offset, 0)
|
||||
&& Assembler::operand_valid_for_add_sub_immediate(masked_offset << shift)) {
|
||||
add(Rd, base, masked_offset << shift);
|
||||
@ -1968,7 +1968,7 @@ void MacroAssembler::decrement(Register reg, int value)
|
||||
if (value < (1 << 12)) { sub(reg, reg, value); return; }
|
||||
/* else */ {
|
||||
assert(reg != rscratch2, "invalid dst for register decrement");
|
||||
mov(rscratch2, (unsigned long)value);
|
||||
mov(rscratch2, (uint64_t)value);
|
||||
sub(reg, reg, rscratch2);
|
||||
}
|
||||
}
|
||||
@ -2720,19 +2720,19 @@ Address MacroAssembler::spill_address(int size, int offset, Register tmp)
|
||||
// Returns true if it is, else false.
|
||||
bool MacroAssembler::merge_alignment_check(Register base,
|
||||
size_t size,
|
||||
long cur_offset,
|
||||
long prev_offset) const {
|
||||
int64_t cur_offset,
|
||||
int64_t prev_offset) const {
|
||||
if (AvoidUnalignedAccesses) {
|
||||
if (base == sp) {
|
||||
// Checks whether low offset if aligned to pair of registers.
|
||||
long pair_mask = size * 2 - 1;
|
||||
long offset = prev_offset > cur_offset ? cur_offset : prev_offset;
|
||||
int64_t pair_mask = size * 2 - 1;
|
||||
int64_t offset = prev_offset > cur_offset ? cur_offset : prev_offset;
|
||||
return (offset & pair_mask) == 0;
|
||||
} else { // If base is not sp, we can't guarantee the access is aligned.
|
||||
return false;
|
||||
}
|
||||
} else {
|
||||
long mask = size - 1;
|
||||
int64_t mask = size - 1;
|
||||
// Load/store pair instruction only supports element size aligned offset.
|
||||
return (cur_offset & mask) == 0 && (prev_offset & mask) == 0;
|
||||
}
|
||||
@ -2765,8 +2765,8 @@ bool MacroAssembler::ldst_can_merge(Register rt,
|
||||
return false;
|
||||
}
|
||||
|
||||
long max_offset = 63 * prev_size_in_bytes;
|
||||
long min_offset = -64 * prev_size_in_bytes;
|
||||
int64_t max_offset = 63 * prev_size_in_bytes;
|
||||
int64_t min_offset = -64 * prev_size_in_bytes;
|
||||
|
||||
assert(prev_ldst->is_not_pre_post_index(), "pre-index or post-index is not supported to be merged.");
|
||||
|
||||
@ -2775,8 +2775,8 @@ bool MacroAssembler::ldst_can_merge(Register rt,
|
||||
return false;
|
||||
}
|
||||
|
||||
long cur_offset = adr.offset();
|
||||
long prev_offset = prev_ldst->offset();
|
||||
int64_t cur_offset = adr.offset();
|
||||
int64_t prev_offset = prev_ldst->offset();
|
||||
size_t diff = abs(cur_offset - prev_offset);
|
||||
if (diff != prev_size_in_bytes) {
|
||||
return false;
|
||||
@ -2793,7 +2793,7 @@ bool MacroAssembler::ldst_can_merge(Register rt,
|
||||
return false;
|
||||
}
|
||||
|
||||
long low_offset = prev_offset > cur_offset ? cur_offset : prev_offset;
|
||||
int64_t low_offset = prev_offset > cur_offset ? cur_offset : prev_offset;
|
||||
// Offset range must be in ldp/stp instruction's range.
|
||||
if (low_offset > max_offset || low_offset < min_offset) {
|
||||
return false;
|
||||
@ -2818,7 +2818,7 @@ void MacroAssembler::merge_ldst(Register rt,
|
||||
address prev = pc() - NativeInstruction::instruction_size;
|
||||
NativeLdSt* prev_ldst = NativeLdSt_at(prev);
|
||||
|
||||
long offset;
|
||||
int64_t offset;
|
||||
|
||||
if (adr.offset() < prev_ldst->offset()) {
|
||||
offset = adr.offset();
|
||||
@ -3364,7 +3364,7 @@ void MacroAssembler::kernel_crc32(Register crc, Register buf, Register len,
|
||||
Register table0, Register table1, Register table2, Register table3,
|
||||
Register tmp, Register tmp2, Register tmp3) {
|
||||
Label L_by16, L_by16_loop, L_by4, L_by4_loop, L_by1, L_by1_loop, L_exit;
|
||||
unsigned long offset;
|
||||
uint64_t offset;
|
||||
|
||||
if (UseCRC32) {
|
||||
kernel_crc32_using_crc32(crc, buf, len, table0, table1, table2, table3);
|
||||
@ -3666,7 +3666,7 @@ void MacroAssembler::kernel_crc32c(Register crc, Register buf, Register len,
|
||||
SkipIfEqual::SkipIfEqual(
|
||||
MacroAssembler* masm, const bool* flag_addr, bool value) {
|
||||
_masm = masm;
|
||||
unsigned long offset;
|
||||
uint64_t offset;
|
||||
_masm->adrp(rscratch1, ExternalAddress((address)flag_addr), offset);
|
||||
_masm->ldrb(rscratch1, Address(rscratch1, offset));
|
||||
_masm->cbzw(rscratch1, _label);
|
||||
@ -3695,7 +3695,7 @@ void MacroAssembler::addptr(const Address &dst, int32_t src) {
|
||||
}
|
||||
|
||||
void MacroAssembler::cmpptr(Register src1, Address src2) {
|
||||
unsigned long offset;
|
||||
uint64_t offset;
|
||||
adrp(rscratch1, src2, offset);
|
||||
ldr(rscratch1, Address(rscratch1, offset));
|
||||
cmp(src1, rscratch1);
|
||||
@ -3951,7 +3951,7 @@ MacroAssembler::KlassDecodeMode MacroAssembler::klass_decode_mode() {
|
||||
if (operand_valid_for_logical_immediate(
|
||||
/*is32*/false, (uint64_t)CompressedKlassPointers::base())) {
|
||||
const uint64_t range_mask =
|
||||
(1UL << log2_intptr(CompressedKlassPointers::range())) - 1;
|
||||
(1ULL << log2_intptr(CompressedKlassPointers::range())) - 1;
|
||||
if (((uint64_t)CompressedKlassPointers::base() & range_mask) == 0) {
|
||||
return (_klass_decode_mode = KlassDecodeXor);
|
||||
}
|
||||
@ -4357,13 +4357,13 @@ address MacroAssembler::read_polling_page(Register r, relocInfo::relocType rtype
|
||||
return inst_mark();
|
||||
}
|
||||
|
||||
void MacroAssembler::adrp(Register reg1, const Address &dest, unsigned long &byte_offset) {
|
||||
void MacroAssembler::adrp(Register reg1, const Address &dest, uint64_t &byte_offset) {
|
||||
relocInfo::relocType rtype = dest.rspec().reloc()->type();
|
||||
unsigned long low_page = (unsigned long)CodeCache::low_bound() >> 12;
|
||||
unsigned long high_page = (unsigned long)(CodeCache::high_bound()-1) >> 12;
|
||||
unsigned long dest_page = (unsigned long)dest.target() >> 12;
|
||||
long offset_low = dest_page - low_page;
|
||||
long offset_high = dest_page - high_page;
|
||||
uint64_t low_page = (uint64_t)CodeCache::low_bound() >> 12;
|
||||
uint64_t high_page = (uint64_t)(CodeCache::high_bound()-1) >> 12;
|
||||
uint64_t dest_page = (uint64_t)dest.target() >> 12;
|
||||
int64_t offset_low = dest_page - low_page;
|
||||
int64_t offset_high = dest_page - high_page;
|
||||
|
||||
assert(is_valid_AArch64_address(dest.target()), "bad address");
|
||||
assert(dest.getMode() == Address::literal, "ADRP must be applied to a literal address");
|
||||
@ -4375,14 +4375,14 @@ void MacroAssembler::adrp(Register reg1, const Address &dest, unsigned long &byt
|
||||
if (offset_high >= -(1<<20) && offset_low < (1<<20)) {
|
||||
_adrp(reg1, dest.target());
|
||||
} else {
|
||||
unsigned long target = (unsigned long)dest.target();
|
||||
unsigned long adrp_target
|
||||
= (target & 0xffffffffUL) | ((unsigned long)pc() & 0xffff00000000UL);
|
||||
uint64_t target = (uint64_t)dest.target();
|
||||
uint64_t adrp_target
|
||||
= (target & 0xffffffffULL) | ((uint64_t)pc() & 0xffff00000000ULL);
|
||||
|
||||
_adrp(reg1, (address)adrp_target);
|
||||
movk(reg1, target >> 32, 32);
|
||||
}
|
||||
byte_offset = (unsigned long)dest.target() & 0xfff;
|
||||
byte_offset = (uint64_t)dest.target() & 0xfff;
|
||||
}
|
||||
|
||||
void MacroAssembler::load_byte_map_base(Register reg) {
|
||||
@ -4392,7 +4392,7 @@ void MacroAssembler::load_byte_map_base(Register reg) {
|
||||
if (is_valid_AArch64_address((address)byte_map_base)) {
|
||||
// Strictly speaking the byte_map_base isn't an address at all,
|
||||
// and it might even be negative.
|
||||
unsigned long offset;
|
||||
uint64_t offset;
|
||||
adrp(reg, ExternalAddress((address)byte_map_base), offset);
|
||||
// We expect offset to be zero with most collectors.
|
||||
if (offset != 0) {
|
||||
|
||||
@ -499,14 +499,14 @@ public:
|
||||
mov_immediate32(dst, imm32);
|
||||
}
|
||||
|
||||
inline void mov(Register dst, long l)
|
||||
inline void mov(Register dst, int64_t l)
|
||||
{
|
||||
mov(dst, (uint64_t)l);
|
||||
}
|
||||
|
||||
inline void mov(Register dst, int i)
|
||||
{
|
||||
mov(dst, (long)i);
|
||||
mov(dst, (int64_t)i);
|
||||
}
|
||||
|
||||
void mov(Register dst, RegisterOrConstant src) {
|
||||
@ -1170,7 +1170,7 @@ public:
|
||||
void sub(Register Rd, Register Rn, RegisterOrConstant decrement);
|
||||
void subw(Register Rd, Register Rn, RegisterOrConstant decrement);
|
||||
|
||||
void adrp(Register reg1, const Address &dest, unsigned long &byte_offset);
|
||||
void adrp(Register reg1, const Address &dest, uint64_t &byte_offset);
|
||||
|
||||
void tableswitch(Register index, jint lowbound, jint highbound,
|
||||
Label &jumptable, Label &jumptable_end, int stride = 1) {
|
||||
@ -1187,7 +1187,7 @@ public:
|
||||
// actually be used: you must use the Address that is returned. It
|
||||
// is up to you to ensure that the shift provided matches the size
|
||||
// of your data.
|
||||
Address form_address(Register Rd, Register base, long byte_offset, int shift);
|
||||
Address form_address(Register Rd, Register base, int64_t byte_offset, int shift);
|
||||
|
||||
// Return true iff an address is within the 48-bit AArch64 address
|
||||
// space.
|
||||
@ -1212,7 +1212,7 @@ public:
|
||||
if (NearCpool) {
|
||||
ldr(dest, const_addr);
|
||||
} else {
|
||||
unsigned long offset;
|
||||
uint64_t offset;
|
||||
adrp(dest, InternalAddress(const_addr.target()), offset);
|
||||
ldr(dest, Address(dest, offset));
|
||||
}
|
||||
@ -1310,7 +1310,7 @@ private:
|
||||
// Uses rscratch2 if the address is not directly reachable
|
||||
Address spill_address(int size, int offset, Register tmp=rscratch2);
|
||||
|
||||
bool merge_alignment_check(Register base, size_t size, long cur_offset, long prev_offset) const;
|
||||
bool merge_alignment_check(Register base, size_t size, int64_t cur_offset, int64_t prev_offset) const;
|
||||
|
||||
// Check whether two loads/stores can be merged into ldp/stp.
|
||||
bool ldst_can_merge(Register rx, const Address &adr, size_t cur_size_in_bytes, bool is_store) const;
|
||||
|
||||
@ -260,9 +260,9 @@ void MacroAssembler::fast_log(FloatRegister vtmp0, FloatRegister vtmp1,
|
||||
Register tmp4, Register tmp5) {
|
||||
Label DONE, CHECK_CORNER_CASES, SMALL_VALUE, MAIN,
|
||||
CHECKED_CORNER_CASES, RETURN_MINF_OR_NAN;
|
||||
const long INF_OR_NAN_PREFIX = 0x7FF0;
|
||||
const long MINF_OR_MNAN_PREFIX = 0xFFF0;
|
||||
const long ONE_PREFIX = 0x3FF0;
|
||||
const int64_t INF_OR_NAN_PREFIX = 0x7FF0;
|
||||
const int64_t MINF_OR_MNAN_PREFIX = 0xFFF0;
|
||||
const int64_t ONE_PREFIX = 0x3FF0;
|
||||
movz(tmp2, ONE_PREFIX, 48);
|
||||
movz(tmp4, 0x0010, 48);
|
||||
fmovd(rscratch1, v0); // rscratch1 = AS_LONG_BITS(X)
|
||||
|
||||
@ -201,9 +201,9 @@
|
||||
// NOTE: fpu registers are actively reused. See comments in code about their usage
|
||||
void MacroAssembler::generate__ieee754_rem_pio2(address npio2_hw,
|
||||
address two_over_pi, address pio2) {
|
||||
const long PIO2_1t = 0x3DD0B4611A626331UL;
|
||||
const long PIO2_2 = 0x3DD0B4611A600000UL;
|
||||
const long PIO2_2t = 0x3BA3198A2E037073UL;
|
||||
const int64_t PIO2_1t = 0x3DD0B4611A626331ULL;
|
||||
const int64_t PIO2_2 = 0x3DD0B4611A600000ULL;
|
||||
const int64_t PIO2_2t = 0x3BA3198A2E037073ULL;
|
||||
Label X_IS_NEGATIVE, X_IS_MEDIUM_OR_LARGE, X_IS_POSITIVE_LONG_PI, LARGE_ELSE,
|
||||
REDUCTION_DONE, X_IS_MEDIUM_BRANCH_DONE, X_IS_LARGE, NX_SET,
|
||||
X_IS_NEGATIVE_LONG_PI;
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
/*
|
||||
* Copyright (c) 1997, 2020, Oracle and/or its affiliates. All rights reserved.
|
||||
* Copyright (c) 2014, 2018, Red Hat Inc. All rights reserved.
|
||||
* Copyright (c) 2014, 2020, Red Hat Inc. All rights reserved.
|
||||
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
|
||||
*
|
||||
* This code is free software; you can redistribute it and/or modify it
|
||||
@ -305,7 +305,7 @@ void NativeMovRegMem::set_offset(int x) {
|
||||
unsigned insn = *(unsigned*)pc;
|
||||
if (maybe_cpool_ref(pc)) {
|
||||
address addr = MacroAssembler::target_addr_for_insn(pc);
|
||||
*(long*)addr = x;
|
||||
*(int64_t*)addr = x;
|
||||
} else {
|
||||
MacroAssembler::pd_patch_instruction(pc, (address)intptr_t(x));
|
||||
ICache::invalidate_range(instruction_address(), instruction_size);
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
/*
|
||||
* Copyright (c) 2000, 2019, Oracle and/or its affiliates. All rights reserved.
|
||||
* Copyright (c) 2014, Red Hat Inc. All rights reserved.
|
||||
* Copyright (c) 2014, 2020, Red Hat Inc. All rights reserved.
|
||||
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
|
||||
*
|
||||
* This code is free software; you can redistribute it and/or modify it
|
||||
@ -65,7 +65,7 @@ class RegisterImpl: public AbstractRegisterImpl {
|
||||
|
||||
// Return the bit which represents this register. This is intended
|
||||
// to be ORed into a bitmask: for usage see class RegSet below.
|
||||
unsigned long bit(bool should_set = true) const { return should_set ? 1 << encoding() : 0; }
|
||||
uint64_t bit(bool should_set = true) const { return should_set ? 1 << encoding() : 0; }
|
||||
};
|
||||
|
||||
// The integer registers of the aarch64 architecture
|
||||
|
||||
@ -403,7 +403,7 @@ static void gen_c2i_adapter(MacroAssembler *masm,
|
||||
// 3 8 T_BOOL
|
||||
// - 0 return address
|
||||
//
|
||||
// However to make thing extra confusing. Because we can fit a long/double in
|
||||
// However to make thing extra confusing. Because we can fit a Java long/double in
|
||||
// a single slot on a 64 bt vm and it would be silly to break them up, the interpreter
|
||||
// leaves one slot empty and only stores to a single slot. In this case the
|
||||
// slot that is occupied is the T_VOID slot. See I said it was confusing.
|
||||
@ -436,7 +436,7 @@ static void gen_c2i_adapter(MacroAssembler *masm,
|
||||
__ str(rscratch1, Address(sp, next_off));
|
||||
#ifdef ASSERT
|
||||
// Overwrite the unused slot with known junk
|
||||
__ mov(rscratch1, 0xdeadffffdeadaaaaul);
|
||||
__ mov(rscratch1, (uint64_t)0xdeadffffdeadaaaaull);
|
||||
__ str(rscratch1, Address(sp, st_off));
|
||||
#endif /* ASSERT */
|
||||
} else {
|
||||
@ -453,10 +453,10 @@ static void gen_c2i_adapter(MacroAssembler *masm,
|
||||
// Two VMREgs|OptoRegs can be T_OBJECT, T_ADDRESS, T_DOUBLE, T_LONG
|
||||
// T_DOUBLE and T_LONG use two slots in the interpreter
|
||||
if ( sig_bt[i] == T_LONG || sig_bt[i] == T_DOUBLE) {
|
||||
// long/double in gpr
|
||||
// jlong/double in gpr
|
||||
#ifdef ASSERT
|
||||
// Overwrite the unused slot with known junk
|
||||
__ mov(rscratch1, 0xdeadffffdeadaaabul);
|
||||
__ mov(rscratch1, (uint64_t)0xdeadffffdeadaaabull);
|
||||
__ str(rscratch1, Address(sp, st_off));
|
||||
#endif /* ASSERT */
|
||||
__ str(r, Address(sp, next_off));
|
||||
@ -472,7 +472,7 @@ static void gen_c2i_adapter(MacroAssembler *masm,
|
||||
} else {
|
||||
#ifdef ASSERT
|
||||
// Overwrite the unused slot with known junk
|
||||
__ mov(rscratch1, 0xdeadffffdeadaaacul);
|
||||
__ mov(rscratch1, (uint64_t)0xdeadffffdeadaaacull);
|
||||
__ str(rscratch1, Address(sp, st_off));
|
||||
#endif /* ASSERT */
|
||||
__ strd(r_1->as_FloatRegister(), Address(sp, next_off));
|
||||
@ -1701,7 +1701,7 @@ nmethod* SharedRuntime::generate_native_wrapper(MacroAssembler* masm,
|
||||
|
||||
Label dtrace_method_entry, dtrace_method_entry_done;
|
||||
{
|
||||
unsigned long offset;
|
||||
uint64_t offset;
|
||||
__ adrp(rscratch1, ExternalAddress((address)&DTraceMethodProbes), offset);
|
||||
__ ldrb(rscratch1, Address(rscratch1, offset));
|
||||
__ cbnzw(rscratch1, dtrace_method_entry);
|
||||
@ -1915,7 +1915,7 @@ nmethod* SharedRuntime::generate_native_wrapper(MacroAssembler* masm,
|
||||
|
||||
Label dtrace_method_exit, dtrace_method_exit_done;
|
||||
{
|
||||
unsigned long offset;
|
||||
uint64_t offset;
|
||||
__ adrp(rscratch1, ExternalAddress((address)&DTraceMethodProbes), offset);
|
||||
__ ldrb(rscratch1, Address(rscratch1, offset));
|
||||
__ cbnzw(rscratch1, dtrace_method_exit);
|
||||
|
||||
@ -3283,8 +3283,8 @@ class StubGenerator: public StubCodeGenerator {
|
||||
|
||||
// Max number of bytes we can process before having to take the mod
|
||||
// 0x15B0 is 5552 in decimal, the largest n such that 255n(n+1)/2 + (n+1)(BASE-1) <= 2^32-1
|
||||
unsigned long BASE = 0xfff1;
|
||||
unsigned long NMAX = 0x15B0;
|
||||
uint64_t BASE = 0xfff1;
|
||||
uint64_t NMAX = 0x15B0;
|
||||
|
||||
__ mov(base, BASE);
|
||||
__ mov(nmax, NMAX);
|
||||
@ -5381,12 +5381,12 @@ class StubGenerator: public StubCodeGenerator {
|
||||
// In C, approximately:
|
||||
|
||||
// void
|
||||
// montgomery_multiply(unsigned long Pa_base[], unsigned long Pb_base[],
|
||||
// unsigned long Pn_base[], unsigned long Pm_base[],
|
||||
// unsigned long inv, int len) {
|
||||
// unsigned long t0 = 0, t1 = 0, t2 = 0; // Triple-precision accumulator
|
||||
// unsigned long *Pa, *Pb, *Pn, *Pm;
|
||||
// unsigned long Ra, Rb, Rn, Rm;
|
||||
// montgomery_multiply(julong Pa_base[], julong Pb_base[],
|
||||
// julong Pn_base[], julong Pm_base[],
|
||||
// julong inv, int len) {
|
||||
// julong t0 = 0, t1 = 0, t2 = 0; // Triple-precision accumulator
|
||||
// julong *Pa, *Pb, *Pn, *Pm;
|
||||
// julong Ra, Rb, Rn, Rm;
|
||||
|
||||
// int i;
|
||||
|
||||
@ -5594,11 +5594,11 @@ class StubGenerator: public StubCodeGenerator {
|
||||
// In C, approximately:
|
||||
|
||||
// void
|
||||
// montgomery_square(unsigned long Pa_base[], unsigned long Pn_base[],
|
||||
// unsigned long Pm_base[], unsigned long inv, int len) {
|
||||
// unsigned long t0 = 0, t1 = 0, t2 = 0; // Triple-precision accumulator
|
||||
// unsigned long *Pa, *Pb, *Pn, *Pm;
|
||||
// unsigned long Ra, Rb, Rn, Rm;
|
||||
// montgomery_square(julong Pa_base[], julong Pn_base[],
|
||||
// julong Pm_base[], julong inv, int len) {
|
||||
// julong t0 = 0, t1 = 0, t2 = 0; // Triple-precision accumulator
|
||||
// julong *Pa, *Pb, *Pn, *Pm;
|
||||
// julong Ra, Rb, Rn, Rm;
|
||||
|
||||
// int i;
|
||||
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
/*
|
||||
* Copyright (c) 2003, 2020, Oracle and/or its affiliates. All rights reserved.
|
||||
* Copyright (c) 2014, 2019, Red Hat Inc. All rights reserved.
|
||||
* Copyright (c) 2014, 2020, Red Hat Inc. All rights reserved.
|
||||
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
|
||||
*
|
||||
* This code is free software; you can redistribute it and/or modify it
|
||||
@ -994,7 +994,7 @@ address TemplateInterpreterGenerator::generate_CRC32_update_entry() {
|
||||
__ ldrw(val, Address(esp, 0)); // byte value
|
||||
__ ldrw(crc, Address(esp, wordSize)); // Initial CRC
|
||||
|
||||
unsigned long offset;
|
||||
uint64_t offset;
|
||||
__ adrp(tbl, ExternalAddress(StubRoutines::crc_table_addr()), offset);
|
||||
__ add(tbl, tbl, offset);
|
||||
|
||||
|
||||
@ -161,7 +161,7 @@ void VM_Version::get_processor_features() {
|
||||
SoftwarePrefetchHintDistance &= ~7;
|
||||
}
|
||||
|
||||
unsigned long auxv = getauxval(AT_HWCAP);
|
||||
uint64_t auxv = getauxval(AT_HWCAP);
|
||||
|
||||
char buf[512];
|
||||
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user