diff --git a/src/hotspot/cpu/x86/assembler_x86.cpp b/src/hotspot/cpu/x86/assembler_x86.cpp index 085ae4a6ddd..f90dfb2aa5b 100644 --- a/src/hotspot/cpu/x86/assembler_x86.cpp +++ b/src/hotspot/cpu/x86/assembler_x86.cpp @@ -332,6 +332,21 @@ void Assembler::emit_arith(int op1, int op2, Register dst, int32_t imm32) { } } +void Assembler::emit_arith_ndd(int op1, int op2, Register dst, int32_t imm32) { + assert(isByte(op1) && isByte(op2), "wrong opcode"); + assert(op1 == 0x81, "Unexpected opcode"); + // This code cache friendly optimization saves 3 bytes per encoding, which offsets the EVEX encoding penalty. + if (is8bit(imm32)) { + emit_int24(op1 | 0x02, // set sign bit + op2 | encode(dst), + imm32 & 0xFF); + } + else { + emit_int16(op1, (op2 | encode(dst))); + emit_int32(imm32); + } +} + // Force generation of a 4 byte immediate value even if it fits into 8bit void Assembler::emit_arith_imm32(int op1, int op2, Register dst, int32_t imm32) { assert(isByte(op1) && isByte(op2), "wrong opcode"); @@ -1461,7 +1476,7 @@ void Assembler::addl(Register dst, int32_t imm32) { void Assembler::eaddl(Register dst, Register src, int32_t imm32, bool no_flags) { InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); (void) evex_prefix_and_encode_ndd(0, dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags); - emit_arith(0x81, 0xC0, src, imm32); + emit_arith_ndd(0x81, 0xC0, src, imm32); } void Assembler::addl(Register dst, Address src) { @@ -1695,7 +1710,7 @@ void Assembler::andl(Register dst, int32_t imm32) { void Assembler::eandl(Register dst, Register src, int32_t imm32, bool no_flags) { InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); (void) evex_prefix_and_encode_ndd(0, dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags); - emit_arith(0x81, 0xE0, src, imm32); + emit_arith_ndd(0x81, 0xE0, src, imm32); } void Assembler::andl(Address dst, Register src) { @@ -4532,7 +4547,7 @@ void Assembler::orl(Register dst, int32_t imm32) { void Assembler::eorl(Register dst, Register src, int32_t imm32, bool no_flags) { InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); evex_prefix_and_encode_ndd(0, dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags); - emit_arith(0x81, 0xC8, src, imm32); + emit_arith_ndd(0x81, 0xC8, src, imm32); } void Assembler::orl(Register dst, Address src) { @@ -7171,7 +7186,7 @@ void Assembler::subl(Register dst, int32_t imm32) { void Assembler::esubl(Register dst, Register src, int32_t imm32, bool no_flags) { InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); (void) evex_prefix_and_encode_ndd(0, dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags); - emit_arith(0x81, 0xE8, src, imm32); + emit_arith_ndd(0x81, 0xE8, src, imm32); } // Force generation of a 4 byte immediate value even if it fits into 8bit @@ -7512,7 +7527,7 @@ void Assembler::xorl(Register dst, int32_t imm32) { void Assembler::exorl(Register dst, Register src, int32_t imm32, bool no_flags) { InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); evex_prefix_and_encode_ndd(0, dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags); - emit_arith(0x81, 0xF0, src, imm32); + emit_arith_ndd(0x81, 0xF0, src, imm32); } void Assembler::xorl(Register dst, Address src) { @@ -15158,7 +15173,7 @@ void Assembler::addq(Register dst, int32_t imm32) { void Assembler::eaddq(Register dst, Register src, int32_t imm32, bool no_flags) { InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); (void) evex_prefix_and_encode_ndd(0, dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags); - emit_arith(0x81, 0xC0, src, imm32); + emit_arith_ndd(0x81, 0xC0, src, imm32); } void Assembler::addq(Register dst, Address src) { @@ -15255,7 +15270,7 @@ void Assembler::andq(Register dst, int32_t imm32) { void Assembler::eandq(Register dst, Register src, int32_t imm32, bool no_flags) { InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); evex_prefix_and_encode_ndd(0, dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags); - emit_arith(0x81, 0xE0, src, imm32); + emit_arith_ndd(0x81, 0xE0, src, imm32); } void Assembler::andq(Register dst, Address src) { @@ -16142,7 +16157,7 @@ void Assembler::orq(Register dst, int32_t imm32) { void Assembler::eorq(Register dst, Register src, int32_t imm32, bool no_flags) { InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); evex_prefix_and_encode_ndd(0, dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags); - emit_arith(0x81, 0xC8, src, imm32); + emit_arith_ndd(0x81, 0xC8, src, imm32); } void Assembler::orq_imm32(Register dst, int32_t imm32) { @@ -16830,7 +16845,7 @@ void Assembler::subq(Register dst, int32_t imm32) { void Assembler::esubq(Register dst, Register src, int32_t imm32, bool no_flags) { InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); (void) evex_prefix_and_encode_ndd(0, dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags); - emit_arith(0x81, 0xE8, src, imm32); + emit_arith_ndd(0x81, 0xE8, src, imm32); } // Force generation of a 4 byte immediate value even if it fits into 8bit @@ -16961,7 +16976,7 @@ void Assembler::xorq(Register dst, int32_t imm32) { void Assembler::exorq(Register dst, Register src, int32_t imm32, bool no_flags) { InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); evex_prefix_and_encode_ndd(0, dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags); - emit_arith(0x81, 0xF0, src, imm32); + emit_arith_ndd(0x81, 0xF0, src, imm32); } void Assembler::xorq(Address dst, int32_t imm32) { diff --git a/src/hotspot/cpu/x86/assembler_x86.hpp b/src/hotspot/cpu/x86/assembler_x86.hpp index 1eb12fb93f0..4992661dce2 100644 --- a/src/hotspot/cpu/x86/assembler_x86.hpp +++ b/src/hotspot/cpu/x86/assembler_x86.hpp @@ -823,6 +823,7 @@ private: void emit_arith_b(int op1, int op2, Register dst, int imm8); void emit_arith(int op1, int op2, Register dst, int32_t imm32); + void emit_arith_ndd(int op1, int op2, Register dst, int32_t imm32); // Force generation of a 4 byte immediate value even if it fits into 8bit void emit_arith_imm32(int op1, int op2, Register dst, int32_t imm32); void emit_arith(int op1, int op2, Register dst, Register src); diff --git a/src/hotspot/cpu/x86/x86_64.ad b/src/hotspot/cpu/x86/x86_64.ad index 10ea0c343a4..b94ff7dbd9e 100644 --- a/src/hotspot/cpu/x86/x86_64.ad +++ b/src/hotspot/cpu/x86/x86_64.ad @@ -4381,16 +4381,21 @@ instruct loadNKlassCompactHeaders(rRegN dst, memory mem, rFlagsReg cr) predicate(UseCompactObjectHeaders); match(Set dst (LoadNKlass mem)); effect(KILL cr); - ins_cost(125); // XXX + ins_cost(125); format %{ "movl $dst, $mem\t# compressed klass ptr, shifted\n\t" "shrl $dst, markWord::klass_shift_at_offset" %} ins_encode %{ - __ movl($dst$$Register, $mem$$Address); - __ shrl($dst$$Register, markWord::klass_shift_at_offset); + if (UseAPX) { + __ eshrl($dst$$Register, $mem$$Address, markWord::klass_shift_at_offset, false); + } + else { + __ movl($dst$$Register, $mem$$Address); + __ shrl($dst$$Register, markWord::klass_shift_at_offset); + } %} - ins_pipe(ialu_reg_mem); // XXX + ins_pipe(ialu_reg_mem); %} // Load Float @@ -6140,6 +6145,7 @@ instruct cmovI_imm_01(rRegI dst, immI_1 src, rFlagsReg cr, cmpOp cop) instruct cmovI_reg(rRegI dst, rRegI src, rFlagsReg cr, cmpOp cop) %{ + predicate(!UseAPX); match(Set dst (CMoveI (Binary cop cr) (Binary dst src))); ins_cost(200); // XXX @@ -6150,6 +6156,19 @@ instruct cmovI_reg(rRegI dst, rRegI src, rFlagsReg cr, cmpOp cop) ins_pipe(pipe_cmov_reg); %} +instruct cmovI_reg_ndd(rRegI dst, rRegI src1, rRegI src2, rFlagsReg cr, cmpOp cop) +%{ + predicate(UseAPX); + match(Set dst (CMoveI (Binary cop cr) (Binary src1 src2))); + + ins_cost(200); + format %{ "ecmovl$cop $dst, $src1, $src2\t# signed, int ndd" %} + ins_encode %{ + __ ecmovl((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src1$$Register, $src2$$Register); + %} + ins_pipe(pipe_cmov_reg); +%} + instruct cmovI_imm_01U(rRegI dst, immI_1 src, rFlagsRegU cr, cmpOpU cop) %{ predicate(n->in(2)->in(2)->is_Con() && n->in(2)->in(2)->get_int() == 0); @@ -6165,6 +6184,7 @@ instruct cmovI_imm_01U(rRegI dst, immI_1 src, rFlagsRegU cr, cmpOpU cop) %} instruct cmovI_regU(cmpOpU cop, rFlagsRegU cr, rRegI dst, rRegI src) %{ + predicate(!UseAPX); match(Set dst (CMoveI (Binary cop cr) (Binary dst src))); ins_cost(200); // XXX @@ -6175,6 +6195,18 @@ instruct cmovI_regU(cmpOpU cop, rFlagsRegU cr, rRegI dst, rRegI src) %{ ins_pipe(pipe_cmov_reg); %} +instruct cmovI_regU_ndd(rRegI dst, cmpOpU cop, rFlagsRegU cr, rRegI src1, rRegI src2) %{ + predicate(UseAPX); + match(Set dst (CMoveI (Binary cop cr) (Binary src1 src2))); + + ins_cost(200); + format %{ "ecmovl$cop $dst, $src1, $src2\t# unsigned, int ndd" %} + ins_encode %{ + __ ecmovl((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src1$$Register, $src2$$Register); + %} + ins_pipe(pipe_cmov_reg); +%} + instruct cmovI_imm_01UCF(rRegI dst, immI_1 src, rFlagsRegUCF cr, cmpOpUCF cop) %{ predicate(n->in(2)->in(2)->is_Con() && n->in(2)->in(2)->get_int() == 0); @@ -6190,6 +6222,7 @@ instruct cmovI_imm_01UCF(rRegI dst, immI_1 src, rFlagsRegUCF cr, cmpOpUCF cop) %} instruct cmovI_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegI dst, rRegI src) %{ + predicate(!UseAPX); match(Set dst (CMoveI (Binary cop cr) (Binary dst src))); ins_cost(200); expand %{ @@ -6197,8 +6230,19 @@ instruct cmovI_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegI dst, rRegI src) %{ %} %} +instruct cmovI_regUCF_ndd(rRegI dst, cmpOpUCF cop, rFlagsRegUCF cr, rRegI src1, rRegI src2) %{ + predicate(UseAPX); + match(Set dst (CMoveI (Binary cop cr) (Binary src1 src2))); + ins_cost(200); + format %{ "ecmovl$cop $dst, $src1, $src2\t# unsigned, int ndd" %} + ins_encode %{ + __ ecmovl((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src1$$Register, $src2$$Register); + %} + ins_pipe(pipe_cmov_reg); +%} + instruct cmovI_regUCF2_ne(cmpOpUCF2 cop, rFlagsRegUCF cr, rRegI dst, rRegI src) %{ - predicate(n->in(1)->in(1)->as_Bool()->_test._test == BoolTest::ne); + predicate(!UseAPX && n->in(1)->in(1)->as_Bool()->_test._test == BoolTest::ne); match(Set dst (CMoveI (Binary cop cr) (Binary dst src))); ins_cost(200); // XXX @@ -6211,10 +6255,24 @@ instruct cmovI_regUCF2_ne(cmpOpUCF2 cop, rFlagsRegUCF cr, rRegI dst, rRegI src) ins_pipe(pipe_cmov_reg); %} +instruct cmovI_regUCF2_ne_ndd(cmpOpUCF2 cop, rFlagsRegUCF cr, rRegI dst, rRegI src1, rRegI src2) %{ + predicate(UseAPX && n->in(1)->in(1)->as_Bool()->_test._test == BoolTest::ne); + match(Set dst (CMoveI (Binary cop cr) (Binary src1 src2))); + + ins_cost(200); + format %{ "ecmovpl $dst, $src1, $src2\n\t" + "ecmovnel $dst, $src1, $src2" %} + ins_encode %{ + __ ecmovl(Assembler::parity, $dst$$Register, $src1$$Register, $src2$$Register); + __ ecmovl(Assembler::notEqual, $dst$$Register, $src1$$Register, $src2$$Register); + %} + ins_pipe(pipe_cmov_reg); +%} + // Since (x == y) == !(x != y), we can flip the sense of the test by flipping the // inputs of the CMove instruct cmovI_regUCF2_eq(cmpOpUCF2 cop, rFlagsRegUCF cr, rRegI dst, rRegI src) %{ - predicate(n->in(1)->in(1)->as_Bool()->_test._test == BoolTest::eq); + predicate(!UseAPX && n->in(1)->in(1)->as_Bool()->_test._test == BoolTest::eq); match(Set dst (CMoveI (Binary cop cr) (Binary src dst))); ins_cost(200); // XXX @@ -6227,8 +6285,25 @@ instruct cmovI_regUCF2_eq(cmpOpUCF2 cop, rFlagsRegUCF cr, rRegI dst, rRegI src) ins_pipe(pipe_cmov_reg); %} +// We need this special handling for only eq / neq comparison since NaN == NaN is false, +// and parity flag bit is set if any of the operand is a NaN. +instruct cmovI_regUCF2_eq_ndd(cmpOpUCF2 cop, rFlagsRegUCF cr, rRegI dst, rRegI src1, rRegI src2) %{ + predicate(UseAPX && n->in(1)->in(1)->as_Bool()->_test._test == BoolTest::eq); + match(Set dst (CMoveI (Binary cop cr) (Binary src1 src2))); + + ins_cost(200); + format %{ "ecmovpl $dst, $src1, $src2\n\t" + "ecmovnel $dst, $src1, $src2" %} + ins_encode %{ + __ ecmovl(Assembler::parity, $dst$$Register, $src1$$Register, $src2$$Register); + __ ecmovl(Assembler::notEqual, $dst$$Register, $src1$$Register, $src2$$Register); + %} + ins_pipe(pipe_cmov_reg); +%} + // Conditional move instruct cmovI_mem(cmpOp cop, rFlagsReg cr, rRegI dst, memory src) %{ + predicate(!UseAPX); match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src)))); ins_cost(250); // XXX @@ -6239,9 +6314,24 @@ instruct cmovI_mem(cmpOp cop, rFlagsReg cr, rRegI dst, memory src) %{ ins_pipe(pipe_cmov_mem); %} +// Conditional move +instruct cmovI_rReg_rReg_mem_ndd(rRegI dst, cmpOp cop, rFlagsReg cr, rRegI src1, memory src2) +%{ + predicate(UseAPX); + match(Set dst (CMoveI (Binary cop cr) (Binary src1 (LoadI src2)))); + + ins_cost(250); + format %{ "ecmovl$cop $dst, $src1, $src2\t# signed, int ndd" %} + ins_encode %{ + __ ecmovl((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src1$$Register, $src2$$Address); + %} + ins_pipe(pipe_cmov_mem); +%} + // Conditional move instruct cmovI_memU(cmpOpU cop, rFlagsRegU cr, rRegI dst, memory src) %{ + predicate(!UseAPX); match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src)))); ins_cost(250); // XXX @@ -6253,6 +6343,7 @@ instruct cmovI_memU(cmpOpU cop, rFlagsRegU cr, rRegI dst, memory src) %} instruct cmovI_memUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegI dst, memory src) %{ + predicate(!UseAPX); match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src)))); ins_cost(250); expand %{ @@ -6260,9 +6351,35 @@ instruct cmovI_memUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegI dst, memory src) %{ %} %} +instruct cmovI_rReg_rReg_memU_ndd(rRegI dst, cmpOpU cop, rFlagsRegU cr, rRegI src1, memory src2) +%{ + predicate(UseAPX); + match(Set dst (CMoveI (Binary cop cr) (Binary src1 (LoadI src2)))); + + ins_cost(250); + format %{ "ecmovl$cop $dst, $src1, $src2\t# unsigned, int ndd" %} + ins_encode %{ + __ ecmovl((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src1$$Register, $src2$$Address); + %} + ins_pipe(pipe_cmov_mem); +%} + +instruct cmovI_rReg_rReg_memUCF_ndd(rRegI dst, cmpOpUCF cop, rFlagsRegUCF cr, rRegI src1, memory src2) +%{ + predicate(UseAPX); + match(Set dst (CMoveI (Binary cop cr) (Binary src1 (LoadI src2)))); + ins_cost(250); + format %{ "ecmovl$cop $dst, $src1, $src2\t# unsigned, int ndd" %} + ins_encode %{ + __ ecmovl((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src1$$Register, $src2$$Address); + %} + ins_pipe(pipe_cmov_mem); +%} + // Conditional move instruct cmovN_reg(rRegN dst, rRegN src, rFlagsReg cr, cmpOp cop) %{ + predicate(!UseAPX); match(Set dst (CMoveN (Binary cop cr) (Binary dst src))); ins_cost(200); // XXX @@ -6273,9 +6390,24 @@ instruct cmovN_reg(rRegN dst, rRegN src, rFlagsReg cr, cmpOp cop) ins_pipe(pipe_cmov_reg); %} +// Conditional move ndd +instruct cmovN_reg_ndd(rRegN dst, rRegN src1, rRegN src2, rFlagsReg cr, cmpOp cop) +%{ + predicate(UseAPX); + match(Set dst (CMoveN (Binary cop cr) (Binary src1 src2))); + + ins_cost(200); + format %{ "ecmovl$cop $dst, $src1, $src2\t# signed, compressed ptr ndd" %} + ins_encode %{ + __ ecmovl((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src1$$Register, $src2$$Register); + %} + ins_pipe(pipe_cmov_reg); +%} + // Conditional move instruct cmovN_regU(cmpOpU cop, rFlagsRegU cr, rRegN dst, rRegN src) %{ + predicate(!UseAPX); match(Set dst (CMoveN (Binary cop cr) (Binary dst src))); ins_cost(200); // XXX @@ -6287,6 +6419,7 @@ instruct cmovN_regU(cmpOpU cop, rFlagsRegU cr, rRegN dst, rRegN src) %} instruct cmovN_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegN dst, rRegN src) %{ + predicate(!UseAPX); match(Set dst (CMoveN (Binary cop cr) (Binary dst src))); ins_cost(200); expand %{ @@ -6294,6 +6427,31 @@ instruct cmovN_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegN dst, rRegN src) %{ %} %} +// Conditional move ndd +instruct cmovN_regU_ndd(rRegN dst, cmpOpU cop, rFlagsRegU cr, rRegN src1, rRegN src2) +%{ + predicate(UseAPX); + match(Set dst (CMoveN (Binary cop cr) (Binary src1 src2))); + + ins_cost(200); + format %{ "ecmovl$cop $dst, $src1, $src2\t# unsigned, compressed ptr ndd" %} + ins_encode %{ + __ ecmovl((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src1$$Register, $src2$$Register); + %} + ins_pipe(pipe_cmov_reg); +%} + +instruct cmovN_regUCF_ndd(rRegN dst, cmpOpUCF cop, rFlagsRegUCF cr, rRegN src1, rRegN src2) %{ + predicate(UseAPX); + match(Set dst (CMoveN (Binary cop cr) (Binary src1 src2))); + ins_cost(200); + format %{ "ecmovl$cop $dst, $src1, $src2\t# unsigned, compressed ptr ndd" %} + ins_encode %{ + __ ecmovl((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src1$$Register, $src2$$Register); + %} + ins_pipe(pipe_cmov_reg); +%} + instruct cmovN_regUCF2_ne(cmpOpUCF2 cop, rFlagsRegUCF cr, rRegN dst, rRegN src) %{ predicate(n->in(1)->in(1)->as_Bool()->_test._test == BoolTest::ne); match(Set dst (CMoveN (Binary cop cr) (Binary dst src))); @@ -6327,6 +6485,7 @@ instruct cmovN_regUCF2_eq(cmpOpUCF2 cop, rFlagsRegUCF cr, rRegN dst, rRegN src) // Conditional move instruct cmovP_reg(rRegP dst, rRegP src, rFlagsReg cr, cmpOp cop) %{ + predicate(!UseAPX); match(Set dst (CMoveP (Binary cop cr) (Binary dst src))); ins_cost(200); // XXX @@ -6337,9 +6496,24 @@ instruct cmovP_reg(rRegP dst, rRegP src, rFlagsReg cr, cmpOp cop) ins_pipe(pipe_cmov_reg); // XXX %} +// Conditional move ndd +instruct cmovP_reg_ndd(rRegP dst, rRegP src1, rRegP src2, rFlagsReg cr, cmpOp cop) +%{ + predicate(UseAPX); + match(Set dst (CMoveP (Binary cop cr) (Binary src1 src2))); + + ins_cost(200); + format %{ "ecmovq$cop $dst, $src1, $src2\t# signed, ptr ndd" %} + ins_encode %{ + __ ecmovq((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src1$$Register, $src2$$Register); + %} + ins_pipe(pipe_cmov_reg); +%} + // Conditional move instruct cmovP_regU(cmpOpU cop, rFlagsRegU cr, rRegP dst, rRegP src) %{ + predicate(!UseAPX); match(Set dst (CMoveP (Binary cop cr) (Binary dst src))); ins_cost(200); // XXX @@ -6350,6 +6524,20 @@ instruct cmovP_regU(cmpOpU cop, rFlagsRegU cr, rRegP dst, rRegP src) ins_pipe(pipe_cmov_reg); // XXX %} +// Conditional move ndd +instruct cmovP_regU_ndd(rRegP dst, cmpOpU cop, rFlagsRegU cr, rRegP src1, rRegP src2) +%{ + predicate(UseAPX); + match(Set dst (CMoveP (Binary cop cr) (Binary src1 src2))); + + ins_cost(200); + format %{ "ecmovq$cop $dst, $src1, $src2\t# unsigned, ptr ndd" %} + ins_encode %{ + __ ecmovq((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src1$$Register, $src2$$Register); + %} + ins_pipe(pipe_cmov_reg); +%} + instruct cmovP_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegP dst, rRegP src) %{ match(Set dst (CMoveP (Binary cop cr) (Binary dst src))); ins_cost(200); @@ -6358,8 +6546,18 @@ instruct cmovP_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegP dst, rRegP src) %{ %} %} +instruct cmovP_regUCF_ndd(rRegP dst, cmpOpUCF cop, rFlagsRegUCF cr, rRegP src1, rRegP src2) %{ + match(Set dst (CMoveP (Binary cop cr) (Binary src1 src2))); + ins_cost(200); + format %{ "ecmovq$cop $dst, $src1, $src2\t# unsigned, ptr ndd" %} + ins_encode %{ + __ ecmovq((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src1$$Register, $src2$$Register); + %} + ins_pipe(pipe_cmov_reg); +%} + instruct cmovP_regUCF2_ne(cmpOpUCF2 cop, rFlagsRegUCF cr, rRegP dst, rRegP src) %{ - predicate(n->in(1)->in(1)->as_Bool()->_test._test == BoolTest::ne); + predicate(!UseAPX && n->in(1)->in(1)->as_Bool()->_test._test == BoolTest::ne); match(Set dst (CMoveP (Binary cop cr) (Binary dst src))); ins_cost(200); // XXX @@ -6372,10 +6570,24 @@ instruct cmovP_regUCF2_ne(cmpOpUCF2 cop, rFlagsRegUCF cr, rRegP dst, rRegP src) ins_pipe(pipe_cmov_reg); %} +instruct cmovP_regUCF2_ne_ndd(cmpOpUCF2 cop, rFlagsRegUCF cr, rRegP dst, rRegP src1, rRegP src2) %{ + predicate(UseAPX && n->in(1)->in(1)->as_Bool()->_test._test == BoolTest::ne); + match(Set dst (CMoveP (Binary cop cr) (Binary src1 src2))); + + ins_cost(200); + format %{ "ecmovpq $dst, $src1, $src2\n\t" + "ecmovneq $dst, $src1, $src2" %} + ins_encode %{ + __ ecmovq(Assembler::parity, $dst$$Register, $src1$$Register, $src2$$Register); + __ ecmovq(Assembler::notEqual, $dst$$Register, $src1$$Register, $src2$$Register); + %} + ins_pipe(pipe_cmov_reg); +%} + // Since (x == y) == !(x != y), we can flip the sense of the test by flipping the // inputs of the CMove instruct cmovP_regUCF2_eq(cmpOpUCF2 cop, rFlagsRegUCF cr, rRegP dst, rRegP src) %{ - predicate(n->in(1)->in(1)->as_Bool()->_test._test == BoolTest::eq); + predicate(!UseAPX && n->in(1)->in(1)->as_Bool()->_test._test == BoolTest::eq); match(Set dst (CMoveP (Binary cop cr) (Binary src dst))); ins_cost(200); // XXX @@ -6388,6 +6600,20 @@ instruct cmovP_regUCF2_eq(cmpOpUCF2 cop, rFlagsRegUCF cr, rRegP dst, rRegP src) ins_pipe(pipe_cmov_reg); %} +instruct cmovP_regUCF2_eq_ndd(cmpOpUCF2 cop, rFlagsRegUCF cr, rRegP dst, rRegP src1, rRegP src2) %{ + predicate(UseAPX && n->in(1)->in(1)->as_Bool()->_test._test == BoolTest::eq); + match(Set dst (CMoveP (Binary cop cr) (Binary src1 src2))); + + ins_cost(200); + format %{ "ecmovpq $dst, $src1, $src2\n\t" + "ecmovneq $dst, $src1, $src2" %} + ins_encode %{ + __ ecmovq(Assembler::parity, $dst$$Register, $src1$$Register, $src2$$Register); + __ ecmovq(Assembler::notEqual, $dst$$Register, $src1$$Register, $src2$$Register); + %} + ins_pipe(pipe_cmov_reg); +%} + instruct cmovL_imm_01(rRegL dst, immL1 src, rFlagsReg cr, cmpOp cop) %{ predicate(n->in(2)->in(2)->is_Con() && n->in(2)->in(2)->get_long() == 0); @@ -6404,6 +6630,7 @@ instruct cmovL_imm_01(rRegL dst, immL1 src, rFlagsReg cr, cmpOp cop) instruct cmovL_reg(cmpOp cop, rFlagsReg cr, rRegL dst, rRegL src) %{ + predicate(!UseAPX); match(Set dst (CMoveL (Binary cop cr) (Binary dst src))); ins_cost(200); // XXX @@ -6414,8 +6641,22 @@ instruct cmovL_reg(cmpOp cop, rFlagsReg cr, rRegL dst, rRegL src) ins_pipe(pipe_cmov_reg); // XXX %} +instruct cmovL_reg_ndd(rRegL dst, cmpOp cop, rFlagsReg cr, rRegL src1, rRegL src2) +%{ + predicate(UseAPX); + match(Set dst (CMoveL (Binary cop cr) (Binary src1 src2))); + + ins_cost(200); + format %{ "ecmovq$cop $dst, $src1, $src2\t# signed, long ndd" %} + ins_encode %{ + __ ecmovq((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src1$$Register, $src2$$Register); + %} + ins_pipe(pipe_cmov_reg); +%} + instruct cmovL_mem(cmpOp cop, rFlagsReg cr, rRegL dst, memory src) %{ + predicate(!UseAPX); match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src)))); ins_cost(200); // XXX @@ -6426,6 +6667,19 @@ instruct cmovL_mem(cmpOp cop, rFlagsReg cr, rRegL dst, memory src) ins_pipe(pipe_cmov_mem); // XXX %} +instruct cmovL_rReg_rReg_mem_ndd(rRegL dst, cmpOp cop, rFlagsReg cr, rRegL src1, memory src2) +%{ + predicate(UseAPX); + match(Set dst (CMoveL (Binary cop cr) (Binary src1 (LoadL src2)))); + + ins_cost(200); + format %{ "ecmovq$cop $dst, $src1, $src2\t# signed, long ndd" %} + ins_encode %{ + __ ecmovq((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src1$$Register, $src2$$Address); + %} + ins_pipe(pipe_cmov_mem); +%} + instruct cmovL_imm_01U(rRegL dst, immL1 src, rFlagsRegU cr, cmpOpU cop) %{ predicate(n->in(2)->in(2)->is_Con() && n->in(2)->in(2)->get_long() == 0); @@ -6442,6 +6696,7 @@ instruct cmovL_imm_01U(rRegL dst, immL1 src, rFlagsRegU cr, cmpOpU cop) instruct cmovL_regU(cmpOpU cop, rFlagsRegU cr, rRegL dst, rRegL src) %{ + predicate(!UseAPX); match(Set dst (CMoveL (Binary cop cr) (Binary dst src))); ins_cost(200); // XXX @@ -6452,6 +6707,19 @@ instruct cmovL_regU(cmpOpU cop, rFlagsRegU cr, rRegL dst, rRegL src) ins_pipe(pipe_cmov_reg); // XXX %} +instruct cmovL_regU_ndd(rRegL dst, cmpOpU cop, rFlagsRegU cr, rRegL src1, rRegL src2) +%{ + predicate(UseAPX); + match(Set dst (CMoveL (Binary cop cr) (Binary src1 src2))); + + ins_cost(200); + format %{ "ecmovq$cop $dst, $src1, $src2\t# unsigned, long ndd" %} + ins_encode %{ + __ ecmovq((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src1$$Register, $src2$$Register); + %} + ins_pipe(pipe_cmov_reg); +%} + instruct cmovL_imm_01UCF(rRegL dst, immL1 src, rFlagsRegUCF cr, cmpOpUCF cop) %{ predicate(n->in(2)->in(2)->is_Con() && n->in(2)->in(2)->get_long() == 0); @@ -6467,6 +6735,7 @@ instruct cmovL_imm_01UCF(rRegL dst, immL1 src, rFlagsRegUCF cr, cmpOpUCF cop) %} instruct cmovL_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegL dst, rRegL src) %{ + predicate(!UseAPX); match(Set dst (CMoveL (Binary cop cr) (Binary dst src))); ins_cost(200); expand %{ @@ -6474,8 +6743,20 @@ instruct cmovL_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegL dst, rRegL src) %{ %} %} +instruct cmovL_regUCF_ndd(rRegL dst, cmpOpUCF cop, rFlagsRegUCF cr, rRegL src1, rRegL src2) +%{ + predicate(UseAPX); + match(Set dst (CMoveL (Binary cop cr) (Binary src1 src2))); + ins_cost(200); + format %{ "ecmovq$cop $dst, $src1, $src2\t# unsigned, long ndd" %} + ins_encode %{ + __ ecmovq((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src1$$Register, $src2$$Register); + %} + ins_pipe(pipe_cmov_reg); +%} + instruct cmovL_regUCF2_ne(cmpOpUCF2 cop, rFlagsRegUCF cr, rRegL dst, rRegL src) %{ - predicate(n->in(1)->in(1)->as_Bool()->_test._test == BoolTest::ne); + predicate(!UseAPX && n->in(1)->in(1)->as_Bool()->_test._test == BoolTest::ne); match(Set dst (CMoveL (Binary cop cr) (Binary dst src))); ins_cost(200); // XXX @@ -6488,10 +6769,24 @@ instruct cmovL_regUCF2_ne(cmpOpUCF2 cop, rFlagsRegUCF cr, rRegL dst, rRegL src) ins_pipe(pipe_cmov_reg); %} +instruct cmovL_regUCF2_ne_ndd(cmpOpUCF2 cop, rFlagsRegUCF cr, rRegL dst, rRegL src1, rRegL src2) %{ + predicate(UseAPX && n->in(1)->in(1)->as_Bool()->_test._test == BoolTest::ne); + match(Set dst (CMoveL (Binary cop cr) (Binary src1 src2))); + + ins_cost(200); + format %{ "ecmovpq $dst, $src1, $src2\n\t" + "ecmovneq $dst, $src1, $src2" %} + ins_encode %{ + __ ecmovq(Assembler::parity, $dst$$Register, $src1$$Register, $src2$$Register); + __ ecmovq(Assembler::notEqual, $dst$$Register, $src1$$Register, $src2$$Register); + %} + ins_pipe(pipe_cmov_reg); +%} + // Since (x == y) == !(x != y), we can flip the sense of the test by flipping the // inputs of the CMove instruct cmovL_regUCF2_eq(cmpOpUCF2 cop, rFlagsRegUCF cr, rRegL dst, rRegL src) %{ - predicate(n->in(1)->in(1)->as_Bool()->_test._test == BoolTest::eq); + predicate(!UseAPX && n->in(1)->in(1)->as_Bool()->_test._test == BoolTest::eq); match(Set dst (CMoveL (Binary cop cr) (Binary src dst))); ins_cost(200); // XXX @@ -6504,8 +6799,23 @@ instruct cmovL_regUCF2_eq(cmpOpUCF2 cop, rFlagsRegUCF cr, rRegL dst, rRegL src) ins_pipe(pipe_cmov_reg); %} +instruct cmovL_regUCF2_eq_ndd(cmpOpUCF2 cop, rFlagsRegUCF cr, rRegL dst, rRegL src1, rRegL src2) %{ + predicate(UseAPX && n->in(1)->in(1)->as_Bool()->_test._test == BoolTest::eq); + match(Set dst (CMoveL (Binary cop cr) (Binary src1 src2))); + + ins_cost(200); + format %{ "ecmovpq $dst, $src1, $src2\n\t" + "ecmovneq $dst, $src1, $src2" %} + ins_encode %{ + __ ecmovq(Assembler::parity, $dst$$Register, $src1$$Register, $src2$$Register); + __ ecmovq(Assembler::notEqual, $dst$$Register, $src1$$Register, $src2$$Register); + %} + ins_pipe(pipe_cmov_reg); +%} + instruct cmovL_memU(cmpOpU cop, rFlagsRegU cr, rRegL dst, memory src) %{ + predicate(!UseAPX); match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src)))); ins_cost(200); // XXX @@ -6517,6 +6827,7 @@ instruct cmovL_memU(cmpOpU cop, rFlagsRegU cr, rRegL dst, memory src) %} instruct cmovL_memUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegL dst, memory src) %{ + predicate(!UseAPX); match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src)))); ins_cost(200); expand %{ @@ -6524,6 +6835,31 @@ instruct cmovL_memUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegL dst, memory src) %{ %} %} +instruct cmovL_rReg_rReg_memU_ndd(rRegL dst, cmpOpU cop, rFlagsRegU cr, rRegL src1, memory src2) +%{ + predicate(UseAPX); + match(Set dst (CMoveL (Binary cop cr) (Binary src1 (LoadL src2)))); + + ins_cost(200); + format %{ "ecmovq$cop $dst, $src1, $src2\t# unsigned, long ndd" %} + ins_encode %{ + __ ecmovq((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src1$$Register, $src2$$Address); + %} + ins_pipe(pipe_cmov_mem); +%} + +instruct cmovL_rReg_rReg_memUCF_ndd(rRegL dst, cmpOpUCF cop, rFlagsRegUCF cr, rRegL src1, memory src2) +%{ + predicate(UseAPX); + match(Set dst (CMoveL (Binary cop cr) (Binary src1 (LoadL src2)))); + ins_cost(200); + format %{ "ecmovq$cop $dst, $src1, $src2\t# unsigned, long ndd" %} + ins_encode %{ + __ ecmovq((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src1$$Register, $src2$$Address); + %} + ins_pipe(pipe_cmov_mem); +%} + instruct cmovF_reg(cmpOp cop, rFlagsReg cr, regF dst, regF src) %{ match(Set dst (CMoveF (Binary cop cr) (Binary dst src))); @@ -6617,6 +6953,7 @@ instruct cmovD_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, regD dst, regD src) %{ instruct addI_rReg(rRegI dst, rRegI src, rFlagsReg cr) %{ + predicate(!UseAPX); match(Set dst (AddI dst src)); effect(KILL cr); flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag); @@ -6627,8 +6964,23 @@ instruct addI_rReg(rRegI dst, rRegI src, rFlagsReg cr) ins_pipe(ialu_reg_reg); %} +instruct addI_rReg_ndd(rRegI dst, rRegI src1, rRegI src2, rFlagsReg cr) +%{ + predicate(UseAPX); + match(Set dst (AddI src1 src2)); + effect(KILL cr); + flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag); + + format %{ "eaddl $dst, $src1, $src2\t# int ndd" %} + ins_encode %{ + __ eaddl($dst$$Register, $src1$$Register, $src2$$Register, false); + %} + ins_pipe(ialu_reg_reg); +%} + instruct addI_rReg_imm(rRegI dst, immI src, rFlagsReg cr) %{ + predicate(!UseAPX); match(Set dst (AddI dst src)); effect(KILL cr); flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag); @@ -6640,8 +6992,37 @@ instruct addI_rReg_imm(rRegI dst, immI src, rFlagsReg cr) ins_pipe( ialu_reg ); %} +instruct addI_rReg_rReg_imm_ndd(rRegI dst, rRegI src1, immI src2, rFlagsReg cr) +%{ + predicate(UseAPX); + match(Set dst (AddI src1 src2)); + effect(KILL cr); + flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag); + + format %{ "eaddl $dst, $src1, $src2\t# int ndd" %} + ins_encode %{ + __ eaddl($dst$$Register, $src1$$Register, $src2$$constant, false); + %} + ins_pipe( ialu_reg ); +%} + +instruct addI_rReg_mem_imm_ndd(rRegI dst, memory src1, immI src2, rFlagsReg cr) +%{ + predicate(UseAPX); + match(Set dst (AddI (LoadI src1) src2)); + effect(KILL cr); + flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag); + + format %{ "eaddl $dst, $src1, $src2\t# int ndd" %} + ins_encode %{ + __ eaddl($dst$$Register, $src1$$Address, $src2$$constant, false); + %} + ins_pipe( ialu_reg ); +%} + instruct addI_rReg_mem(rRegI dst, memory src, rFlagsReg cr) %{ + predicate(!UseAPX); match(Set dst (AddI dst (LoadI src))); effect(KILL cr); flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag); @@ -6654,6 +7035,36 @@ instruct addI_rReg_mem(rRegI dst, memory src, rFlagsReg cr) ins_pipe(ialu_reg_mem); %} +instruct addI_rReg_mem_rReg_ndd(rRegI dst, memory src1, rRegI src2, rFlagsReg cr) +%{ + predicate(UseAPX); + match(Set dst (AddI (LoadI src1) src2)); + effect(KILL cr); + flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag); + + ins_cost(150); + format %{ "eaddl $dst, $src1, $src2\t# int ndd" %} + ins_encode %{ + __ eaddl($dst$$Register, $src1$$Address, $src2$$Register, false); + %} + ins_pipe(ialu_reg_mem); +%} + +instruct addI_rReg_rReg_mem_ndd(rRegI dst, rRegI src1, memory src2, rFlagsReg cr) +%{ + predicate(UseAPX); + match(Set dst (AddI src1 (LoadI src2))); + effect(KILL cr); + flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag); + + ins_cost(150); + format %{ "eaddl $dst, $src1, $src2\t# int ndd" %} + ins_encode %{ + __ eaddl($dst$$Register, $src1$$Register, $src2$$Address, false); + %} + ins_pipe(ialu_reg_mem); +%} + instruct addI_mem_rReg(memory dst, rRegI src, rFlagsReg cr) %{ match(Set dst (StoreI dst (AddI (LoadI dst) src))); @@ -6685,7 +7096,7 @@ instruct addI_mem_imm(memory dst, immI src, rFlagsReg cr) instruct incI_rReg(rRegI dst, immI_1 src, rFlagsReg cr) %{ - predicate(UseIncDec); + predicate(!UseAPX && UseIncDec); match(Set dst (AddI dst src)); effect(KILL cr); @@ -6696,6 +7107,32 @@ instruct incI_rReg(rRegI dst, immI_1 src, rFlagsReg cr) ins_pipe(ialu_reg); %} +instruct incI_rReg_ndd(rRegI dst, rRegI src, immI_1 val, rFlagsReg cr) +%{ + predicate(UseAPX && UseIncDec); + match(Set dst (AddI src val)); + effect(KILL cr); + + format %{ "eincl $dst, $src\t# int ndd" %} + ins_encode %{ + __ eincl($dst$$Register, $src$$Register, false); + %} + ins_pipe(ialu_reg); +%} + +instruct incI_rReg_mem_ndd(rRegI dst, memory src, immI_1 val, rFlagsReg cr) +%{ + predicate(UseAPX && UseIncDec); + match(Set dst (AddI (LoadI src) val)); + effect(KILL cr); + + format %{ "eincl $dst, $src\t# int ndd" %} + ins_encode %{ + __ eincl($dst$$Register, $src$$Address, false); + %} + ins_pipe(ialu_reg); +%} + instruct incI_mem(memory dst, immI_1 src, rFlagsReg cr) %{ predicate(UseIncDec); @@ -6713,7 +7150,7 @@ instruct incI_mem(memory dst, immI_1 src, rFlagsReg cr) // XXX why does that use AddI instruct decI_rReg(rRegI dst, immI_M1 src, rFlagsReg cr) %{ - predicate(UseIncDec); + predicate(!UseAPX && UseIncDec); match(Set dst (AddI dst src)); effect(KILL cr); @@ -6724,6 +7161,32 @@ instruct decI_rReg(rRegI dst, immI_M1 src, rFlagsReg cr) ins_pipe(ialu_reg); %} +instruct decI_rReg_ndd(rRegI dst, rRegI src, immI_M1 val, rFlagsReg cr) +%{ + predicate(UseAPX && UseIncDec); + match(Set dst (AddI src val)); + effect(KILL cr); + + format %{ "edecl $dst, $src\t# int ndd" %} + ins_encode %{ + __ edecl($dst$$Register, $src$$Register, false); + %} + ins_pipe(ialu_reg); +%} + +instruct decI_rReg_mem_ndd(rRegI dst, memory src, immI_M1 val, rFlagsReg cr) +%{ + predicate(UseAPX && UseIncDec); + match(Set dst (AddI (LoadI src) val)); + effect(KILL cr); + + format %{ "edecl $dst, $src\t# int ndd" %} + ins_encode %{ + __ edecl($dst$$Register, $src$$Address, false); + %} + ins_pipe(ialu_reg); +%} + // XXX why does that use AddI instruct decI_mem(memory dst, immI_M1 src, rFlagsReg cr) %{ @@ -6792,6 +7255,7 @@ instruct leaI_rReg_rReg_immI2_immI(rRegI dst, rRegI base, rRegI index, immI2 sca instruct addL_rReg(rRegL dst, rRegL src, rFlagsReg cr) %{ + predicate(!UseAPX); match(Set dst (AddL dst src)); effect(KILL cr); flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag); @@ -6803,8 +7267,23 @@ instruct addL_rReg(rRegL dst, rRegL src, rFlagsReg cr) ins_pipe(ialu_reg_reg); %} +instruct addL_rReg_ndd(rRegL dst, rRegL src1, rRegL src2, rFlagsReg cr) +%{ + predicate(UseAPX); + match(Set dst (AddL src1 src2)); + effect(KILL cr); + flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag); + + format %{ "eaddq $dst, $src1, $src2\t# long ndd" %} + ins_encode %{ + __ eaddq($dst$$Register, $src1$$Register, $src2$$Register, false); + %} + ins_pipe(ialu_reg_reg); +%} + instruct addL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr) %{ + predicate(!UseAPX); match(Set dst (AddL dst src)); effect(KILL cr); flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag); @@ -6816,8 +7295,37 @@ instruct addL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr) ins_pipe( ialu_reg ); %} +instruct addL_rReg_rReg_imm_ndd(rRegL dst, rRegL src1, immL32 src2, rFlagsReg cr) +%{ + predicate(UseAPX); + match(Set dst (AddL src1 src2)); + effect(KILL cr); + flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag); + + format %{ "eaddq $dst, $src1, $src2\t# long ndd" %} + ins_encode %{ + __ eaddq($dst$$Register, $src1$$Register, $src2$$constant, false); + %} + ins_pipe( ialu_reg ); +%} + +instruct addL_rReg_mem_imm_ndd(rRegL dst, memory src1, immL32 src2, rFlagsReg cr) +%{ + predicate(UseAPX); + match(Set dst (AddL (LoadL src1) src2)); + effect(KILL cr); + flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag); + + format %{ "eaddq $dst, $src1, $src2\t# long ndd" %} + ins_encode %{ + __ eaddq($dst$$Register, $src1$$Address, $src2$$constant, false); + %} + ins_pipe( ialu_reg ); +%} + instruct addL_rReg_mem(rRegL dst, memory src, rFlagsReg cr) %{ + predicate(!UseAPX); match(Set dst (AddL dst (LoadL src))); effect(KILL cr); flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag); @@ -6830,6 +7338,36 @@ instruct addL_rReg_mem(rRegL dst, memory src, rFlagsReg cr) ins_pipe(ialu_reg_mem); %} +instruct addL_rReg_rReg_mem_ndd(rRegL dst, rRegL src1, memory src2, rFlagsReg cr) +%{ + predicate(UseAPX); + match(Set dst (AddL src1 (LoadL src2))); + effect(KILL cr); + flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag); + + ins_cost(150); + format %{ "eaddq $dst, $src1, $src2\t# long ndd" %} + ins_encode %{ + __ eaddq($dst$$Register, $src1$$Register, $src2$$Address, false); + %} + ins_pipe(ialu_reg_mem); +%} + +instruct addL_rReg_mem_rReg_ndd(rRegL dst, memory src1, rRegL src2, rFlagsReg cr) +%{ + predicate(UseAPX); + match(Set dst (AddL (LoadL src1) src2)); + effect(KILL cr); + flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag); + + ins_cost(150); + format %{ "eaddq $dst, $src1, $src2\t# long ndd" %} + ins_encode %{ + __ eaddq($dst$$Register, $src1$$Address, $src2$$Register, false); + %} + ins_pipe(ialu_reg_mem); +%} + instruct addL_mem_rReg(memory dst, rRegL src, rFlagsReg cr) %{ match(Set dst (StoreL dst (AddL (LoadL dst) src))); @@ -6860,7 +7398,7 @@ instruct addL_mem_imm(memory dst, immL32 src, rFlagsReg cr) instruct incL_rReg(rRegI dst, immL1 src, rFlagsReg cr) %{ - predicate(UseIncDec); + predicate(!UseAPX && UseIncDec); match(Set dst (AddL dst src)); effect(KILL cr); @@ -6871,6 +7409,32 @@ instruct incL_rReg(rRegI dst, immL1 src, rFlagsReg cr) ins_pipe(ialu_reg); %} +instruct incL_rReg_ndd(rRegI dst, rRegI src, immL1 val, rFlagsReg cr) +%{ + predicate(UseAPX && UseIncDec); + match(Set dst (AddL src val)); + effect(KILL cr); + + format %{ "eincq $dst, $src\t# long ndd" %} + ins_encode %{ + __ eincq($dst$$Register, $src$$Register, false); + %} + ins_pipe(ialu_reg); +%} + +instruct incL_rReg_mem_ndd(rRegI dst, memory src, immL1 val, rFlagsReg cr) +%{ + predicate(UseAPX && UseIncDec); + match(Set dst (AddL (LoadL src) val)); + effect(KILL cr); + + format %{ "eincq $dst, $src\t# long ndd" %} + ins_encode %{ + __ eincq($dst$$Register, $src$$Address, false); + %} + ins_pipe(ialu_reg); +%} + instruct incL_mem(memory dst, immL1 src, rFlagsReg cr) %{ predicate(UseIncDec); @@ -6888,7 +7452,7 @@ instruct incL_mem(memory dst, immL1 src, rFlagsReg cr) // XXX why does that use AddL instruct decL_rReg(rRegL dst, immL_M1 src, rFlagsReg cr) %{ - predicate(UseIncDec); + predicate(!UseAPX && UseIncDec); match(Set dst (AddL dst src)); effect(KILL cr); @@ -6899,6 +7463,32 @@ instruct decL_rReg(rRegL dst, immL_M1 src, rFlagsReg cr) ins_pipe(ialu_reg); %} +instruct decL_rReg_ndd(rRegL dst, rRegL src, immL_M1 val, rFlagsReg cr) +%{ + predicate(UseAPX && UseIncDec); + match(Set dst (AddL src val)); + effect(KILL cr); + + format %{ "edecq $dst, $src\t# long ndd" %} + ins_encode %{ + __ edecq($dst$$Register, $src$$Register, false); + %} + ins_pipe(ialu_reg); +%} + +instruct decL_rReg_mem_ndd(rRegL dst, memory src, immL_M1 val, rFlagsReg cr) +%{ + predicate(UseAPX && UseIncDec); + match(Set dst (AddL (LoadL src) val)); + effect(KILL cr); + + format %{ "edecq $dst, $src\t# long ndd" %} + ins_encode %{ + __ edecq($dst$$Register, $src$$Address, false); + %} + ins_pipe(ialu_reg); +%} + // XXX why does that use AddL instruct decL_mem(memory dst, immL_M1 src, rFlagsReg cr) %{ @@ -7534,6 +8124,7 @@ instruct absL_rReg(rRegL dst, rRegL src, rFlagsReg cr) // Integer Subtraction Instructions instruct subI_rReg(rRegI dst, rRegI src, rFlagsReg cr) %{ + predicate(!UseAPX); match(Set dst (SubI dst src)); effect(KILL cr); flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag); @@ -7545,8 +8136,51 @@ instruct subI_rReg(rRegI dst, rRegI src, rFlagsReg cr) ins_pipe(ialu_reg_reg); %} +instruct subI_rReg_ndd(rRegI dst, rRegI src1, rRegI src2, rFlagsReg cr) +%{ + predicate(UseAPX); + match(Set dst (SubI src1 src2)); + effect(KILL cr); + flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag); + + format %{ "esubl $dst, $src1, $src2\t# int ndd" %} + ins_encode %{ + __ esubl($dst$$Register, $src1$$Register, $src2$$Register, false); + %} + ins_pipe(ialu_reg_reg); +%} + +instruct subI_rReg_rReg_imm_ndd(rRegI dst, rRegI src1, immI src2, rFlagsReg cr) +%{ + predicate(UseAPX); + match(Set dst (SubI src1 src2)); + effect(KILL cr); + flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag); + + format %{ "esubl $dst, $src1, $src2\t# int ndd" %} + ins_encode %{ + __ esubl($dst$$Register, $src1$$Register, $src2$$constant, false); + %} + ins_pipe(ialu_reg_reg); +%} + +instruct subI_rReg_mem_imm_ndd(rRegI dst, memory src1, immI src2, rFlagsReg cr) +%{ + predicate(UseAPX); + match(Set dst (SubI (LoadI src1) src2)); + effect(KILL cr); + flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag); + + format %{ "esubl $dst, $src1, $src2\t# int ndd" %} + ins_encode %{ + __ esubl($dst$$Register, $src1$$Address, $src2$$constant, false); + %} + ins_pipe(ialu_reg_reg); +%} + instruct subI_rReg_mem(rRegI dst, memory src, rFlagsReg cr) %{ + predicate(!UseAPX); match(Set dst (SubI dst (LoadI src))); effect(KILL cr); flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag); @@ -7559,6 +8193,36 @@ instruct subI_rReg_mem(rRegI dst, memory src, rFlagsReg cr) ins_pipe(ialu_reg_mem); %} +instruct subI_rReg_rReg_mem_ndd(rRegI dst, rRegI src1, memory src2, rFlagsReg cr) +%{ + predicate(UseAPX); + match(Set dst (SubI src1 (LoadI src2))); + effect(KILL cr); + flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag); + + ins_cost(150); + format %{ "esubl $dst, $src1, $src2\t# int ndd" %} + ins_encode %{ + __ esubl($dst$$Register, $src1$$Register, $src2$$Address, false); + %} + ins_pipe(ialu_reg_mem); +%} + +instruct subI_rReg_mem_rReg_ndd(rRegI dst, memory src1, rRegI src2, rFlagsReg cr) +%{ + predicate(UseAPX); + match(Set dst (SubI (LoadI src1) src2)); + effect(KILL cr); + flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag); + + ins_cost(150); + format %{ "esubl $dst, $src1, $src2\t# int ndd" %} + ins_encode %{ + __ esubl($dst$$Register, $src1$$Address, $src2$$Register, false); + %} + ins_pipe(ialu_reg_mem); +%} + instruct subI_mem_rReg(memory dst, rRegI src, rFlagsReg cr) %{ match(Set dst (StoreI dst (SubI (LoadI dst) src))); @@ -7575,6 +8239,7 @@ instruct subI_mem_rReg(memory dst, rRegI src, rFlagsReg cr) instruct subL_rReg(rRegL dst, rRegL src, rFlagsReg cr) %{ + predicate(!UseAPX); match(Set dst (SubL dst src)); effect(KILL cr); flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag); @@ -7586,8 +8251,51 @@ instruct subL_rReg(rRegL dst, rRegL src, rFlagsReg cr) ins_pipe(ialu_reg_reg); %} +instruct subL_rReg_ndd(rRegL dst, rRegL src1, rRegL src2, rFlagsReg cr) +%{ + predicate(UseAPX); + match(Set dst (SubL src1 src2)); + effect(KILL cr); + flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag); + + format %{ "esubq $dst, $src1, $src2\t# long ndd" %} + ins_encode %{ + __ esubq($dst$$Register, $src1$$Register, $src2$$Register, false); + %} + ins_pipe(ialu_reg_reg); +%} + +instruct subL_rReg_rReg_imm_ndd(rRegL dst, rRegL src1, immL32 src2, rFlagsReg cr) +%{ + predicate(UseAPX); + match(Set dst (SubL src1 src2)); + effect(KILL cr); + flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag); + + format %{ "esubq $dst, $src1, $src2\t# long ndd" %} + ins_encode %{ + __ esubq($dst$$Register, $src1$$Register, $src2$$constant, false); + %} + ins_pipe(ialu_reg_reg); +%} + +instruct subL_rReg_mem_imm_ndd(rRegL dst, memory src1, immL32 src2, rFlagsReg cr) +%{ + predicate(UseAPX); + match(Set dst (SubL (LoadL src1) src2)); + effect(KILL cr); + flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag); + + format %{ "esubq $dst, $src1, $src2\t# long ndd" %} + ins_encode %{ + __ esubq($dst$$Register, $src1$$Address, $src2$$constant, false); + %} + ins_pipe(ialu_reg_reg); +%} + instruct subL_rReg_mem(rRegL dst, memory src, rFlagsReg cr) %{ + predicate(!UseAPX); match(Set dst (SubL dst (LoadL src))); effect(KILL cr); flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag); @@ -7600,6 +8308,36 @@ instruct subL_rReg_mem(rRegL dst, memory src, rFlagsReg cr) ins_pipe(ialu_reg_mem); %} +instruct subL_rReg_rReg_mem_ndd(rRegL dst, rRegL src1, memory src2, rFlagsReg cr) +%{ + predicate(UseAPX); + match(Set dst (SubL src1 (LoadL src2))); + effect(KILL cr); + flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag); + + ins_cost(150); + format %{ "esubq $dst, $src1, $src2\t# long ndd" %} + ins_encode %{ + __ esubq($dst$$Register, $src1$$Register, $src2$$Address, false); + %} + ins_pipe(ialu_reg_mem); +%} + +instruct subL_rReg_mem_rReg_ndd(rRegL dst, memory src1, rRegL src2, rFlagsReg cr) +%{ + predicate(UseAPX); + match(Set dst (SubL (LoadL src1) src2)); + effect(KILL cr); + flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag); + + ins_cost(150); + format %{ "esubq $dst, $src1, $src2\t# long ndd" %} + ins_encode %{ + __ esubq($dst$$Register, $src1$$Address, $src2$$Register, false); + %} + ins_pipe(ialu_reg_mem); +%} + instruct subL_mem_rReg(memory dst, rRegL src, rFlagsReg cr) %{ match(Set dst (StoreL dst (SubL (LoadL dst) src))); @@ -7630,6 +8368,7 @@ instruct subP_rReg(rRegP dst, rRegI src, immI_0 zero, rFlagsReg cr) instruct negI_rReg(rRegI dst, immI_0 zero, rFlagsReg cr) %{ + predicate(!UseAPX); match(Set dst (SubI zero dst)); effect(KILL cr); flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag); @@ -7641,8 +8380,23 @@ instruct negI_rReg(rRegI dst, immI_0 zero, rFlagsReg cr) ins_pipe(ialu_reg); %} +instruct negI_rReg_ndd(rRegI dst, rRegI src, immI_0 zero, rFlagsReg cr) +%{ + predicate(UseAPX); + match(Set dst (SubI zero src)); + effect(KILL cr); + flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag); + + format %{ "enegl $dst, $src\t# int ndd" %} + ins_encode %{ + __ enegl($dst$$Register, $src$$Register, false); + %} + ins_pipe(ialu_reg); +%} + instruct negI_rReg_2(rRegI dst, rFlagsReg cr) %{ + predicate(!UseAPX); match(Set dst (NegI dst)); effect(KILL cr); flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag); @@ -7654,6 +8408,20 @@ instruct negI_rReg_2(rRegI dst, rFlagsReg cr) ins_pipe(ialu_reg); %} +instruct negI_rReg_2_ndd(rRegI dst, rRegI src, rFlagsReg cr) +%{ + predicate(UseAPX); + match(Set dst (NegI src)); + effect(KILL cr); + flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag); + + format %{ "enegl $dst, $src\t# int ndd" %} + ins_encode %{ + __ enegl($dst$$Register, $src$$Register, false); + %} + ins_pipe(ialu_reg); +%} + instruct negI_mem(memory dst, immI_0 zero, rFlagsReg cr) %{ match(Set dst (StoreI dst (SubI zero (LoadI dst)))); @@ -7669,6 +8437,7 @@ instruct negI_mem(memory dst, immI_0 zero, rFlagsReg cr) instruct negL_rReg(rRegL dst, immL0 zero, rFlagsReg cr) %{ + predicate(!UseAPX); match(Set dst (SubL zero dst)); effect(KILL cr); flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag); @@ -7680,8 +8449,23 @@ instruct negL_rReg(rRegL dst, immL0 zero, rFlagsReg cr) ins_pipe(ialu_reg); %} +instruct negL_rReg_ndd(rRegL dst, rRegL src, immL0 zero, rFlagsReg cr) +%{ + predicate(UseAPX); + match(Set dst (SubL zero src)); + effect(KILL cr); + flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag); + + format %{ "enegq $dst, $src\t# long ndd" %} + ins_encode %{ + __ enegq($dst$$Register, $src$$Register, false); + %} + ins_pipe(ialu_reg); +%} + instruct negL_rReg_2(rRegL dst, rFlagsReg cr) %{ + predicate(!UseAPX); match(Set dst (NegL dst)); effect(KILL cr); flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag); @@ -7693,6 +8477,20 @@ instruct negL_rReg_2(rRegL dst, rFlagsReg cr) ins_pipe(ialu_reg); %} +instruct negL_rReg_2_ndd(rRegL dst, rRegL src, rFlagsReg cr) +%{ + predicate(UseAPX); + match(Set dst (NegL src)); + effect(KILL cr); + flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag); + + format %{ "enegq $dst, $src\t# long ndd" %} + ins_encode %{ + __ enegq($dst$$Register, $src$$Register, false); + %} + ins_pipe(ialu_reg); +%} + instruct negL_mem(memory dst, immL0 zero, rFlagsReg cr) %{ match(Set dst (StoreL dst (SubL zero (LoadL dst)))); @@ -7712,6 +8510,7 @@ instruct negL_mem(memory dst, immL0 zero, rFlagsReg cr) instruct mulI_rReg(rRegI dst, rRegI src, rFlagsReg cr) %{ + predicate(!UseAPX); match(Set dst (MulI dst src)); effect(KILL cr); @@ -7723,8 +8522,23 @@ instruct mulI_rReg(rRegI dst, rRegI src, rFlagsReg cr) ins_pipe(ialu_reg_reg_alu0); %} +instruct mulI_rReg_ndd(rRegI dst, rRegI src1, rRegI src2, rFlagsReg cr) +%{ + predicate(UseAPX); + match(Set dst (MulI src1 src2)); + effect(KILL cr); + + ins_cost(300); + format %{ "eimull $dst, $src1, $src2\t# int ndd" %} + ins_encode %{ + __ eimull($dst$$Register, $src1$$Register, $src2$$Register, false); + %} + ins_pipe(ialu_reg_reg_alu0); +%} + instruct mulI_rReg_imm(rRegI dst, rRegI src, immI imm, rFlagsReg cr) %{ + predicate(!UseAPX); match(Set dst (MulI src imm)); effect(KILL cr); @@ -7736,8 +8550,23 @@ instruct mulI_rReg_imm(rRegI dst, rRegI src, immI imm, rFlagsReg cr) ins_pipe(ialu_reg_reg_alu0); %} +instruct mulI_rReg_rReg_imm_ndd(rRegI dst, rRegI src1, immI src2, rFlagsReg cr) +%{ + predicate(UseAPX); + match(Set dst (MulI src1 src2)); + effect(KILL cr); + + ins_cost(300); + format %{ "eimull $dst, $src1, $src2\t# int ndd" %} + ins_encode %{ + __ eimull($dst$$Register, $src1$$Register, $src2$$constant, false); + %} + ins_pipe(ialu_reg_reg_alu0); +%} + instruct mulI_mem(rRegI dst, memory src, rFlagsReg cr) %{ + predicate(!UseAPX); match(Set dst (MulI dst (LoadI src))); effect(KILL cr); @@ -7749,8 +8578,23 @@ instruct mulI_mem(rRegI dst, memory src, rFlagsReg cr) ins_pipe(ialu_reg_mem_alu0); %} +instruct mulI_rReg_rReg_mem_ndd(rRegI dst, rRegI src1, memory src2, rFlagsReg cr) +%{ + predicate(UseAPX); + match(Set dst (MulI src1 (LoadI src2))); + effect(KILL cr); + + ins_cost(350); + format %{ "eimull $dst, $src1, $src2\t# int ndd" %} + ins_encode %{ + __ eimull($dst$$Register, $src1$$Register, $src2$$Address, false); + %} + ins_pipe(ialu_reg_mem_alu0); +%} + instruct mulI_mem_imm(rRegI dst, memory src, immI imm, rFlagsReg cr) %{ + predicate(!UseAPX); match(Set dst (MulI (LoadI src) imm)); effect(KILL cr); @@ -7762,6 +8606,20 @@ instruct mulI_mem_imm(rRegI dst, memory src, immI imm, rFlagsReg cr) ins_pipe(ialu_reg_mem_alu0); %} +instruct mulI_rReg_mem_imm(rRegI dst, memory src1, immI src2, rFlagsReg cr) +%{ + predicate(UseAPX); + match(Set dst (MulI (LoadI src1) src2)); + effect(KILL cr); + + ins_cost(300); + format %{ "eimull $dst, $src1, $src2\t# int ndd" %} + ins_encode %{ + __ eimull($dst$$Register, $src1$$Address, $src2$$constant, false); + %} + ins_pipe(ialu_reg_mem_alu0); +%} + instruct mulAddS2I_rReg(rRegI dst, rRegI src1, rRegI src2, rRegI src3, rFlagsReg cr) %{ match(Set dst (MulAddS2I (Binary dst src1) (Binary src2 src3))); @@ -7774,6 +8632,7 @@ instruct mulAddS2I_rReg(rRegI dst, rRegI src1, rRegI src2, rRegI src3, rFlagsReg instruct mulL_rReg(rRegL dst, rRegL src, rFlagsReg cr) %{ + predicate(!UseAPX); match(Set dst (MulL dst src)); effect(KILL cr); @@ -7785,8 +8644,23 @@ instruct mulL_rReg(rRegL dst, rRegL src, rFlagsReg cr) ins_pipe(ialu_reg_reg_alu0); %} +instruct mulL_rReg_ndd(rRegL dst, rRegL src1, rRegL src2, rFlagsReg cr) +%{ + predicate(UseAPX); + match(Set dst (MulL src1 src2)); + effect(KILL cr); + + ins_cost(300); + format %{ "eimulq $dst, $src1, $src2\t# long ndd" %} + ins_encode %{ + __ eimulq($dst$$Register, $src1$$Register, $src2$$Register, false); + %} + ins_pipe(ialu_reg_reg_alu0); +%} + instruct mulL_rReg_imm(rRegL dst, rRegL src, immL32 imm, rFlagsReg cr) %{ + predicate(!UseAPX); match(Set dst (MulL src imm)); effect(KILL cr); @@ -7798,8 +8672,23 @@ instruct mulL_rReg_imm(rRegL dst, rRegL src, immL32 imm, rFlagsReg cr) ins_pipe(ialu_reg_reg_alu0); %} +instruct mulL_rReg_rReg_imm_ndd(rRegL dst, rRegL src1, immL32 src2, rFlagsReg cr) +%{ + predicate(UseAPX); + match(Set dst (MulL src1 src2)); + effect(KILL cr); + + ins_cost(300); + format %{ "eimulq $dst, $src1, $src2\t# long ndd" %} + ins_encode %{ + __ eimulq($dst$$Register, $src1$$Register, $src2$$constant, false); + %} + ins_pipe(ialu_reg_reg_alu0); +%} + instruct mulL_mem(rRegL dst, memory src, rFlagsReg cr) %{ + predicate(!UseAPX); match(Set dst (MulL dst (LoadL src))); effect(KILL cr); @@ -7811,8 +8700,23 @@ instruct mulL_mem(rRegL dst, memory src, rFlagsReg cr) ins_pipe(ialu_reg_mem_alu0); %} +instruct mulL_rReg_rReg_mem_ndd(rRegL dst, rRegL src1, memory src2, rFlagsReg cr) +%{ + predicate(UseAPX); + match(Set dst (MulL src1 (LoadL src2))); + effect(KILL cr); + + ins_cost(350); + format %{ "eimulq $dst, $src1, $src2 \t# long" %} + ins_encode %{ + __ eimulq($dst$$Register, $src1$$Register, $src2$$Address, false); + %} + ins_pipe(ialu_reg_mem_alu0); +%} + instruct mulL_mem_imm(rRegL dst, memory src, immL32 imm, rFlagsReg cr) %{ + predicate(!UseAPX); match(Set dst (MulL (LoadL src) imm)); effect(KILL cr); @@ -7824,6 +8728,20 @@ instruct mulL_mem_imm(rRegL dst, memory src, immL32 imm, rFlagsReg cr) ins_pipe(ialu_reg_mem_alu0); %} +instruct mulL_rReg_mem_imm_ndd(rRegL dst, memory src1, immL32 src2, rFlagsReg cr) +%{ + predicate(UseAPX); + match(Set dst (MulL (LoadL src1) src2)); + effect(KILL cr); + + ins_cost(300); + format %{ "eimulq $dst, $src1, $src2\t# long ndd" %} + ins_encode %{ + __ eimulq($dst$$Register, $src1$$Address, $src2$$constant, false); + %} + ins_pipe(ialu_reg_mem_alu0); +%} + instruct mulHiL_rReg(rdx_RegL dst, rRegL src, rax_RegL rax, rFlagsReg cr) %{ match(Set dst (MulHiL src rax)); @@ -8059,6 +8977,35 @@ instruct umodL_rReg(rdx_RegL rdx, rax_RegL rax, no_rax_rdx_RegL div, rFlagsReg c // Shift Left by one, two, three instruct salI_rReg_immI2(rRegI dst, immI2 shift, rFlagsReg cr) %{ + predicate(!UseAPX); + match(Set dst (LShiftI dst shift)); + effect(KILL cr); + + format %{ "sall $dst, $shift" %} + ins_encode %{ + __ sall($dst$$Register, $shift$$constant); + %} + ins_pipe(ialu_reg); +%} + +// Shift Left by one, two, three +instruct salI_rReg_immI2_ndd(rRegI dst, rRegI src, immI2 shift, rFlagsReg cr) +%{ + predicate(UseAPX); + match(Set dst (LShiftI src shift)); + effect(KILL cr); + + format %{ "esall $dst, $src, $shift\t# int(ndd)" %} + ins_encode %{ + __ esall($dst$$Register, $src$$Register, $shift$$constant, false); + %} + ins_pipe(ialu_reg); +%} + +// Shift Left by 8-bit immediate +instruct salI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr) +%{ + predicate(!UseAPX); match(Set dst (LShiftI dst shift)); effect(KILL cr); @@ -8070,14 +9017,28 @@ instruct salI_rReg_immI2(rRegI dst, immI2 shift, rFlagsReg cr) %} // Shift Left by 8-bit immediate -instruct salI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr) +instruct salI_rReg_imm_ndd(rRegI dst, rRegI src, immI8 shift, rFlagsReg cr) %{ - match(Set dst (LShiftI dst shift)); + predicate(UseAPX); + match(Set dst (LShiftI src shift)); effect(KILL cr); - format %{ "sall $dst, $shift" %} + format %{ "esall $dst, $src, $shift\t# int (ndd)" %} ins_encode %{ - __ sall($dst$$Register, $shift$$constant); + __ esall($dst$$Register, $src$$Register, $shift$$constant, false); + %} + ins_pipe(ialu_reg); +%} + +instruct salI_rReg_mem_imm_ndd(rRegI dst, memory src, immI8 shift, rFlagsReg cr) +%{ + predicate(UseAPX); + match(Set dst (LShiftI (LoadI src) shift)); + effect(KILL cr); + + format %{ "esall $dst, $src, $shift\t# int (ndd)" %} + ins_encode %{ + __ esall($dst$$Register, $src$$Address, $shift$$constant, false); %} ins_pipe(ialu_reg); %} @@ -8150,6 +9111,7 @@ instruct salI_mem_rReg(rRegI dst, memory src, rRegI shift) // Arithmetic Shift Right by 8-bit immediate instruct sarI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr) %{ + predicate(!UseAPX); match(Set dst (RShiftI dst shift)); effect(KILL cr); @@ -8160,6 +9122,33 @@ instruct sarI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr) ins_pipe(ialu_mem_imm); %} +// Arithmetic Shift Right by 8-bit immediate +instruct sarI_rReg_imm_ndd(rRegI dst, rRegI src, immI8 shift, rFlagsReg cr) +%{ + predicate(UseAPX); + match(Set dst (RShiftI src shift)); + effect(KILL cr); + + format %{ "esarl $dst, $src, $shift\t# int (ndd)" %} + ins_encode %{ + __ esarl($dst$$Register, $src$$Register, $shift$$constant, false); + %} + ins_pipe(ialu_mem_imm); +%} + +instruct sarI_rReg_mem_imm_ndd(rRegI dst, memory src, immI8 shift, rFlagsReg cr) +%{ + predicate(UseAPX); + match(Set dst (RShiftI (LoadI src) shift)); + effect(KILL cr); + + format %{ "esarl $dst, $src, $shift\t# int (ndd)" %} + ins_encode %{ + __ esarl($dst$$Register, $src$$Address, $shift$$constant, false); + %} + ins_pipe(ialu_mem_imm); +%} + // Arithmetic Shift Right by 8-bit immediate instruct sarI_mem_imm(memory dst, immI8 shift, rFlagsReg cr) %{ @@ -8228,6 +9217,7 @@ instruct sarI_mem_rReg(rRegI dst, memory src, rRegI shift) // Logical Shift Right by 8-bit immediate instruct shrI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr) %{ + predicate(!UseAPX); match(Set dst (URShiftI dst shift)); effect(KILL cr); @@ -8238,6 +9228,33 @@ instruct shrI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr) ins_pipe(ialu_reg); %} +// Logical Shift Right by 8-bit immediate +instruct shrI_rReg_imm_ndd(rRegI dst, rRegI src, immI8 shift, rFlagsReg cr) +%{ + predicate(UseAPX); + match(Set dst (URShiftI src shift)); + effect(KILL cr); + + format %{ "eshrl $dst, $src, $shift\t # int (ndd)" %} + ins_encode %{ + __ eshrl($dst$$Register, $src$$Register, $shift$$constant, false); + %} + ins_pipe(ialu_reg); +%} + +instruct shrI_rReg_mem_imm_ndd(rRegI dst, memory src, immI8 shift, rFlagsReg cr) +%{ + predicate(UseAPX); + match(Set dst (URShiftI (LoadI src) shift)); + effect(KILL cr); + + format %{ "eshrl $dst, $src, $shift\t # int (ndd)" %} + ins_encode %{ + __ eshrl($dst$$Register, $src$$Address, $shift$$constant, false); + %} + ins_pipe(ialu_reg); +%} + // Logical Shift Right by 8-bit immediate instruct shrI_mem_imm(memory dst, immI8 shift, rFlagsReg cr) %{ @@ -8307,6 +9324,35 @@ instruct shrI_mem_rReg(rRegI dst, memory src, rRegI shift) // Shift Left by one, two, three instruct salL_rReg_immI2(rRegL dst, immI2 shift, rFlagsReg cr) %{ + predicate(!UseAPX); + match(Set dst (LShiftL dst shift)); + effect(KILL cr); + + format %{ "salq $dst, $shift" %} + ins_encode %{ + __ salq($dst$$Register, $shift$$constant); + %} + ins_pipe(ialu_reg); +%} + +// Shift Left by one, two, three +instruct salL_rReg_immI2_ndd(rRegL dst, rRegL src, immI2 shift, rFlagsReg cr) +%{ + predicate(UseAPX); + match(Set dst (LShiftL src shift)); + effect(KILL cr); + + format %{ "esalq $dst, $src, $shift\t# long (ndd)" %} + ins_encode %{ + __ esalq($dst$$Register, $src$$Register, $shift$$constant, false); + %} + ins_pipe(ialu_reg); +%} + +// Shift Left by 8-bit immediate +instruct salL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr) +%{ + predicate(!UseAPX); match(Set dst (LShiftL dst shift)); effect(KILL cr); @@ -8318,14 +9364,28 @@ instruct salL_rReg_immI2(rRegL dst, immI2 shift, rFlagsReg cr) %} // Shift Left by 8-bit immediate -instruct salL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr) +instruct salL_rReg_imm_ndd(rRegL dst, rRegL src, immI8 shift, rFlagsReg cr) %{ - match(Set dst (LShiftL dst shift)); + predicate(UseAPX); + match(Set dst (LShiftL src shift)); effect(KILL cr); - format %{ "salq $dst, $shift" %} + format %{ "esalq $dst, $src, $shift\t# long (ndd)" %} ins_encode %{ - __ salq($dst$$Register, $shift$$constant); + __ esalq($dst$$Register, $src$$Register, $shift$$constant, false); + %} + ins_pipe(ialu_reg); +%} + +instruct salL_rReg_mem_imm_ndd(rRegL dst, memory src, immI8 shift, rFlagsReg cr) +%{ + predicate(UseAPX); + match(Set dst (LShiftL (LoadL src) shift)); + effect(KILL cr); + + format %{ "esalq $dst, $src, $shift\t# long (ndd)" %} + ins_encode %{ + __ esalq($dst$$Register, $src$$Address, $shift$$constant, false); %} ins_pipe(ialu_reg); %} @@ -8398,6 +9458,7 @@ instruct salL_mem_rReg(rRegL dst, memory src, rRegI shift) // Arithmetic Shift Right by 8-bit immediate instruct sarL_rReg_imm(rRegL dst, immI shift, rFlagsReg cr) %{ + predicate(!UseAPX); match(Set dst (RShiftL dst shift)); effect(KILL cr); @@ -8408,6 +9469,33 @@ instruct sarL_rReg_imm(rRegL dst, immI shift, rFlagsReg cr) ins_pipe(ialu_mem_imm); %} +// Arithmetic Shift Right by 8-bit immediate +instruct sarL_rReg_imm_ndd(rRegL dst, rRegL src, immI shift, rFlagsReg cr) +%{ + predicate(UseAPX); + match(Set dst (RShiftL src shift)); + effect(KILL cr); + + format %{ "esarq $dst, $src, $shift\t# long (ndd)" %} + ins_encode %{ + __ esarq($dst$$Register, $src$$Register, (unsigned char)($shift$$constant & 0x3F), false); + %} + ins_pipe(ialu_mem_imm); +%} + +instruct sarL_rReg_mem_imm_ndd(rRegL dst, memory src, immI shift, rFlagsReg cr) +%{ + predicate(UseAPX); + match(Set dst (RShiftL (LoadL src) shift)); + effect(KILL cr); + + format %{ "esarq $dst, $src, $shift\t# long (ndd)" %} + ins_encode %{ + __ esarq($dst$$Register, $src$$Address, (unsigned char)($shift$$constant & 0x3F), false); + %} + ins_pipe(ialu_mem_imm); +%} + // Arithmetic Shift Right by 8-bit immediate instruct sarL_mem_imm(memory dst, immI shift, rFlagsReg cr) %{ @@ -8476,6 +9564,7 @@ instruct sarL_mem_rReg(rRegL dst, memory src, rRegI shift) // Logical Shift Right by 8-bit immediate instruct shrL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr) %{ + predicate(!UseAPX); match(Set dst (URShiftL dst shift)); effect(KILL cr); @@ -8486,6 +9575,33 @@ instruct shrL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr) ins_pipe(ialu_reg); %} +// Logical Shift Right by 8-bit immediate +instruct shrL_rReg_imm_ndd(rRegL dst, rRegL src, immI8 shift, rFlagsReg cr) +%{ + predicate(UseAPX); + match(Set dst (URShiftL src shift)); + effect(KILL cr); + + format %{ "eshrq $dst, $src, $shift\t# long (ndd)" %} + ins_encode %{ + __ eshrq($dst$$Register, $src$$Register, $shift$$constant, false); + %} + ins_pipe(ialu_reg); +%} + +instruct shrL_rReg_mem_imm_ndd(rRegL dst, memory src, immI8 shift, rFlagsReg cr) +%{ + predicate(UseAPX); + match(Set dst (URShiftL (LoadL src) shift)); + effect(KILL cr); + + format %{ "eshrq $dst, $src, $shift\t# long (ndd)" %} + ins_encode %{ + __ eshrq($dst$$Register, $src$$Address, $shift$$constant, false); + %} + ins_pipe(ialu_reg); +%} + // Logical Shift Right by 8-bit immediate instruct shrL_mem_imm(memory dst, immI8 shift, rFlagsReg cr) %{ @@ -8594,7 +9710,7 @@ instruct rolI_immI8_legacy(rRegI dst, immI8 shift, rFlagsReg cr) instruct rolI_immI8(rRegI dst, rRegI src, immI8 shift) %{ - predicate(VM_Version::supports_bmi2() && n->bottom_type()->basic_type() == T_INT); + predicate(!UseAPX && VM_Version::supports_bmi2() && n->bottom_type()->basic_type() == T_INT); match(Set dst (RotateLeft src shift)); format %{ "rolxl $dst, $src, $shift" %} ins_encode %{ @@ -8620,7 +9736,7 @@ instruct rolI_mem_immI8(rRegI dst, memory src, immI8 shift) // Rotate Left by variable instruct rolI_rReg_Var(rRegI dst, rcx_RegI shift, rFlagsReg cr) %{ - predicate(n->bottom_type()->basic_type() == T_INT); + predicate(!UseAPX && n->bottom_type()->basic_type() == T_INT); match(Set dst (RotateLeft dst shift)); effect(KILL cr); format %{ "roll $dst, $shift" %} @@ -8630,6 +9746,20 @@ instruct rolI_rReg_Var(rRegI dst, rcx_RegI shift, rFlagsReg cr) ins_pipe(ialu_reg_reg); %} +// Rotate Left by variable +instruct rolI_rReg_Var_ndd(rRegI dst, rRegI src, rcx_RegI shift, rFlagsReg cr) +%{ + predicate(UseAPX && n->bottom_type()->basic_type() == T_INT); + match(Set dst (RotateLeft src shift)); + effect(KILL cr); + + format %{ "eroll $dst, $src, $shift\t# rotate left (int ndd)" %} + ins_encode %{ + __ eroll($dst$$Register, $src$$Register, false); + %} + ins_pipe(ialu_reg_reg); +%} + // Rotate Right by constant. instruct rorI_immI8_legacy(rRegI dst, immI8 shift, rFlagsReg cr) %{ @@ -8646,7 +9776,7 @@ instruct rorI_immI8_legacy(rRegI dst, immI8 shift, rFlagsReg cr) // Rotate Right by constant. instruct rorI_immI8(rRegI dst, rRegI src, immI8 shift) %{ - predicate(VM_Version::supports_bmi2() && n->bottom_type()->basic_type() == T_INT); + predicate(!UseAPX && VM_Version::supports_bmi2() && n->bottom_type()->basic_type() == T_INT); match(Set dst (RotateRight src shift)); format %{ "rorxl $dst, $src, $shift" %} ins_encode %{ @@ -8670,7 +9800,7 @@ instruct rorI_mem_immI8(rRegI dst, memory src, immI8 shift) // Rotate Right by variable instruct rorI_rReg_Var(rRegI dst, rcx_RegI shift, rFlagsReg cr) %{ - predicate(n->bottom_type()->basic_type() == T_INT); + predicate(!UseAPX && n->bottom_type()->basic_type() == T_INT); match(Set dst (RotateRight dst shift)); effect(KILL cr); format %{ "rorl $dst, $shift" %} @@ -8680,6 +9810,20 @@ instruct rorI_rReg_Var(rRegI dst, rcx_RegI shift, rFlagsReg cr) ins_pipe(ialu_reg_reg); %} +// Rotate Right by variable +instruct rorI_rReg_Var_ndd(rRegI dst, rRegI src, rcx_RegI shift, rFlagsReg cr) +%{ + predicate(UseAPX && n->bottom_type()->basic_type() == T_INT); + match(Set dst (RotateRight src shift)); + effect(KILL cr); + + format %{ "erorl $dst, $src, $shift\t# rotate right(int ndd)" %} + ins_encode %{ + __ erorl($dst$$Register, $src$$Register, false); + %} + ins_pipe(ialu_reg_reg); +%} + // Rotate Left by constant. instruct rolL_immI8_legacy(rRegL dst, immI8 shift, rFlagsReg cr) %{ @@ -8695,7 +9839,7 @@ instruct rolL_immI8_legacy(rRegL dst, immI8 shift, rFlagsReg cr) instruct rolL_immI8(rRegL dst, rRegL src, immI8 shift) %{ - predicate(VM_Version::supports_bmi2() && n->bottom_type()->basic_type() == T_LONG); + predicate(!UseAPX && VM_Version::supports_bmi2() && n->bottom_type()->basic_type() == T_LONG); match(Set dst (RotateLeft src shift)); format %{ "rolxq $dst, $src, $shift" %} ins_encode %{ @@ -8721,7 +9865,7 @@ instruct rolL_mem_immI8(rRegL dst, memory src, immI8 shift) // Rotate Left by variable instruct rolL_rReg_Var(rRegL dst, rcx_RegI shift, rFlagsReg cr) %{ - predicate(n->bottom_type()->basic_type() == T_LONG); + predicate(!UseAPX && n->bottom_type()->basic_type() == T_LONG); match(Set dst (RotateLeft dst shift)); effect(KILL cr); format %{ "rolq $dst, $shift" %} @@ -8731,6 +9875,20 @@ instruct rolL_rReg_Var(rRegL dst, rcx_RegI shift, rFlagsReg cr) ins_pipe(ialu_reg_reg); %} +// Rotate Left by variable +instruct rolL_rReg_Var_ndd(rRegL dst, rRegL src, rcx_RegI shift, rFlagsReg cr) +%{ + predicate(UseAPX && n->bottom_type()->basic_type() == T_LONG); + match(Set dst (RotateLeft src shift)); + effect(KILL cr); + + format %{ "erolq $dst, $src, $shift\t# rotate left(long ndd)" %} + ins_encode %{ + __ erolq($dst$$Register, $src$$Register, false); + %} + ins_pipe(ialu_reg_reg); +%} + // Rotate Right by constant. instruct rorL_immI8_legacy(rRegL dst, immI8 shift, rFlagsReg cr) %{ @@ -8771,7 +9929,7 @@ instruct rorL_mem_immI8(rRegL dst, memory src, immI8 shift) // Rotate Right by variable instruct rorL_rReg_Var(rRegL dst, rcx_RegI shift, rFlagsReg cr) %{ - predicate(n->bottom_type()->basic_type() == T_LONG); + predicate(!UseAPX && n->bottom_type()->basic_type() == T_LONG); match(Set dst (RotateRight dst shift)); effect(KILL cr); format %{ "rorq $dst, $shift" %} @@ -8781,6 +9939,20 @@ instruct rorL_rReg_Var(rRegL dst, rcx_RegI shift, rFlagsReg cr) ins_pipe(ialu_reg_reg); %} +// Rotate Right by variable +instruct rorL_rReg_Var_ndd(rRegL dst, rRegL src, rcx_RegI shift, rFlagsReg cr) +%{ + predicate(UseAPX && n->bottom_type()->basic_type() == T_LONG); + match(Set dst (RotateRight src shift)); + effect(KILL cr); + + format %{ "erorq $dst, $src, $shift\t# rotate right(long ndd)" %} + ins_encode %{ + __ erorq($dst$$Register, $src$$Register, false); + %} + ins_pipe(ialu_reg_reg); +%} + //----------------------------- CompressBits/ExpandBits ------------------------ instruct compressBitsL_reg(rRegL dst, rRegL src, rRegL mask) %{ @@ -8832,6 +10004,7 @@ instruct expandBitsL_mem(rRegL dst, rRegL src, memory mask) %{ // And Register with Register instruct andI_rReg(rRegI dst, rRegI src, rFlagsReg cr) %{ + predicate(!UseAPX); match(Set dst (AndI dst src)); effect(KILL cr); flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag); @@ -8843,6 +10016,22 @@ instruct andI_rReg(rRegI dst, rRegI src, rFlagsReg cr) ins_pipe(ialu_reg_reg); %} +// And Register with Register using New Data Destination (NDD) +instruct andI_rReg_ndd(rRegI dst, rRegI src1, rRegI src2, rFlagsReg cr) +%{ + predicate(UseAPX); + match(Set dst (AndI src1 src2)); + effect(KILL cr); + flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag); + + format %{ "eandl $dst, $src1, $src2\t# int ndd" %} + ins_encode %{ + __ eandl($dst$$Register, $src1$$Register, $src2$$Register, false); + + %} + ins_pipe(ialu_reg_reg); +%} + // And Register with Immediate 255 instruct andI_rReg_imm255(rRegI dst, rRegI src, immI_255 mask) %{ @@ -8909,6 +10098,7 @@ instruct convI2LAndI_reg_immIbitmask(rRegL dst, rRegI src, immI_Pow2M1 mask, rR // And Register with Immediate instruct andI_rReg_imm(rRegI dst, immI src, rFlagsReg cr) %{ + predicate(!UseAPX); match(Set dst (AndI dst src)); effect(KILL cr); flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag); @@ -8920,9 +10110,38 @@ instruct andI_rReg_imm(rRegI dst, immI src, rFlagsReg cr) ins_pipe(ialu_reg); %} +instruct andI_rReg_rReg_imm_ndd(rRegI dst, rRegI src1, immI src2, rFlagsReg cr) +%{ + predicate(UseAPX); + match(Set dst (AndI src1 src2)); + effect(KILL cr); + flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag); + + format %{ "eandl $dst, $src1, $src2\t# int ndd" %} + ins_encode %{ + __ eandl($dst$$Register, $src1$$Register, $src2$$constant, false); + %} + ins_pipe(ialu_reg); +%} + +instruct andI_rReg_mem_imm_ndd(rRegI dst, memory src1, immI src2, rFlagsReg cr) +%{ + predicate(UseAPX); + match(Set dst (AndI (LoadI src1) src2)); + effect(KILL cr); + flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag); + + format %{ "eandl $dst, $src1, $src2\t# int ndd" %} + ins_encode %{ + __ eandl($dst$$Register, $src1$$Address, $src2$$constant, false); + %} + ins_pipe(ialu_reg); +%} + // And Register with Memory instruct andI_rReg_mem(rRegI dst, memory src, rFlagsReg cr) %{ + predicate(!UseAPX); match(Set dst (AndI dst (LoadI src))); effect(KILL cr); flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag); @@ -8935,6 +10154,21 @@ instruct andI_rReg_mem(rRegI dst, memory src, rFlagsReg cr) ins_pipe(ialu_reg_mem); %} +instruct andI_rReg_rReg_mem_ndd(rRegI dst, rRegI src1, memory src2, rFlagsReg cr) +%{ + predicate(UseAPX); + match(Set dst (AndI src1 (LoadI src2))); + effect(KILL cr); + flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag); + + ins_cost(150); + format %{ "eandl $dst, $src1, $src2\t# int ndd" %} + ins_encode %{ + __ eandl($dst$$Register, $src1$$Register, $src2$$Address, false); + %} + ins_pipe(ialu_reg_mem); +%} + // And Memory with Register instruct andB_mem_rReg(memory dst, rRegI src, rFlagsReg cr) %{ @@ -9107,6 +10341,7 @@ instruct blsrI_rReg_mem(rRegI dst, memory src, immI_M1 minus_1, rFlagsReg cr) // Or Register with Register instruct orI_rReg(rRegI dst, rRegI src, rFlagsReg cr) %{ + predicate(!UseAPX); match(Set dst (OrI dst src)); effect(KILL cr); flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag); @@ -9118,9 +10353,25 @@ instruct orI_rReg(rRegI dst, rRegI src, rFlagsReg cr) ins_pipe(ialu_reg_reg); %} +// Or Register with Register using New Data Destination (NDD) +instruct orI_rReg_ndd(rRegI dst, rRegI src1, rRegI src2, rFlagsReg cr) +%{ + predicate(UseAPX); + match(Set dst (OrI src1 src2)); + effect(KILL cr); + flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag); + + format %{ "eorl $dst, $src1, $src2\t# int ndd" %} + ins_encode %{ + __ eorl($dst$$Register, $src1$$Register, $src2$$Register, false); + %} + ins_pipe(ialu_reg_reg); +%} + // Or Register with Immediate instruct orI_rReg_imm(rRegI dst, immI src, rFlagsReg cr) %{ + predicate(!UseAPX); match(Set dst (OrI dst src)); effect(KILL cr); flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag); @@ -9132,9 +10383,52 @@ instruct orI_rReg_imm(rRegI dst, immI src, rFlagsReg cr) ins_pipe(ialu_reg); %} +instruct orI_rReg_rReg_imm_ndd(rRegI dst, rRegI src1, immI src2, rFlagsReg cr) +%{ + predicate(UseAPX); + match(Set dst (OrI src1 src2)); + effect(KILL cr); + flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag); + + format %{ "eorl $dst, $src1, $src2\t# int ndd" %} + ins_encode %{ + __ eorl($dst$$Register, $src1$$Register, $src2$$constant, false); + %} + ins_pipe(ialu_reg); +%} + +instruct orI_rReg_imm_rReg_ndd(rRegI dst, immI src1, rRegI src2, rFlagsReg cr) +%{ + predicate(UseAPX); + match(Set dst (OrI src1 src2)); + effect(KILL cr); + flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag); + + format %{ "eorl $dst, $src2, $src1\t# int ndd" %} + ins_encode %{ + __ eorl($dst$$Register, $src2$$Register, $src1$$constant, false); + %} + ins_pipe(ialu_reg); +%} + +instruct orI_rReg_mem_imm_ndd(rRegI dst, memory src1, immI src2, rFlagsReg cr) +%{ + predicate(UseAPX); + match(Set dst (OrI (LoadI src1) src2)); + effect(KILL cr); + flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag); + + format %{ "eorl $dst, $src1, $src2\t# int ndd" %} + ins_encode %{ + __ eorl($dst$$Register, $src1$$Address, $src2$$constant, false); + %} + ins_pipe(ialu_reg); +%} + // Or Register with Memory instruct orI_rReg_mem(rRegI dst, memory src, rFlagsReg cr) %{ + predicate(!UseAPX); match(Set dst (OrI dst (LoadI src))); effect(KILL cr); flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag); @@ -9147,6 +10441,21 @@ instruct orI_rReg_mem(rRegI dst, memory src, rFlagsReg cr) ins_pipe(ialu_reg_mem); %} +instruct orI_rReg_rReg_mem_ndd(rRegI dst, rRegI src1, memory src2, rFlagsReg cr) +%{ + predicate(UseAPX); + match(Set dst (OrI src1 (LoadI src2))); + effect(KILL cr); + flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag); + + ins_cost(150); + format %{ "eorl $dst, $src1, $src2\t# int ndd" %} + ins_encode %{ + __ eorl($dst$$Register, $src1$$Register, $src2$$Address, false); + %} + ins_pipe(ialu_reg_mem); +%} + // Or Memory with Register instruct orB_mem_rReg(memory dst, rRegI src, rFlagsReg cr) %{ @@ -9195,6 +10504,7 @@ instruct orI_mem_imm(memory dst, immI src, rFlagsReg cr) // Xor Register with Register instruct xorI_rReg(rRegI dst, rRegI src, rFlagsReg cr) %{ + predicate(!UseAPX); match(Set dst (XorI dst src)); effect(KILL cr); flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag); @@ -9206,20 +10516,50 @@ instruct xorI_rReg(rRegI dst, rRegI src, rFlagsReg cr) ins_pipe(ialu_reg_reg); %} +// Xor Register with Register using New Data Destination (NDD) +instruct xorI_rReg_ndd(rRegI dst, rRegI src1, rRegI src2, rFlagsReg cr) +%{ + predicate(UseAPX); + match(Set dst (XorI src1 src2)); + effect(KILL cr); + flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag); + + format %{ "exorl $dst, $src1, $src2\t# int ndd" %} + ins_encode %{ + __ exorl($dst$$Register, $src1$$Register, $src2$$Register, false); + %} + ins_pipe(ialu_reg_reg); +%} + // Xor Register with Immediate -1 -instruct xorI_rReg_im1(rRegI dst, immI_M1 imm) %{ +instruct xorI_rReg_im1(rRegI dst, immI_M1 imm) +%{ + predicate(!UseAPX); match(Set dst (XorI dst imm)); - format %{ "not $dst" %} + format %{ "notl $dst" %} ins_encode %{ __ notl($dst$$Register); %} ins_pipe(ialu_reg); %} +instruct xorI_rReg_im1_ndd(rRegI dst, rRegI src, immI_M1 imm) +%{ + match(Set dst (XorI src imm)); + predicate(UseAPX); + + format %{ "enotl $dst, $src" %} + ins_encode %{ + __ enotl($dst$$Register, $src$$Register); + %} + ins_pipe(ialu_reg); +%} + // Xor Register with Immediate instruct xorI_rReg_imm(rRegI dst, immI src, rFlagsReg cr) %{ + predicate(!UseAPX); match(Set dst (XorI dst src)); effect(KILL cr); flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag); @@ -9231,9 +10571,39 @@ instruct xorI_rReg_imm(rRegI dst, immI src, rFlagsReg cr) ins_pipe(ialu_reg); %} +instruct xorI_rReg_rReg_imm_ndd(rRegI dst, rRegI src1, immI src2, rFlagsReg cr) +%{ + predicate(UseAPX); + match(Set dst (XorI src1 src2)); + effect(KILL cr); + flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag); + + format %{ "exorl $dst, $src1, $src2\t# int ndd" %} + ins_encode %{ + __ exorl($dst$$Register, $src1$$Register, $src2$$constant, false); + %} + ins_pipe(ialu_reg); +%} + +// Xor Memory with Immediate +instruct xorI_rReg_mem_imm_ndd(rRegI dst, memory src1, immI src2, rFlagsReg cr) +%{ + predicate(UseAPX); + match(Set dst (XorI (LoadI src1) src2)); + effect(KILL cr); + flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag); + + format %{ "exorl $dst, $src1, $src2\t# int ndd" %} + ins_encode %{ + __ exorl($dst$$Register, $src1$$Address, $src2$$constant, false); + %} + ins_pipe(ialu_reg); +%} + // Xor Register with Memory instruct xorI_rReg_mem(rRegI dst, memory src, rFlagsReg cr) %{ + predicate(!UseAPX); match(Set dst (XorI dst (LoadI src))); effect(KILL cr); flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag); @@ -9246,6 +10616,36 @@ instruct xorI_rReg_mem(rRegI dst, memory src, rFlagsReg cr) ins_pipe(ialu_reg_mem); %} +instruct xorI_rReg_rReg_mem_ndd(rRegI dst, rRegI src1, memory src2, rFlagsReg cr) +%{ + predicate(UseAPX); + match(Set dst (XorI src1 (LoadI src2))); + effect(KILL cr); + flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag); + + ins_cost(150); + format %{ "exorl $dst, $src1, $src2\t# int ndd" %} + ins_encode %{ + __ exorl($dst$$Register, $src1$$Register, $src2$$Address, false); + %} + ins_pipe(ialu_reg_mem); +%} + +instruct xorI_rReg_mem_rReg_ndd(rRegI dst, memory src1, rRegI src2, rFlagsReg cr) +%{ + predicate(UseAPX); + match(Set dst (XorI (LoadI src1) src2)); + effect(KILL cr); + flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag); + + ins_cost(150); + format %{ "exorl $dst, $src1, $src2\t# int ndd" %} + ins_encode %{ + __ exorl($dst$$Register, $src1$$Address, $src2$$Register, false); + %} + ins_pipe(ialu_reg_mem); +%} + // Xor Memory with Register instruct xorB_mem_rReg(memory dst, rRegI src, rFlagsReg cr) %{ @@ -9297,6 +10697,7 @@ instruct xorI_mem_imm(memory dst, immI src, rFlagsReg cr) // And Register with Register instruct andL_rReg(rRegL dst, rRegL src, rFlagsReg cr) %{ + predicate(!UseAPX); match(Set dst (AndL dst src)); effect(KILL cr); flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag); @@ -9308,6 +10709,22 @@ instruct andL_rReg(rRegL dst, rRegL src, rFlagsReg cr) ins_pipe(ialu_reg_reg); %} +// And Register with Register using New Data Destination (NDD) +instruct andL_rReg_ndd(rRegL dst, rRegL src1, rRegL src2, rFlagsReg cr) +%{ + predicate(UseAPX); + match(Set dst (AndL src1 src2)); + effect(KILL cr); + flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag); + + format %{ "eandq $dst, $src1, $src2\t# long ndd" %} + ins_encode %{ + __ eandq($dst$$Register, $src1$$Register, $src2$$Register, false); + + %} + ins_pipe(ialu_reg_reg); +%} + // And Register with Immediate 255 instruct andL_rReg_imm255(rRegL dst, rRegL src, immL_255 mask) %{ @@ -9337,6 +10754,7 @@ instruct andL_rReg_imm65535(rRegL dst, rRegL src, immL_65535 mask) // And Register with Immediate instruct andL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr) %{ + predicate(!UseAPX); match(Set dst (AndL dst src)); effect(KILL cr); flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag); @@ -9348,9 +10766,38 @@ instruct andL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr) ins_pipe(ialu_reg); %} +instruct andL_rReg_rReg_imm_ndd(rRegL dst, rRegL src1, immL32 src2, rFlagsReg cr) +%{ + predicate(UseAPX); + match(Set dst (AndL src1 src2)); + effect(KILL cr); + flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag); + + format %{ "eandq $dst, $src1, $src2\t# long ndd" %} + ins_encode %{ + __ eandq($dst$$Register, $src1$$Register, $src2$$constant, false); + %} + ins_pipe(ialu_reg); +%} + +instruct andL_rReg_mem_imm_ndd(rRegL dst, memory src1, immL32 src2, rFlagsReg cr) +%{ + predicate(UseAPX); + match(Set dst (AndL (LoadL src1) src2)); + effect(KILL cr); + flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag); + + format %{ "eandq $dst, $src1, $src2\t# long ndd" %} + ins_encode %{ + __ eandq($dst$$Register, $src1$$Address, $src2$$constant, false); + %} + ins_pipe(ialu_reg); +%} + // And Register with Memory instruct andL_rReg_mem(rRegL dst, memory src, rFlagsReg cr) %{ + predicate(!UseAPX); match(Set dst (AndL dst (LoadL src))); effect(KILL cr); flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag); @@ -9363,6 +10810,36 @@ instruct andL_rReg_mem(rRegL dst, memory src, rFlagsReg cr) ins_pipe(ialu_reg_mem); %} +instruct andL_rReg_rReg_mem_ndd(rRegL dst, rRegL src1, memory src2, rFlagsReg cr) +%{ + predicate(UseAPX); + match(Set dst (AndL src1 (LoadL src2))); + effect(KILL cr); + flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag); + + ins_cost(150); + format %{ "eandq $dst, $src1, $src2\t# long ndd" %} + ins_encode %{ + __ eandq($dst$$Register, $src1$$Register, $src2$$Address, false); + %} + ins_pipe(ialu_reg_mem); +%} + +instruct andL_rReg_mem_rReg_ndd(rRegL dst, memory src1, rRegL src2, rFlagsReg cr) +%{ + predicate(UseAPX); + match(Set dst (AndL (LoadL src1) src2)); + effect(KILL cr); + flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag); + + ins_cost(150); + format %{ "eandq $dst, $src1, $src2\t# long ndd" %} + ins_encode %{ + __ eandq($dst$$Register, $src1$$Address, $src2$$Register, false); + %} + ins_pipe(ialu_reg_mem); +%} + // And Memory with Register instruct andL_mem_rReg(memory dst, rRegL src, rFlagsReg cr) %{ @@ -9538,6 +11015,7 @@ instruct blsrL_rReg_mem(rRegL dst, memory src, immL_M1 minus_1, rFlagsReg cr) // Or Register with Register instruct orL_rReg(rRegL dst, rRegL src, rFlagsReg cr) %{ + predicate(!UseAPX); match(Set dst (OrL dst src)); effect(KILL cr); flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag); @@ -9549,6 +11027,22 @@ instruct orL_rReg(rRegL dst, rRegL src, rFlagsReg cr) ins_pipe(ialu_reg_reg); %} +// Or Register with Register using New Data Destination (NDD) +instruct orL_rReg_ndd(rRegL dst, rRegL src1, rRegL src2, rFlagsReg cr) +%{ + predicate(UseAPX); + match(Set dst (OrL src1 src2)); + effect(KILL cr); + flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag); + + format %{ "eorq $dst, $src1, $src2\t# long ndd" %} + ins_encode %{ + __ eorq($dst$$Register, $src1$$Register, $src2$$Register, false); + + %} + ins_pipe(ialu_reg_reg); +%} + // Use any_RegP to match R15 (TLS register) without spilling. instruct orL_rReg_castP2X(rRegL dst, any_RegP src, rFlagsReg cr) %{ match(Set dst (OrL dst (CastP2X src))); @@ -9562,10 +11056,22 @@ instruct orL_rReg_castP2X(rRegL dst, any_RegP src, rFlagsReg cr) %{ ins_pipe(ialu_reg_reg); %} +instruct orL_rReg_castP2X_ndd(rRegL dst, any_RegP src1, any_RegP src2, rFlagsReg cr) %{ + match(Set dst (OrL src1 (CastP2X src2))); + effect(KILL cr); + flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag); + + format %{ "eorq $dst, $src1, $src2\t# long ndd" %} + ins_encode %{ + __ eorq($dst$$Register, $src1$$Register, $src2$$Register, false); + %} + ins_pipe(ialu_reg_reg); +%} // Or Register with Immediate instruct orL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr) %{ + predicate(!UseAPX); match(Set dst (OrL dst src)); effect(KILL cr); flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag); @@ -9577,9 +11083,53 @@ instruct orL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr) ins_pipe(ialu_reg); %} +instruct orL_rReg_rReg_imm_ndd(rRegL dst, rRegL src1, immL32 src2, rFlagsReg cr) +%{ + predicate(UseAPX); + match(Set dst (OrL src1 src2)); + effect(KILL cr); + flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag); + + format %{ "eorq $dst, $src1, $src2\t# long ndd" %} + ins_encode %{ + __ eorq($dst$$Register, $src1$$Register, $src2$$constant, false); + %} + ins_pipe(ialu_reg); +%} + +instruct orL_rReg_imm_rReg_ndd(rRegL dst, immL32 src1, rRegL src2, rFlagsReg cr) +%{ + predicate(UseAPX); + match(Set dst (OrL src1 src2)); + effect(KILL cr); + flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag); + + format %{ "eorq $dst, $src2, $src1\t# long ndd" %} + ins_encode %{ + __ eorq($dst$$Register, $src2$$Register, $src1$$constant, false); + %} + ins_pipe(ialu_reg); +%} + +// Or Memory with Immediate +instruct orL_rReg_mem_imm_ndd(rRegL dst, memory src1, immL32 src2, rFlagsReg cr) +%{ + predicate(UseAPX); + match(Set dst (OrL (LoadL src1) src2)); + effect(KILL cr); + flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag); + + format %{ "eorq $dst, $src1, $src2\t# long ndd" %} + ins_encode %{ + __ eorq($dst$$Register, $src1$$Address, $src2$$constant, false); + %} + ins_pipe(ialu_reg); +%} + // Or Register with Memory instruct orL_rReg_mem(rRegL dst, memory src, rFlagsReg cr) %{ + predicate(!UseAPX); match(Set dst (OrL dst (LoadL src))); effect(KILL cr); flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag); @@ -9592,6 +11142,21 @@ instruct orL_rReg_mem(rRegL dst, memory src, rFlagsReg cr) ins_pipe(ialu_reg_mem); %} +instruct orL_rReg_rReg_mem_ndd(rRegL dst, rRegL src1, memory src2, rFlagsReg cr) +%{ + predicate(UseAPX); + match(Set dst (OrL src1 (LoadL src2))); + effect(KILL cr); + flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag); + + ins_cost(150); + format %{ "eorq $dst, $src1, $src2\t# long ndd" %} + ins_encode %{ + __ eorq($dst$$Register, $src1$$Register, $src2$$Address, false); + %} + ins_pipe(ialu_reg_mem); +%} + // Or Memory with Register instruct orL_mem_rReg(memory dst, rRegL src, rFlagsReg cr) %{ @@ -9643,6 +11208,7 @@ instruct btsL_mem_imm(memory dst, immL_Pow2 con, rFlagsReg cr) // Xor Register with Register instruct xorL_rReg(rRegL dst, rRegL src, rFlagsReg cr) %{ + predicate(!UseAPX); match(Set dst (XorL dst src)); effect(KILL cr); flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag); @@ -9654,8 +11220,25 @@ instruct xorL_rReg(rRegL dst, rRegL src, rFlagsReg cr) ins_pipe(ialu_reg_reg); %} +// Xor Register with Register using New Data Destination (NDD) +instruct xorL_rReg_ndd(rRegL dst, rRegL src1, rRegL src2, rFlagsReg cr) +%{ + predicate(UseAPX); + match(Set dst (XorL src1 src2)); + effect(KILL cr); + flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag); + + format %{ "exorq $dst, $src1, $src2\t# long ndd" %} + ins_encode %{ + __ exorq($dst$$Register, $src1$$Register, $src2$$Register, false); + %} + ins_pipe(ialu_reg_reg); +%} + // Xor Register with Immediate -1 -instruct xorL_rReg_im1(rRegL dst, immL_M1 imm) %{ +instruct xorL_rReg_im1(rRegL dst, immL_M1 imm) +%{ + predicate(!UseAPX); match(Set dst (XorL dst imm)); format %{ "notq $dst" %} @@ -9665,9 +11248,22 @@ instruct xorL_rReg_im1(rRegL dst, immL_M1 imm) %{ ins_pipe(ialu_reg); %} +instruct xorL_rReg_im1_ndd(rRegL dst,rRegL src, immL_M1 imm) +%{ + predicate(UseAPX); + match(Set dst (XorL src imm)); + + format %{ "enotq $dst, $src" %} + ins_encode %{ + __ enotq($dst$$Register, $src$$Register); + %} + ins_pipe(ialu_reg); +%} + // Xor Register with Immediate instruct xorL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr) %{ + predicate(!UseAPX); match(Set dst (XorL dst src)); effect(KILL cr); flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag); @@ -9679,9 +11275,39 @@ instruct xorL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr) ins_pipe(ialu_reg); %} +instruct xorL_rReg_rReg_imm(rRegL dst, rRegL src1, immL32 src2, rFlagsReg cr) +%{ + predicate(UseAPX); + match(Set dst (XorL src1 src2)); + effect(KILL cr); + flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag); + + format %{ "exorq $dst, $src1, $src2\t# long ndd" %} + ins_encode %{ + __ exorq($dst$$Register, $src1$$Register, $src2$$constant, false); + %} + ins_pipe(ialu_reg); +%} + +// Xor Memory with Immediate +instruct xorL_rReg_mem_imm(rRegL dst, memory src1, immL32 src2, rFlagsReg cr) +%{ + predicate(UseAPX); + match(Set dst (XorL (LoadL src1) src2)); + effect(KILL cr); + flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag); + + format %{ "exorq $dst, $src1, $src2\t# long ndd" %} + ins_encode %{ + __ exorq($dst$$Register, $src1$$Address, $src2$$constant, false); + %} + ins_pipe(ialu_reg); +%} + // Xor Register with Memory instruct xorL_rReg_mem(rRegL dst, memory src, rFlagsReg cr) %{ + predicate(!UseAPX); match(Set dst (XorL dst (LoadL src))); effect(KILL cr); flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag); @@ -9694,6 +11320,36 @@ instruct xorL_rReg_mem(rRegL dst, memory src, rFlagsReg cr) ins_pipe(ialu_reg_mem); %} +instruct xorL_rReg_rReg_mem_ndd(rRegL dst, rRegL src1, memory src2, rFlagsReg cr) +%{ + predicate(UseAPX); + match(Set dst (XorL src1 (LoadL src2))); + effect(KILL cr); + flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag); + + ins_cost(150); + format %{ "exorq $dst, $src1, $src2\t# long ndd" %} + ins_encode %{ + __ exorq($dst$$Register, $src1$$Register, $src2$$Address, false); + %} + ins_pipe(ialu_reg_mem); +%} + +instruct xorL_rReg_mem_rReg_ndd(rRegL dst, memory src1, rRegL src2, rFlagsReg cr) +%{ + predicate(UseAPX); + match(Set dst (XorL (LoadL src1) src2)); + effect(KILL cr); + flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag); + + ins_cost(150); + format %{ "exorq $dst, $src1, $src2\t# long ndd" %} + ins_encode %{ + __ exorq($dst$$Register, $src1$$Address, $src1$$Register, false); + %} + ins_pipe(ialu_reg_mem); +%} + // Xor Memory with Register instruct xorL_mem_rReg(memory dst, rRegL src, rFlagsReg cr) %{ @@ -12007,6 +13663,7 @@ instruct testB_mem_imm(rFlagsReg cr, memory mem, immI8 imm, immI_0 zero) instruct cmovI_reg_g(rRegI dst, rRegI src, rFlagsReg cr) %{ + predicate(!UseAPX); effect(USE_DEF dst, USE src, USE cr); format %{ "cmovlgt $dst, $src\t# min" %} @@ -12016,9 +13673,21 @@ instruct cmovI_reg_g(rRegI dst, rRegI src, rFlagsReg cr) ins_pipe(pipe_cmov_reg); %} +instruct cmovI_reg_g_ndd(rRegI dst, rRegI src1, rRegI src2, rFlagsReg cr) +%{ + predicate(UseAPX); + effect(DEF dst, USE src1, USE src2, USE cr); + + format %{ "ecmovlgt $dst, $src1, $src2\t# min ndd" %} + ins_encode %{ + __ ecmovl(Assembler::greater, $dst$$Register, $src1$$Register, $src2$$Register); + %} + ins_pipe(pipe_cmov_reg); +%} instruct minI_rReg(rRegI dst, rRegI src) %{ + predicate(!UseAPX); match(Set dst (MinI dst src)); ins_cost(200); @@ -12029,8 +13698,23 @@ instruct minI_rReg(rRegI dst, rRegI src) %} %} +instruct minI_rReg_ndd(rRegI dst, rRegI src1, rRegI src2) +%{ + predicate(UseAPX); + match(Set dst (MinI src1 src2)); + effect(DEF dst, USE src1, USE src2); + + ins_cost(200); + expand %{ + rFlagsReg cr; + compI_rReg(cr, src1, src2); + cmovI_reg_g_ndd(dst, src1, src2, cr); + %} +%} + instruct cmovI_reg_l(rRegI dst, rRegI src, rFlagsReg cr) %{ + predicate(!UseAPX); effect(USE_DEF dst, USE src, USE cr); format %{ "cmovllt $dst, $src\t# max" %} @@ -12040,9 +13724,21 @@ instruct cmovI_reg_l(rRegI dst, rRegI src, rFlagsReg cr) ins_pipe(pipe_cmov_reg); %} +instruct cmovI_reg_l_ndd(rRegI dst, rRegI src1, rRegI src2, rFlagsReg cr) +%{ + predicate(UseAPX); + effect(DEF dst, USE src1, USE src2, USE cr); + + format %{ "ecmovllt $dst, $src1, $src2\t# max ndd" %} + ins_encode %{ + __ ecmovl(Assembler::less, $dst$$Register, $src1$$Register, $src2$$Register); + %} + ins_pipe(pipe_cmov_reg); +%} instruct maxI_rReg(rRegI dst, rRegI src) %{ + predicate(!UseAPX); match(Set dst (MaxI dst src)); ins_cost(200); @@ -12053,6 +13749,20 @@ instruct maxI_rReg(rRegI dst, rRegI src) %} %} +instruct maxI_rReg_ndd(rRegI dst, rRegI src1, rRegI src2) +%{ + predicate(UseAPX); + match(Set dst (MaxI src1 src2)); + effect(DEF dst, USE src1, USE src2); + + ins_cost(200); + expand %{ + rFlagsReg cr; + compI_rReg(cr, src1, src2); + cmovI_reg_l_ndd(dst, src1, src2, cr); + %} +%} + // ============================================================================ // Branch Instructions diff --git a/test/hotspot/gtest/x86/asmtest.out.h b/test/hotspot/gtest/x86/asmtest.out.h index f43a9527e0f..ac4a8a21aeb 100644 --- a/test/hotspot/gtest/x86/asmtest.out.h +++ b/test/hotspot/gtest/x86/asmtest.out.h @@ -266,414 +266,472 @@ __ exorb(r9, Address(r31, +0x72a4f58e), r30, false); // {EVEX}xor r9b, byte ptr [r31+0x72a4f58e], r30b IID252 __ exorb(r24, Address(r25, r15, (Address::ScaleFactor)0, +0x20fc1a0a), r16, true); // {NF}xor r24b, byte ptr [r25+r15*1+0x20fc1a0a], r16b IID253 __ eaddl(r12, rbx, 65536, false); // {EVEX}add r12d, ebx, 65536 IID254 - __ eaddl(r20, r24, 4096, true); // {NF}add r20d, r24d, 4096 IID255 - __ eandl(r18, r26, 1048576, false); // {EVEX}and r18d, r26d, 1048576 IID256 - __ eandl(r29, r13, 1, true); // {NF}and r29d, r13d, 1 IID257 - __ eimull(rcx, r31, 65536, false); // {EVEX}imul ecx, r31d, 65536 IID258 - __ eimull(r23, r29, 65536, true); // {NF}imul r23d, r29d, 65536 IID259 - __ eorl(r23, r23, 1048576, false); // {EVEX}or r23d, r23d, 1048576 IID260 - __ eorl(r21, r9, 268435456, true); // {NF}or r21d, r9d, 268435456 IID261 - __ ercll(r13, rdx, 4); // {EVEX}rcl r13d, edx, 4 IID262 - __ eroll(r15, r31, 8, false); // {EVEX}rol r15d, r31d, 8 IID263 - __ eroll(r8, r9, 2, true); // {NF}rol r8d, r9d, 2 IID264 - __ erorl(r9, r15, 8, false); // {EVEX}ror r9d, r15d, 8 IID265 - __ erorl(r21, r12, 8, true); // {NF}ror r21d, r12d, 8 IID266 - __ esall(r19, r27, 1, false); // {EVEX}sal r19d, r27d, 1 IID267 - __ esall(r10, r11, 16, true); // {NF}sal r10d, r11d, 16 IID268 - __ esarl(r8, rdx, 8, false); // {EVEX}sar r8d, edx, 8 IID269 - __ esarl(r22, r30, 4, true); // {NF}sar r22d, r30d, 4 IID270 - __ eshll(r25, r31, 16, false); // {EVEX}shl r25d, r31d, 16 IID271 - __ eshll(r10, r9, 8, true); // {NF}shl r10d, r9d, 8 IID272 - __ eshrl(r13, r8, 4, false); // {EVEX}shr r13d, r8d, 4 IID273 - __ eshrl(r16, r21, 16, true); // {NF}shr r16d, r21d, 16 IID274 - __ esubl(r26, r23, 16777216, false); // {EVEX}sub r26d, r23d, 16777216 IID275 - __ esubl(r26, r14, 1048576, true); // {NF}sub r26d, r14d, 1048576 IID276 - __ exorl(r27, r26, 256, false); // {EVEX}xor r27d, r26d, 256 IID277 - __ exorl(r22, r9, 1, true); // {NF}xor r22d, r9d, 1 IID278 - __ esubl_imm32(r22, r30, 268435456, false); // {EVEX}sub r22d, r30d, 268435456 IID279 - __ esubl_imm32(r8, r16, 4194304, true); // {NF}sub r8d, r16d, 4194304 IID280 - __ eaddl(r20, r29, Address(r11, r12, (Address::ScaleFactor)1, +0xac0980), false); // {EVEX}add r20d, r29d, dword ptr [r11+r12*2+0xac0980] IID281 - __ eaddl(r18, rbx, Address(r9, r18, (Address::ScaleFactor)1, +0x434a125d), true); // {NF}add r18d, ebx, dword ptr [r9+r18*2+0x434a125d] IID282 - __ eandl(r14, r15, Address(r14, r19, (Address::ScaleFactor)2, +0x15a5a5ee), false); // {EVEX}and r14d, r15d, dword ptr [r14+r19*4+0x15a5a5ee] IID283 - __ eandl(r28, r31, Address(r24, r12, (Address::ScaleFactor)3, -0x6d6d7e68), true); // {NF}and r28d, r31d, dword ptr [r24+r12*8-0x6d6d7e68] IID284 - __ eimull(r24, r13, Address(r24, r25, (Address::ScaleFactor)3, +0x784673fd), false); // {EVEX}imul r24d, r13d, dword ptr [r24+r25*8+0x784673fd] IID285 - __ eimull(r24, r21, Address(r8, r13, (Address::ScaleFactor)2, -0x63663889), true); // {NF}imul r24d, r21d, dword ptr [r8+r13*4-0x63663889] IID286 - __ eorl(r12, r24, Address(r30, -0x67526556), false); // {EVEX}or r12d, r24d, dword ptr [r30-0x67526556] IID287 - __ eorl(r13, r13, Address(rbx, r25, (Address::ScaleFactor)2, -0x5f394dd9), true); // {NF}or r13d, r13d, dword ptr [rbx+r25*4-0x5f394dd9] IID288 - __ esubl(r26, r25, Address(r25, rdx, (Address::ScaleFactor)3, -0x2e39f79a), false); // {EVEX}sub r26d, r25d, dword ptr [r25+rdx*8-0x2e39f79a] IID289 - __ esubl(r28, r8, Address(rdx, r24, (Address::ScaleFactor)3, -0xed99a54), true); // {NF}sub r28d, r8d, dword ptr [rdx+r24*8-0xed99a54] IID290 - __ exorl(r31, r22, Address(r30, r20, (Address::ScaleFactor)3, +0x3ac41cbd), false); // {EVEX}xor r31d, r22d, dword ptr [r30+r20*8+0x3ac41cbd] IID291 - __ exorl(r24, r30, Address(r13, r17, (Address::ScaleFactor)1, +0x1efdc2e3), true); // {NF}xor r24d, r30d, dword ptr [r13+r17*2+0x1efdc2e3] IID292 - __ exorb(r16, r16, Address(r9, r15, (Address::ScaleFactor)1, +0x769feb34), false); // {EVEX}xor r16b, r16b, byte ptr [r9+r15*2+0x769feb34] IID293 - __ exorb(r19, r25, Address(r10, +0x2239b429), true); // {NF}xor r19b, r25b, byte ptr [r10+0x2239b429] IID294 - __ exorw(r25, r19, Address(r16, r24, (Address::ScaleFactor)1, +0x1c71faea), false); // {EVEX}xor r25w, r19w, word ptr [r16+r24*2+0x1c71faea] IID295 - __ exorw(r19, r10, Address(r28, -0x299a0cfd), true); // {NF}xor r19w, r10w, word ptr [r28-0x299a0cfd] IID296 - __ eaddl(rbx, r23, r24, false); // {load}{EVEX}add ebx, r23d, r24d IID297 - __ eaddl(r28, r14, r24, true); // {load}{NF}add r28d, r14d, r24d IID298 - __ eandl(r30, r31, r26, false); // {load}{EVEX}and r30d, r31d, r26d IID299 - __ eandl(r12, r31, r23, true); // {load}{NF}and r12d, r31d, r23d IID300 - __ eimull(r9, r20, r10, false); // {load}{EVEX}imul r9d, r20d, r10d IID301 - __ eimull(r13, r30, r9, true); // {load}{NF}imul r13d, r30d, r9d IID302 - __ eorw(r25, r19, r23, false); // {load}{EVEX}or r25w, r19w, r23w IID303 - __ eorw(r12, r16, rdx, true); // {load}{NF}or r12w, r16w, dx IID304 - __ eorl(r31, r17, r9, false); // {load}{EVEX}or r31d, r17d, r9d IID305 - __ eorl(r15, r13, rbx, true); // {load}{NF}or r15d, r13d, ebx IID306 - __ eshldl(r28, rbx, r29, false); // {load}{EVEX}shld r28d, ebx, r29d, cl IID307 - __ eshldl(r22, rbx, r8, true); // {load}{NF}shld r22d, ebx, r8d, cl IID308 - __ eshrdl(r8, r11, r16, false); // {load}{EVEX}shrd r8d, r11d, r16d, cl IID309 - __ eshrdl(r13, r12, r15, true); // {load}{NF}shrd r13d, r12d, r15d, cl IID310 - __ esubl(r17, r23, r31, false); // {load}{EVEX}sub r17d, r23d, r31d IID311 - __ esubl(r20, r22, r26, true); // {load}{NF}sub r20d, r22d, r26d IID312 - __ exorl(r10, r25, r19, false); // {load}{EVEX}xor r10d, r25d, r19d IID313 - __ exorl(r11, r19, r30, true); // {load}{NF}xor r11d, r19d, r30d IID314 - __ eshldl(r12, r10, rdx, 1, false); // {EVEX}shld r12d, r10d, edx, 1 IID315 - __ eshldl(r20, r30, r18, 16, true); // {NF}shld r20d, r30d, r18d, 16 IID316 - __ eshrdl(r18, r25, r18, 8, false); // {EVEX}shrd r18d, r25d, r18d, 8 IID317 - __ eshrdl(r19, r16, r25, 1, true); // {NF}shrd r19d, r16d, r25d, 1 IID318 - __ ecmovl (Assembler::Condition::overflow, r11, r31, r24); // cmovo r11d, r31d, r24d IID319 - __ ecmovl (Assembler::Condition::noOverflow, r14, r30, r16); // cmovno r14d, r30d, r16d IID320 - __ ecmovl (Assembler::Condition::below, r9, r11, r26); // cmovb r9d, r11d, r26d IID321 - __ ecmovl (Assembler::Condition::aboveEqual, r27, rdx, r31); // cmovae r27d, edx, r31d IID322 - __ ecmovl (Assembler::Condition::zero, r24, r29, r10); // cmovz r24d, r29d, r10d IID323 - __ ecmovl (Assembler::Condition::notZero, rcx, r21, r15); // cmovnz ecx, r21d, r15d IID324 - __ ecmovl (Assembler::Condition::belowEqual, r23, r17, r26); // cmovbe r23d, r17d, r26d IID325 - __ ecmovl (Assembler::Condition::above, r20, r27, r13); // cmova r20d, r27d, r13d IID326 - __ ecmovl (Assembler::Condition::negative, r15, r22, r15); // cmovs r15d, r22d, r15d IID327 - __ ecmovl (Assembler::Condition::positive, r29, r26, r18); // cmovns r29d, r26d, r18d IID328 - __ ecmovl (Assembler::Condition::parity, r9, r9, r22); // cmovp r9d, r9d, r22d IID329 - __ ecmovl (Assembler::Condition::noParity, r30, r23, r11); // cmovnp r30d, r23d, r11d IID330 - __ ecmovl (Assembler::Condition::less, r20, r11, rbx); // cmovl r20d, r11d, ebx IID331 - __ ecmovl (Assembler::Condition::greaterEqual, r28, r16, r20); // cmovge r28d, r16d, r20d IID332 - __ ecmovl (Assembler::Condition::lessEqual, r17, r24, r22); // cmovle r17d, r24d, r22d IID333 - __ ecmovl (Assembler::Condition::greater, r16, r15, r15); // cmovg r16d, r15d, r15d IID334 - __ ecmovl (Assembler::Condition::overflow, r28, r25, Address(r29, r16, (Address::ScaleFactor)2, -0x3c9110ad)); // cmovo r28d, r25d, dword ptr [r29+r16*4-0x3c9110ad] IID335 - __ ecmovl (Assembler::Condition::noOverflow, r23, r15, Address(rbx, r30, (Address::ScaleFactor)3, +0x1cbc58bd)); // cmovno r23d, r15d, dword ptr [rbx+r30*8+0x1cbc58bd] IID336 - __ ecmovl (Assembler::Condition::below, r26, rbx, Address(r12, rcx, (Address::ScaleFactor)3, +0x84e581a)); // cmovb r26d, ebx, dword ptr [r12+rcx*8+0x84e581a] IID337 - __ ecmovl (Assembler::Condition::aboveEqual, rcx, r24, Address(r17, +0x5cece92d)); // cmovae ecx, r24d, dword ptr [r17+0x5cece92d] IID338 - __ ecmovl (Assembler::Condition::zero, r26, r24, Address(r24, r12, (Address::ScaleFactor)3, +0x507746a2)); // cmovz r26d, r24d, dword ptr [r24+r12*8+0x507746a2] IID339 - __ ecmovl (Assembler::Condition::notZero, r8, r15, Address(rcx, r19, (Address::ScaleFactor)0, -0xf035c76)); // cmovnz r8d, r15d, dword ptr [rcx+r19*1-0xf035c76] IID340 - __ ecmovl (Assembler::Condition::belowEqual, rdx, r23, Address(r22, r27, (Address::ScaleFactor)0, -0x12fe3534)); // cmovbe edx, r23d, dword ptr [r22+r27*1-0x12fe3534] IID341 - __ ecmovl (Assembler::Condition::above, r30, r19, Address(r13, r28, (Address::ScaleFactor)0, +0x73b8ee9d)); // cmova r30d, r19d, dword ptr [r13+r28*1+0x73b8ee9d] IID342 - __ ecmovl (Assembler::Condition::negative, r22, r30, Address(r16, rcx, (Address::ScaleFactor)0, +0x22aac146)); // cmovs r22d, r30d, dword ptr [r16+rcx*1+0x22aac146] IID343 - __ ecmovl (Assembler::Condition::positive, r17, r30, Address(r17, r9, (Address::ScaleFactor)2, +0x79db2b1)); // cmovns r17d, r30d, dword ptr [r17+r9*4+0x79db2b1] IID344 - __ ecmovl (Assembler::Condition::parity, r26, rdx, Address(r14, r16, (Address::ScaleFactor)1, -0x8242011)); // cmovp r26d, edx, dword ptr [r14+r16*2-0x8242011] IID345 - __ ecmovl (Assembler::Condition::noParity, r11, r19, Address(r14, r31, (Address::ScaleFactor)1, -0x4ff251cc)); // cmovnp r11d, r19d, dword ptr [r14+r31*2-0x4ff251cc] IID346 - __ ecmovl (Assembler::Condition::less, r20, r18, Address(r13, r16, (Address::ScaleFactor)2, -0x19efc6e2)); // cmovl r20d, r18d, dword ptr [r13+r16*4-0x19efc6e2] IID347 - __ ecmovl (Assembler::Condition::greaterEqual, r19, r13, Address(r13, r23, (Address::ScaleFactor)1, +0x611b7714)); // cmovge r19d, r13d, dword ptr [r13+r23*2+0x611b7714] IID348 - __ ecmovl (Assembler::Condition::lessEqual, r29, r13, Address(r17, r17, (Address::ScaleFactor)3, +0x3a94a93f)); // cmovle r29d, r13d, dword ptr [r17+r17*8+0x3a94a93f] IID349 - __ ecmovl (Assembler::Condition::greater, r13, r29, Address(r15, r23, (Address::ScaleFactor)1, +0x76d43532)); // cmovg r13d, r29d, dword ptr [r15+r23*2+0x76d43532] IID350 + __ eaddl(rax, r11, 65536, false); // {EVEX}add eax, r11d, 65536 IID255 + __ eaddl(r24, r16, 268435456, true); // {NF}add r24d, r16d, 268435456 IID256 + __ eaddl(rax, r18, 268435456, true); // {NF}add eax, r18d, 268435456 IID257 + __ eandl(r29, r13, 1, false); // {EVEX}and r29d, r13d, 1 IID258 + __ eandl(rax, r13, 1, false); // {EVEX}and eax, r13d, 1 IID259 + __ eandl(r31, r22, 1, true); // {NF}and r31d, r22d, 1 IID260 + __ eandl(rax, r29, 1, true); // {NF}and eax, r29d, 1 IID261 + __ eimull(r23, r29, 65536, false); // {EVEX}imul r23d, r29d, 65536 IID262 + __ eimull(rax, r15, 65536, false); // {EVEX}imul eax, r15d, 65536 IID263 + __ eimull(r21, r9, 268435456, true); // {NF}imul r21d, r9d, 268435456 IID264 + __ eimull(rax, r15, 268435456, true); // {NF}imul eax, r15d, 268435456 IID265 + __ eorl(rdx, r18, 65536, false); // {EVEX}or edx, r18d, 65536 IID266 + __ eorl(rax, r15, 65536, false); // {EVEX}or eax, r15d, 65536 IID267 + __ eorl(r8, r9, 256, true); // {NF}or r8d, r9d, 256 IID268 + __ eorl(rax, r27, 256, true); // {NF}or eax, r27d, 256 IID269 + __ ercll(r9, r15, 8); // {EVEX}rcl r9d, r15d, 8 IID270 + __ ercll(rax, r18, 8); // {EVEX}rcl eax, r18d, 8 IID271 + __ eroll(r12, rbx, 16, false); // {EVEX}rol r12d, ebx, 16 IID272 + __ eroll(rax, r19, 16, false); // {EVEX}rol eax, r19d, 16 IID273 + __ eroll(r10, r11, 16, true); // {NF}rol r10d, r11d, 16 IID274 + __ eroll(rax, r18, 16, true); // {NF}rol eax, r18d, 16 IID275 + __ erorl(rdx, r14, 1, false); // {EVEX}ror edx, r14d, 1 IID276 + __ erorl(rax, r22, 1, false); // {EVEX}ror eax, r22d, 1 IID277 + __ erorl(r25, r31, 16, true); // {NF}ror r25d, r31d, 16 IID278 + __ erorl(rax, r19, 16, true); // {NF}ror eax, r19d, 16 IID279 + __ esall(r9, r15, 2, false); // {EVEX}sal r9d, r15d, 2 IID280 + __ esall(rax, r13, 2, false); // {EVEX}sal eax, r13d, 2 IID281 + __ esall(r21, r16, 1, true); // {NF}sal r21d, r16d, 1 IID282 + __ esall(rax, r21, 1, true); // {NF}sal eax, r21d, 1 IID283 + __ esarl(r26, r23, 8, false); // {EVEX}sar r26d, r23d, 8 IID284 + __ esarl(rax, r28, 8, false); // {EVEX}sar eax, r28d, 8 IID285 + __ esarl(r26, r14, 4, true); // {NF}sar r26d, r14d, 4 IID286 + __ esarl(rax, r10, 4, true); // {NF}sar eax, r10d, 4 IID287 + __ eshll(r22, r9, 1, false); // {EVEX}shl r22d, r9d, 1 IID288 + __ eshll(rax, r18, 1, false); // {EVEX}shl eax, r18d, 1 IID289 + __ eshll(r30, r24, 16, true); // {NF}shl r30d, r24d, 16 IID290 + __ eshll(rax, r23, 16, true); // {NF}shl eax, r23d, 16 IID291 + __ eshrl(r11, r8, 16, false); // {EVEX}shr r11d, r8d, 16 IID292 + __ eshrl(rax, r16, 16, false); // {EVEX}shr eax, r16d, 16 IID293 + __ eshrl(r11, r12, 8, true); // {NF}shr r11d, r12d, 8 IID294 + __ eshrl(rax, r29, 8, true); // {NF}shr eax, r29d, 8 IID295 + __ esubl(r16, r21, 1048576, false); // {EVEX}sub r16d, r21d, 1048576 IID296 + __ esubl(rax, r15, 1048576, false); // {EVEX}sub eax, r15d, 1048576 IID297 + __ esubl(r9, r18, 16777216, true); // {NF}sub r9d, r18d, 16777216 IID298 +#endif // _LP64 + __ esubl(rax, rbx, 16777216, true); // {NF}sub eax, ebx, 16777216 IID299 +#ifdef _LP64 + __ exorl(r19, r23, 65536, false); // {EVEX}xor r19d, r23d, 65536 IID300 + __ exorl(rax, r17, 65536, false); // {EVEX}xor eax, r17d, 65536 IID301 + __ exorl(r29, r18, 1048576, true); // {NF}xor r29d, r18d, 1048576 IID302 + __ exorl(rax, r14, 1048576, true); // {NF}xor eax, r14d, 1048576 IID303 + __ esubl_imm32(r19, r15, 16777216, false); // {EVEX}sub r19d, r15d, 16777216 IID304 + __ esubl_imm32(rax, r27, 16777216, false); // {EVEX}sub eax, r27d, 16777216 IID305 + __ esubl_imm32(r23, r27, 1073741824, true); // {NF}sub r23d, r27d, 1073741824 IID306 + __ esubl_imm32(rax, r23, 1073741824, true); // {NF}sub eax, r23d, 1073741824 IID307 + __ eaddl(r8, r12, Address(r28, r24, (Address::ScaleFactor)3, -0x6d6d7e68), false); // {EVEX}add r8d, r12d, dword ptr [r28+r24*8-0x6d6d7e68] IID308 + __ eaddl(r24, r13, Address(r24, r25, (Address::ScaleFactor)3, +0x784673fd), true); // {NF}add r24d, r13d, dword ptr [r24+r25*8+0x784673fd] IID309 + __ eandl(r24, r21, Address(r8, r13, (Address::ScaleFactor)2, -0x63663889), false); // {EVEX}and r24d, r21d, dword ptr [r8+r13*4-0x63663889] IID310 + __ eandl(r12, r24, Address(r30, -0x67526556), true); // {NF}and r12d, r24d, dword ptr [r30-0x67526556] IID311 + __ eimull(r13, r13, Address(rbx, r25, (Address::ScaleFactor)2, -0x5f394dd9), false); // {EVEX}imul r13d, r13d, dword ptr [rbx+r25*4-0x5f394dd9] IID312 + __ eimull(r26, r25, Address(r25, rdx, (Address::ScaleFactor)3, -0x2e39f79a), true); // {NF}imul r26d, r25d, dword ptr [r25+rdx*8-0x2e39f79a] IID313 + __ eorl(r28, r8, Address(rdx, r24, (Address::ScaleFactor)3, -0xed99a54), false); // {EVEX}or r28d, r8d, dword ptr [rdx+r24*8-0xed99a54] IID314 + __ eorl(r31, r22, Address(r30, r20, (Address::ScaleFactor)3, +0x3ac41cbd), true); // {NF}or r31d, r22d, dword ptr [r30+r20*8+0x3ac41cbd] IID315 + __ esubl(r24, r30, Address(r13, r17, (Address::ScaleFactor)1, +0x1efdc2e3), false); // {EVEX}sub r24d, r30d, dword ptr [r13+r17*2+0x1efdc2e3] IID316 + __ esubl(r16, r16, Address(r9, r15, (Address::ScaleFactor)1, +0x769feb34), true); // {NF}sub r16d, r16d, dword ptr [r9+r15*2+0x769feb34] IID317 + __ exorl(r19, r25, Address(r10, +0x2239b429), false); // {EVEX}xor r19d, r25d, dword ptr [r10+0x2239b429] IID318 + __ exorl(r25, r19, Address(r16, r24, (Address::ScaleFactor)1, +0x1c71faea), true); // {NF}xor r25d, r19d, dword ptr [r16+r24*2+0x1c71faea] IID319 + __ exorb(r19, r10, Address(r28, -0x299a0cfd), false); // {EVEX}xor r19b, r10b, byte ptr [r28-0x299a0cfd] IID320 + __ exorb(rbx, r28, Address(r23, r24, (Address::ScaleFactor)1, -0x5d78ddd9), true); // {NF}xor bl, r28b, byte ptr [r23+r24*2-0x5d78ddd9] IID321 + __ exorw(r10, r9, Address(r13, r30, (Address::ScaleFactor)2, +0x11151188), false); // {EVEX}xor r10w, r9w, word ptr [r13+r30*4+0x11151188] IID322 + __ exorw(r16, r17, Address(rdx, r31, (Address::ScaleFactor)0, +0x61936ce7), true); // {NF}xor r16w, r17w, word ptr [rdx+r31*1+0x61936ce7] IID323 + __ eaddl(r13, rbx, r28, false); // {load}{EVEX}add r13d, ebx, r28d IID324 + __ eaddl(rbx, r29, r22, true); // {load}{NF}add ebx, r29d, r22d IID325 + __ eandl(rbx, r8, r8, false); // {load}{EVEX}and ebx, r8d, r8d IID326 + __ eandl(r11, r16, r13, true); // {load}{NF}and r11d, r16d, r13d IID327 + __ eimull(r12, r15, r17, false); // {load}{EVEX}imul r12d, r15d, r17d IID328 + __ eimull(r23, r31, r20, true); // {load}{NF}imul r23d, r31d, r20d IID329 + __ eorw(r22, r26, r10, false); // {load}{EVEX}or r22w, r26w, r10w IID330 + __ eorw(r25, r19, r11, true); // {load}{NF}or r25w, r19w, r11w IID331 + __ eorl(r19, r30, r8, false); // {load}{EVEX}or r19d, r30d, r8d IID332 + __ eorl(r12, r10, rdx, true); // {load}{NF}or r12d, r10d, edx IID333 + __ eshldl(r22, r20, r30, false); // {load}{EVEX}shld r22d, r20d, r30d, cl IID334 + __ eshldl(r18, r19, r18, true); // {load}{NF}shld r18d, r19d, r18d, cl IID335 + __ eshrdl(r25, r18, rcx, false); // {load}{EVEX}shrd r25d, r18d, ecx, cl IID336 + __ eshrdl(r19, r16, r25, true); // {load}{NF}shrd r19d, r16d, r25d, cl IID337 + __ esubl(r11, r31, r24, false); // {load}{EVEX}sub r11d, r31d, r24d IID338 + __ esubl(r14, r30, r16, true); // {load}{NF}sub r14d, r30d, r16d IID339 + __ exorl(r9, r11, r26, false); // {load}{EVEX}xor r9d, r11d, r26d IID340 + __ exorl(r27, rdx, r31, true); // {load}{NF}xor r27d, edx, r31d IID341 + __ eshldl(r29, r10, rcx, 16, false); // {EVEX}shld r29d, r10d, ecx, 16 IID342 + __ eshldl(r15, r23, r17, 16, true); // {NF}shld r15d, r23d, r17d, 16 IID343 + __ eshrdl(r27, r13, r15, 8, false); // {EVEX}shrd r27d, r13d, r15d, 8 IID344 + __ eshrdl(r15, r29, r26, 16, true); // {NF}shrd r15d, r29d, r26d, 16 IID345 + __ ecmovl (Assembler::Condition::overflow, r18, r9, r9); // cmovo r18d, r9d, r9d IID346 + __ ecmovl (Assembler::Condition::noOverflow, r22, r30, r23); // cmovno r22d, r30d, r23d IID347 + __ ecmovl (Assembler::Condition::below, r11, r20, r11); // cmovb r11d, r20d, r11d IID348 + __ ecmovl (Assembler::Condition::aboveEqual, rbx, r28, r16); // cmovae ebx, r28d, r16d IID349 + __ ecmovl (Assembler::Condition::zero, r20, r17, r24); // cmovz r20d, r17d, r24d IID350 + __ ecmovl (Assembler::Condition::notZero, r22, r16, r15); // cmovnz r22d, r16d, r15d IID351 + __ ecmovl (Assembler::Condition::belowEqual, r15, r28, r29); // cmovbe r15d, r28d, r29d IID352 + __ ecmovl (Assembler::Condition::above, r16, r25, r25); // cmova r16d, r25d, r25d IID353 + __ ecmovl (Assembler::Condition::negative, r17, r13, r17); // cmovs r17d, r13d, r17d IID354 + __ ecmovl (Assembler::Condition::positive, r23, rbx, r30); // cmovns r23d, ebx, r30d IID355 + __ ecmovl (Assembler::Condition::parity, r15, r22, r11); // cmovp r15d, r22d, r11d IID356 + __ ecmovl (Assembler::Condition::noParity, r27, rdx, r22); // cmovnp r27d, edx, r22d IID357 + __ ecmovl (Assembler::Condition::less, r9, r17, r28); // cmovl r9d, r17d, r28d IID358 + __ ecmovl (Assembler::Condition::greaterEqual, r24, r11, r26); // cmovge r24d, r11d, r26d IID359 + __ ecmovl (Assembler::Condition::lessEqual, r12, rcx, rbx); // cmovle r12d, ecx, ebx IID360 + __ ecmovl (Assembler::Condition::greater, r28, r22, r22); // cmovg r28d, r22d, r22d IID361 + __ ecmovl (Assembler::Condition::overflow, r10, r14, Address(rcx, r17, (Address::ScaleFactor)3, -0x7857b23d)); // cmovo r10d, r14d, dword ptr [rcx+r17*8-0x7857b23d] IID362 + __ ecmovl (Assembler::Condition::noOverflow, r17, r12, Address(r26, r24, (Address::ScaleFactor)3, +0x10642223)); // cmovno r17d, r12d, dword ptr [r26+r24*8+0x10642223] IID363 + __ ecmovl (Assembler::Condition::below, r26, r8, Address(r31, -0xb2d2be4)); // cmovb r26d, r8d, dword ptr [r31-0xb2d2be4] IID364 + __ ecmovl (Assembler::Condition::aboveEqual, r12, r20, Address(r12, r22, (Address::ScaleFactor)2, -0x667ff72b)); // cmovae r12d, r20d, dword ptr [r12+r22*4-0x667ff72b] IID365 + __ ecmovl (Assembler::Condition::zero, r22, r9, Address(r27, r23, (Address::ScaleFactor)2, +0x66ce4d22)); // cmovz r22d, r9d, dword ptr [r27+r23*4+0x66ce4d22] IID366 + __ ecmovl (Assembler::Condition::notZero, r12, r8, Address(r30, r27, (Address::ScaleFactor)3, -0x2b9676e1)); // cmovnz r12d, r8d, dword ptr [r30+r27*8-0x2b9676e1] IID367 + __ ecmovl (Assembler::Condition::belowEqual, r17, r20, Address(r9, r30, (Address::ScaleFactor)3, -0x351022df)); // cmovbe r17d, r20d, dword ptr [r9+r30*8-0x351022df] IID368 + __ ecmovl (Assembler::Condition::above, rdx, r8, Address(r14, +0x3d6b7a59)); // cmova edx, r8d, dword ptr [r14+0x3d6b7a59] IID369 + __ ecmovl (Assembler::Condition::negative, rcx, r31, Address(r11, r14, (Address::ScaleFactor)2, +0x2cd585f2)); // cmovs ecx, r31d, dword ptr [r11+r14*4+0x2cd585f2] IID370 + __ ecmovl (Assembler::Condition::positive, r25, r18, Address(r24, r11, (Address::ScaleFactor)2, -0x3f699c34)); // cmovns r25d, r18d, dword ptr [r24+r11*4-0x3f699c34] IID371 + __ ecmovl (Assembler::Condition::parity, r18, r8, Address(r19, r17, (Address::ScaleFactor)2, -0x390da4c5)); // cmovp r18d, r8d, dword ptr [r19+r17*4-0x390da4c5] IID372 + __ ecmovl (Assembler::Condition::noParity, r11, r29, Address(r29, rdx, (Address::ScaleFactor)2, +0x3a94a93f)); // cmovnp r11d, r29d, dword ptr [r29+rdx*4+0x3a94a93f] IID373 + __ ecmovl (Assembler::Condition::less, r13, r29, Address(r15, r23, (Address::ScaleFactor)1, +0x76d43532)); // cmovl r13d, r29d, dword ptr [r15+r23*2+0x76d43532] IID374 + __ ecmovl (Assembler::Condition::greaterEqual, r15, r12, Address(r13, r9, (Address::ScaleFactor)1, +0x16f7a5b)); // cmovge r15d, r12d, dword ptr [r13+r9*2+0x16f7a5b] IID375 + __ ecmovl (Assembler::Condition::lessEqual, r9, rdx, Address(r17, r23, (Address::ScaleFactor)1, +0x43b6bfe1)); // cmovle r9d, edx, dword ptr [r17+r23*2+0x43b6bfe1] IID376 + __ ecmovl (Assembler::Condition::greater, r28, r20, Address(r24, r10, (Address::ScaleFactor)0, -0x326e802f)); // cmovg r28d, r20d, dword ptr [r24+r10*1-0x326e802f] IID377 #endif // _LP64 #ifdef _LP64 - __ adcq(r15, r13); // {load}adc r15, r13 IID351 - __ cmpq(r9, r12); // {load}cmp r9, r12 IID352 - __ imulq(r15, r21); // {load}imul r15, r21 IID353 - __ popcntq(r12, r9); // {load}popcnt r12, r9 IID354 - __ sbbq(r17, r23); // {load}sbb r17, r23 IID355 - __ subq(rdx, r16); // {load}sub rdx, r16 IID356 - __ tzcntq(r29, r10); // {load}tzcnt r29, r10 IID357 - __ lzcntq(r21, r17); // {load}lzcnt r21, r17 IID358 - __ addq(r29, r18); // {load}add r29, r18 IID359 - __ andq(r28, r24); // {load}and r28, r24 IID360 - __ orq(r10, r20); // {load}or r10, r20 IID361 - __ xorq(r27, r10); // {load}xor r27, r10 IID362 - __ movq(r14, r11); // {load}mov r14, r11 IID363 - __ bsfq(r27, rcx); // {load}bsf r27, rcx IID364 - __ bsrq(r22, r15); // {load}bsr r22, r15 IID365 - __ btq(r31, r30); // {load}bt r31, r30 IID366 - __ xchgq(r19, r19); // {load}xchg r19, r19 IID367 - __ testq(r26, r21); // {load}test r26, r21 IID368 - __ addq(Address(r26, r20, (Address::ScaleFactor)1, -0x4096149c), r14); // add qword ptr [r26+r20*2-0x4096149c], r14 IID369 - __ andq(Address(r28, r20, (Address::ScaleFactor)2, +0x1bd8898a), r23); // and qword ptr [r28+r20*4+0x1bd8898a], r23 IID370 - __ cmpq(Address(r15, r19, (Address::ScaleFactor)2, +0x39eee631), r10); // cmp qword ptr [r15+r19*4+0x39eee631], r10 IID371 - __ orq(Address(r13, rdx, (Address::ScaleFactor)3, +0x1a49859), r13); // or qword ptr [r13+rdx*8+0x1a49859], r13 IID372 - __ xorq(Address(r21, +0x5fe8636), r24); // xor qword ptr [r21+0x5fe8636], r24 IID373 - __ subq(Address(r30, r23, (Address::ScaleFactor)2, -0x56643cc1), r25); // sub qword ptr [r30+r23*4-0x56643cc1], r25 IID374 - __ movq(Address(r21, r26, (Address::ScaleFactor)3, +0x7e8544ab), r31); // mov qword ptr [r21+r26*8+0x7e8544ab], r31 IID375 - __ xaddq(Address(rcx, r24, (Address::ScaleFactor)3, -0x79ca4889), rbx); // xadd qword ptr [rcx+r24*8-0x79ca4889], rbx IID376 - __ andq(Address(r13, r31, (Address::ScaleFactor)3, -0xd72b030), 256); // and qword ptr [r13+r31*8-0xd72b030], 256 IID377 - __ addq(Address(r16, +0x534d775e), 268435456); // add qword ptr [r16+0x534d775e], 268435456 IID378 - __ cmpq(Address(r20, r15, (Address::ScaleFactor)2, -0x7cb22277), 268435456); // cmp qword ptr [r20+r15*4-0x7cb22277], 268435456 IID379 - __ sarq(Address(r9, r23, (Address::ScaleFactor)2, -0x72f6d86e), 4); // sar qword ptr [r9+r23*4-0x72f6d86e], 4 IID380 - __ salq(Address(r11, r24, (Address::ScaleFactor)1, -0x22826f95), 4); // sal qword ptr [r11+r24*2-0x22826f95], 4 IID381 - __ sbbq(Address(r14, r30, (Address::ScaleFactor)1, +0x1b43fc34), 268435456); // sbb qword ptr [r14+r30*2+0x1b43fc34], 268435456 IID382 - __ shrq(Address(r26, r21, (Address::ScaleFactor)0, -0x3bae50c3), 8); // shr qword ptr [r26+r21*1-0x3bae50c3], 8 IID383 - __ subq(Address(r22, r10, (Address::ScaleFactor)3, +0x47e1403), 65536); // sub qword ptr [r22+r10*8+0x47e1403], 65536 IID384 - __ xorq(Address(rdx, r19, (Address::ScaleFactor)3, -0x644a5318), 1); // xor qword ptr [rdx+r19*8-0x644a5318], 1 IID385 - __ orq(Address(r30, r31, (Address::ScaleFactor)1, +0x2c93c783), 256); // or qword ptr [r30+r31*2+0x2c93c783], 256 IID386 - __ movq(Address(r26, r24, (Address::ScaleFactor)2, -0x534785f), 65536); // mov qword ptr [r26+r24*4-0x534785f], 65536 IID387 - __ testq(Address(r14, r30, (Address::ScaleFactor)1, +0x3932e147), -256); // test qword ptr [r14+r30*2+0x3932e147], -256 IID388 - __ addq(r30, Address(r30, r24, (Address::ScaleFactor)3, -0x66e0235e)); // add r30, qword ptr [r30+r24*8-0x66e0235e] IID389 - __ andq(r15, Address(r26, +0x36456e42)); // and r15, qword ptr [r26+0x36456e42] IID390 - __ cmpq(r10, Address(r18, +0x5044bed)); // cmp r10, qword ptr [r18+0x5044bed] IID391 - __ lzcntq(r31, Address(r12, rdx, (Address::ScaleFactor)2, -0x1707b7d4)); // lzcnt r31, qword ptr [r12+rdx*4-0x1707b7d4] IID392 - __ orq(r16, Address(r20, r23, (Address::ScaleFactor)2, -0x26783729)); // or r16, qword ptr [r20+r23*4-0x26783729] IID393 - __ adcq(r31, Address(r30, r31, (Address::ScaleFactor)0, +0x1ec3265d)); // adc r31, qword ptr [r30+r31*1+0x1ec3265d] IID394 - __ imulq(r16, Address(rdx, r26, (Address::ScaleFactor)0, +0x3586831b)); // imul r16, qword ptr [rdx+r26*1+0x3586831b] IID395 - __ popcntq(r12, Address(r18, -0x3c3e9f7a)); // popcnt r12, qword ptr [r18-0x3c3e9f7a] IID396 - __ sbbq(rcx, Address(r8, r21, (Address::ScaleFactor)3, +0x6b1515ab)); // sbb rcx, qword ptr [r8+r21*8+0x6b1515ab] IID397 - __ subq(r29, Address(rcx, r23, (Address::ScaleFactor)2, +0x4ff06c4d)); // sub r29, qword ptr [rcx+r23*4+0x4ff06c4d] IID398 - __ tzcntq(r26, Address(r24, r10, (Address::ScaleFactor)1, -0x75d9a189)); // tzcnt r26, qword ptr [r24+r10*2-0x75d9a189] IID399 - __ xorq(r17, Address(rbx, rbx, (Address::ScaleFactor)0, +0x4033d59c)); // xor r17, qword ptr [rbx+rbx*1+0x4033d59c] IID400 - __ movq(r18, Address(r22, r12, (Address::ScaleFactor)3, -0x3893347d)); // mov r18, qword ptr [r22+r12*8-0x3893347d] IID401 - __ leaq(r12, Address(r20, r23, (Address::ScaleFactor)3, +0x4b311560)); // lea r12, qword ptr [r20+r23*8+0x4b311560] IID402 - __ cvttsd2siq(r29, Address(r10, r28, (Address::ScaleFactor)2, +0x5c3a2657)); // cvttsd2si r29, qword ptr [r10+r28*4+0x5c3a2657] IID403 - __ xchgq(r22, Address(r13, r25, (Address::ScaleFactor)3, +0x1a3d6f3f)); // xchg r22, qword ptr [r13+r25*8+0x1a3d6f3f] IID404 - __ testq(r25, Address(r17, r24, (Address::ScaleFactor)3, -0x35addbd8)); // test r25, qword ptr [r17+r24*8-0x35addbd8] IID405 - __ addq(r18, 1); // add r18, 1 IID406 - __ andq(r13, 16777216); // and r13, 16777216 IID407 - __ adcq(r13, 65536); // adc r13, 65536 IID408 - __ cmpq(r10, 65536); // cmp r10, 65536 IID409 - __ rclq(r20, 2); // rcl r20, 2 IID410 - __ rcrq(r9, 16); // rcr r9, 16 IID411 - __ rolq(r8, 1); // rol r8, 1 IID412 - __ rorq(r25, 2); // ror r25, 2 IID413 - __ sarq(r22, 8); // sar r22, 8 IID414 - __ salq(r17, 1); // sal r17, 1 IID415 - __ sbbq(r31, 16); // sbb r31, 16 IID416 - __ shlq(r27, 4); // shl r27, 4 IID417 - __ shrq(r28, 2); // shr r28, 2 IID418 - __ subq(rcx, 16777216); // sub rcx, 16777216 IID419 - __ xorq(r27, 1048576); // xor r27, 1048576 IID420 - __ movq(r20, 268435456); // mov r20, 268435456 IID421 - __ mov64(r27, 4503599627370496); // mov r27, 4503599627370496 IID422 - __ btq(r22, 4); // bt r22, 4 IID423 - __ testq(r8, -4096); // test r8, -4096 IID424 - __ orq_imm32(r28, 1048576); // or r28, 1048576 IID425 - __ subq_imm32(r13, 65536); // sub r13, 65536 IID426 - __ cmovq(Assembler::Condition::overflow, r16, Address(r16, -0x1389a3eb)); // cmovo r16, qword ptr [r16-0x1389a3eb] IID427 - __ cmovq(Assembler::Condition::noOverflow, rbx, Address(r29, r8, (Address::ScaleFactor)0, +0x1d022615)); // cmovno rbx, qword ptr [r29+r8*1+0x1d022615] IID428 - __ cmovq(Assembler::Condition::below, rdx, Address(r12, r28, (Address::ScaleFactor)1, -0x34c898e2)); // cmovb rdx, qword ptr [r12+r28*2-0x34c898e2] IID429 - __ cmovq(Assembler::Condition::aboveEqual, r27, Address(r10, rcx, (Address::ScaleFactor)3, -0x1ef7abf1)); // cmovae r27, qword ptr [r10+rcx*8-0x1ef7abf1] IID430 - __ cmovq(Assembler::Condition::zero, r14, Address(r13, r29, (Address::ScaleFactor)2, -0x7c4c8369)); // cmovz r14, qword ptr [r13+r29*4-0x7c4c8369] IID431 - __ cmovq(Assembler::Condition::notZero, r15, Address(r23, rcx, (Address::ScaleFactor)2, -0x6bd22ccf)); // cmovnz r15, qword ptr [r23+rcx*4-0x6bd22ccf] IID432 - __ cmovq(Assembler::Condition::belowEqual, r24, Address(r15, r10, (Address::ScaleFactor)1, -0x7ffb3d09)); // cmovbe r24, qword ptr [r15+r10*2-0x7ffb3d09] IID433 - __ cmovq(Assembler::Condition::above, r23, Address(r11, +0x276a863b)); // cmova r23, qword ptr [r11+0x276a863b] IID434 - __ cmovq(Assembler::Condition::negative, r28, Address(r29, +0x3fb4396e)); // cmovs r28, qword ptr [r29+0x3fb4396e] IID435 - __ cmovq(Assembler::Condition::positive, r26, Address(r27, rcx, (Address::ScaleFactor)3, +0x4ddea61c)); // cmovns r26, qword ptr [r27+rcx*8+0x4ddea61c] IID436 - __ cmovq(Assembler::Condition::parity, r10, Address(r22, r19, (Address::ScaleFactor)1, +0x2a126966)); // cmovp r10, qword ptr [r22+r19*2+0x2a126966] IID437 - __ cmovq(Assembler::Condition::noParity, r12, Address(r10, +0x3d7c59f)); // cmovnp r12, qword ptr [r10+0x3d7c59f] IID438 - __ cmovq(Assembler::Condition::less, r10, Address(r8, r8, (Address::ScaleFactor)3, -0xe61862d)); // cmovl r10, qword ptr [r8+r8*8-0xe61862d] IID439 - __ cmovq(Assembler::Condition::greaterEqual, r23, Address(r29, -0x777ed96d)); // cmovge r23, qword ptr [r29-0x777ed96d] IID440 - __ cmovq(Assembler::Condition::lessEqual, rcx, Address(rbx, r19, (Address::ScaleFactor)1, +0x53c601cb)); // cmovle rcx, qword ptr [rbx+r19*2+0x53c601cb] IID441 - __ cmovq(Assembler::Condition::greater, r14, Address(r17, rbx, (Address::ScaleFactor)0, -0x768bf073)); // cmovg r14, qword ptr [r17+rbx*1-0x768bf073] IID442 - __ call(r29); // call r29 IID443 - __ divq(r10); // div r10 IID444 - __ idivq(r19); // idiv r19 IID445 - __ imulq(r15); // imul r15 IID446 - __ mulq(r27); // mul r27 IID447 - __ negq(r20); // neg r20 IID448 - __ notq(r10); // not r10 IID449 - __ rolq(r16); // rol r16, cl IID450 - __ rorq(r27); // ror r27, cl IID451 - __ sarq(r9); // sar r9, cl IID452 - __ salq(r13); // sal r13, cl IID453 - __ shlq(r14); // shl r14, cl IID454 - __ shrq(r18); // shr r18, cl IID455 - __ incrementq(r28); // inc r28 IID456 - __ decrementq(r28); // dec r28 IID457 - __ pushp(r22); // pushp r22 IID458 - __ popp(r8); // popp r8 IID459 - __ call(Address(r12, +0x64cc424e)); // call qword ptr [r12+0x64cc424e] IID460 - __ mulq(Address(r26, r29, (Address::ScaleFactor)0, -0x466f085f)); // mul qword ptr [r26+r29*1-0x466f085f] IID461 - __ negq(Address(r21, r24, (Address::ScaleFactor)0, +0x2037df0b)); // neg qword ptr [r21+r24*1+0x2037df0b] IID462 - __ sarq(Address(r12, r31, (Address::ScaleFactor)3, -0x57d225aa)); // sar qword ptr [r12+r31*8-0x57d225aa], cl IID463 - __ salq(Address(r20, -0x1ea02f90)); // sal qword ptr [r20-0x1ea02f90], cl IID464 - __ shrq(Address(r13, r20, (Address::ScaleFactor)3, +0x171081f2)); // shr qword ptr [r13+r20*8+0x171081f2], cl IID465 - __ incrementq(Address(r31, +0x13a808db)); // inc qword ptr [r31+0x13a808db] IID466 - __ decrementq(Address(r19, -0x180d3ea1)); // dec qword ptr [r19-0x180d3ea1] IID467 - __ imulq(r17, Address(r16, -0x2af2fd58), 4096); // imul r17, qword ptr [r16-0x2af2fd58], 4096 IID468 - __ imulq(r28, r25, 16); // imul r28, r25, 16 IID469 - __ shldq(r27, r13, 16); // shld r27, r13, 16 IID470 - __ shrdq(r8, r10, 16); // shrd r8, r10, 16 IID471 - __ pop2(r14, r8); // {load}pop2 r8, r14 IID472 - __ pop2p(r18, rbx); // {load}pop2p rbx, r18 IID473 - __ push2(r23, r19); // {load}push2 r19, r23 IID474 - __ push2p(r12, rbx); // {load}push2p rbx, r12 IID475 - __ movzbq(r9, Address(r14, r23, (Address::ScaleFactor)3, -0x428d2646)); // movzx r9, byte ptr [r14+r23*8-0x428d2646] IID476 - __ movzwq(r28, Address(r9, rcx, (Address::ScaleFactor)2, -0x72611661)); // movzx r28, word ptr [r9+rcx*4-0x72611661] IID477 - __ movsbq(rbx, Address(r24, r21, (Address::ScaleFactor)2, +0x3a6be990)); // movsx rbx, byte ptr [r24+r21*4+0x3a6be990] IID478 - __ movswq(r16, Address(r22, r10, (Address::ScaleFactor)0, +0x7ef8bdd)); // movsx r16, word ptr [r22+r10*1+0x7ef8bdd] IID479 - __ movzbq(r28, r14); // movzx r28, r14b IID480 - __ movzwq(r13, r28); // movzx r13, r28w IID481 - __ movsbq(r11, rdx); // movsx r11, dl IID482 - __ movswq(r12, r26); // movsx r12, r26w IID483 - __ cmpxchgq(r20, Address(r10, -0xbd2a8da)); // cmpxchg qword ptr [r10-0xbd2a8da], r20 IID484 - __ eidivq(r15, false); // {EVEX}idiv r15 IID485 - __ eidivq(r23, true); // {NF}idiv r23 IID486 - __ edivq(r14, false); // {EVEX}div r14 IID487 - __ edivq(r14, true); // {NF}div r14 IID488 - __ eimulq(r15, false); // {EVEX}imul r15 IID489 - __ eimulq(r20, true); // {NF}imul r20 IID490 - __ emulq(rcx, false); // {EVEX}mul rcx IID491 - __ emulq(r21, true); // {NF}mul r21 IID492 - __ emulq(Address(r16, r10, (Address::ScaleFactor)3, +0x5f66ac1e), false); // {EVEX}mul qword ptr [r16+r10*8+0x5f66ac1e] IID493 - __ emulq(Address(r21, r22, (Address::ScaleFactor)3, -0xbbc807d), true); // {NF}mul qword ptr [r21+r22*8-0xbbc807d] IID494 - __ eimulq(r22, r26, false); // {EVEX}imul r22, r26 IID495 - __ eimulq(r25, r21, true); // {NF}imul r25, r21 IID496 - __ elzcntq(r20, r13, false); // {EVEX}lzcnt r20, r13 IID497 - __ elzcntq(r25, r19, true); // {NF}lzcnt r25, r19 IID498 - __ enegq(r21, r30, false); // {EVEX}neg r21, r30 IID499 - __ enegq(r29, r11, true); // {NF}neg r29, r11 IID500 - __ enotq(r22, r8); // {EVEX}not r22, r8 IID501 - __ epopcntq(r12, r19, false); // {EVEX}popcnt r12, r19 IID502 - __ epopcntq(r29, r23, true); // {NF}popcnt r29, r23 IID503 - __ erolq(r28, r24, false); // {EVEX}rol r28, r24, cl IID504 - __ erolq(rdx, r20, true); // {NF}rol rdx, r20, cl IID505 - __ erorq(rbx, r30, false); // {EVEX}ror rbx, r30, cl IID506 - __ erorq(r10, r15, true); // {NF}ror r10, r15, cl IID507 - __ esalq(r17, r13, false); // {EVEX}sal r17, r13, cl IID508 - __ esalq(r21, r24, true); // {NF}sal r21, r24, cl IID509 - __ esarq(r31, r12, false); // {EVEX}sar r31, r12, cl IID510 - __ esarq(rdx, r24, true); // {NF}sar rdx, r24, cl IID511 - __ edecq(r21, r24, false); // {EVEX}dec r21, r24 IID512 - __ edecq(r15, r31, true); // {NF}dec r15, r31 IID513 - __ eincq(r10, rbx, false); // {EVEX}inc r10, rbx IID514 - __ eincq(r18, r8, true); // {NF}inc r18, r8 IID515 - __ eshlq(r10, r26, false); // {EVEX}shl r10, r26, cl IID516 - __ eshlq(r28, r14, true); // {NF}shl r28, r14, cl IID517 - __ eshrq(r10, r19, false); // {EVEX}shr r10, r19, cl IID518 - __ eshrq(r28, r21, true); // {NF}shr r28, r21, cl IID519 - __ etzcntq(r21, r22, false); // {EVEX}tzcnt r21, r22 IID520 - __ etzcntq(r16, r23, true); // {NF}tzcnt r16, r23 IID521 - __ eimulq(r11, Address(r18, r9, (Address::ScaleFactor)2, -0x132285a1), false); // {EVEX}imul r11, qword ptr [r18+r9*4-0x132285a1] IID522 - __ eimulq(r13, Address(r24, r15, (Address::ScaleFactor)3, +0x48f50ca0), true); // {NF}imul r13, qword ptr [r24+r15*8+0x48f50ca0] IID523 - __ elzcntq(r9, Address(r13, +0x2115cf0e), false); // {EVEX}lzcnt r9, qword ptr [r13+0x2115cf0e] IID524 - __ elzcntq(r27, Address(r30, +0x49cabbb), true); // {NF}lzcnt r27, qword ptr [r30+0x49cabbb] IID525 - __ enegq(r21, Address(r13, r31, (Address::ScaleFactor)2, +0x50a8f4d2), false); // {EVEX}neg r21, qword ptr [r13+r31*4+0x50a8f4d2] IID526 - __ enegq(r22, Address(r18, r20, (Address::ScaleFactor)1, -0x5da0584c), true); // {NF}neg r22, qword ptr [r18+r20*2-0x5da0584c] IID527 - __ epopcntq(r14, Address(rbx, r22, (Address::ScaleFactor)2, -0x606349d1), false); // {EVEX}popcnt r14, qword ptr [rbx+r22*4-0x606349d1] IID528 - __ epopcntq(r26, Address(r23, r22, (Address::ScaleFactor)3, -0x72c66c23), true); // {NF}popcnt r26, qword ptr [r23+r22*8-0x72c66c23] IID529 - __ esalq(r26, Address(r9, +0x334aba09), false); // {EVEX}sal r26, qword ptr [r9+0x334aba09], cl IID530 - __ esalq(r9, Address(r9, r30, (Address::ScaleFactor)3, -0x219a6102), true); // {NF}sal r9, qword ptr [r9+r30*8-0x219a6102], cl IID531 - __ esarq(r25, Address(r20, -0x2131bab1), false); // {EVEX}sar r25, qword ptr [r20-0x2131bab1], cl IID532 - __ esarq(r16, Address(r28, r16, (Address::ScaleFactor)1, +0x48c483b9), true); // {NF}sar r16, qword ptr [r28+r16*2+0x48c483b9], cl IID533 - __ edecq(r30, Address(r9, r16, (Address::ScaleFactor)0, -0x88ce84f), false); // {EVEX}dec r30, qword ptr [r9+r16*1-0x88ce84f] IID534 - __ edecq(r11, Address(r30, r29, (Address::ScaleFactor)2, +0x3eeb8fd0), true); // {NF}dec r11, qword ptr [r30+r29*4+0x3eeb8fd0] IID535 - __ eincq(r26, Address(r29, r10, (Address::ScaleFactor)3, +0x3ef4822e), false); // {EVEX}inc r26, qword ptr [r29+r10*8+0x3ef4822e] IID536 - __ eincq(r29, Address(r19, r20, (Address::ScaleFactor)2, -0x3f0f3db9), true); // {NF}inc r29, qword ptr [r19+r20*4-0x3f0f3db9] IID537 - __ eshrq(r8, Address(r30, r20, (Address::ScaleFactor)0, +0x15b56a17), false); // {EVEX}shr r8, qword ptr [r30+r20*1+0x15b56a17], cl IID538 - __ eshrq(r26, Address(r11, -0x2de86561), true); // {NF}shr r26, qword ptr [r11-0x2de86561], cl IID539 - __ etzcntq(r11, Address(rcx, r30, (Address::ScaleFactor)1, -0x32ffb1c2), false); // {EVEX}tzcnt r11, qword ptr [rcx+r30*2-0x32ffb1c2] IID540 - __ etzcntq(r23, Address(r9, r12, (Address::ScaleFactor)1, -0x54823e69), true); // {NF}tzcnt r23, qword ptr [r9+r12*2-0x54823e69] IID541 - __ eaddq(r20, Address(r13, rcx, (Address::ScaleFactor)3, -0x46116c0d), r15, false); // {EVEX}add r20, qword ptr [r13+rcx*8-0x46116c0d], r15 IID542 - __ eaddq(r13, Address(r9, r23, (Address::ScaleFactor)1, -0x286c7605), r16, true); // {NF}add r13, qword ptr [r9+r23*2-0x286c7605], r16 IID543 - __ eandq(r21, Address(r30, r17, (Address::ScaleFactor)0, +0xf4e30b2), r29, false); // {EVEX}and r21, qword ptr [r30+r17*1+0xf4e30b2], r29 IID544 - __ eandq(r30, Address(r17, r31, (Address::ScaleFactor)0, +0x3ab9dec4), r17, true); // {NF}and r30, qword ptr [r17+r31*1+0x3ab9dec4], r17 IID545 - __ eorq(r10, Address(r27, r30, (Address::ScaleFactor)1, -0x197f1266), r28, false); // {EVEX}or r10, qword ptr [r27+r30*2-0x197f1266], r28 IID546 - __ eorq(r9, Address(r29, r30, (Address::ScaleFactor)0, -0x24ea9b08), r11, true); // {NF}or r9, qword ptr [r29+r30*1-0x24ea9b08], r11 IID547 - __ esubq(r15, Address(r14, -0x4f44bf90), r16, false); // {EVEX}sub r15, qword ptr [r14-0x4f44bf90], r16 IID548 - __ esubq(rcx, Address(r21, r18, (Address::ScaleFactor)1, -0x11d0ac8f), r28, true); // {NF}sub rcx, qword ptr [r21+r18*2-0x11d0ac8f], r28 IID549 - __ exorq(r19, Address(r19, r18, (Address::ScaleFactor)0, -0xa5e55ec), r8, false); // {EVEX}xor r19, qword ptr [r19+r18*1-0xa5e55ec], r8 IID550 - __ exorq(r28, Address(r17, r28, (Address::ScaleFactor)1, -0x6eb42fe0), r16, true); // {NF}xor r28, qword ptr [r17+r28*2-0x6eb42fe0], r16 IID551 - __ eaddq(r17, Address(r18, -0x60ab1105), 16777216, false); // {EVEX}add r17, qword ptr [r18-0x60ab1105], 16777216 IID552 - __ eaddq(r25, Address(r19, r25, (Address::ScaleFactor)0, +0x122444d9), 65536, true); // {NF}add r25, qword ptr [r19+r25*1+0x122444d9], 65536 IID553 - __ eandq(r30, Address(r9, r28, (Address::ScaleFactor)1, -0x25b00cf3), 4096, false); // {EVEX}and r30, qword ptr [r9+r28*2-0x25b00cf3], 4096 IID554 - __ eandq(r9, Address(r22, rbx, (Address::ScaleFactor)1, -0x7e465026), 268435456, true); // {NF}and r9, qword ptr [r22+rbx*2-0x7e465026], 268435456 IID555 - __ eimulq(r12, Address(r25, r25, (Address::ScaleFactor)1, -0x432d68cc), 1, false); // {EVEX}imul r12, qword ptr [r25+r25*2-0x432d68cc], 1 IID556 - __ eimulq(r15, Address(r17, r31, (Address::ScaleFactor)3, -0x2b97565e), 16, true); // {NF}imul r15, qword ptr [r17+r31*8-0x2b97565e], 16 IID557 - __ eorq(r28, Address(rdx, r31, (Address::ScaleFactor)0, +0x3f1363b1), 256, false); // {EVEX}or r28, qword ptr [rdx+r31*1+0x3f1363b1], 256 IID558 - __ eorq(r16, Address(r12, r23, (Address::ScaleFactor)3, -0x1785863c), 16777216, true); // {NF}or r16, qword ptr [r12+r23*8-0x1785863c], 16777216 IID559 - __ esalq(r8, Address(r14, r24, (Address::ScaleFactor)2, -0x714290a5), 2, false); // {EVEX}sal r8, qword ptr [r14+r24*4-0x714290a5], 2 IID560 - __ esalq(r8, Address(r15, r14, (Address::ScaleFactor)2, +0x21f13243), 16, true); // {NF}sal r8, qword ptr [r15+r14*4+0x21f13243], 16 IID561 - __ esarq(r10, Address(r13, r29, (Address::ScaleFactor)0, +0x7d04cb72), 2, false); // {EVEX}sar r10, qword ptr [r13+r29*1+0x7d04cb72], 2 IID562 - __ esarq(r11, Address(r21, r31, (Address::ScaleFactor)3, -0x2176b4dc), 8, true); // {NF}sar r11, qword ptr [r21+r31*8-0x2176b4dc], 8 IID563 - __ eshrq(rcx, Address(r16, r12, (Address::ScaleFactor)1, +0x260c9a38), 4, false); // {EVEX}shr rcx, qword ptr [r16+r12*2+0x260c9a38], 4 IID564 - __ eshrq(r22, Address(r26, r9, (Address::ScaleFactor)0, -0x5e56bb62), 8, true); // {NF}shr r22, qword ptr [r26+r9*1-0x5e56bb62], 8 IID565 - __ esubq(r31, Address(rbx, r28, (Address::ScaleFactor)1, +0x2b00bb10), 1, false); // {EVEX}sub r31, qword ptr [rbx+r28*2+0x2b00bb10], 1 IID566 - __ esubq(r21, Address(r31, -0x6c10f4ad), 4096, true); // {NF}sub r21, qword ptr [r31-0x6c10f4ad], 4096 IID567 - __ exorq(r11, Address(r23, r30, (Address::ScaleFactor)1, +0x51a6026b), 65536, false); // {EVEX}xor r11, qword ptr [r23+r30*2+0x51a6026b], 65536 IID568 - __ exorq(r14, Address(r27, r10, (Address::ScaleFactor)2, -0x34ad9bab), 16, true); // {NF}xor r14, qword ptr [r27+r10*4-0x34ad9bab], 16 IID569 - __ eaddq(r20, r23, 16777216, false); // {EVEX}add r20, r23, 16777216 IID570 - __ eaddq(r9, r21, 4096, true); // {NF}add r9, r21, 4096 IID571 - __ eandq(r20, rdx, 16, false); // {EVEX}and r20, rdx, 16 IID572 - __ eandq(r14, r19, 16, true); // {NF}and r14, r19, 16 IID573 - __ eimulq(r27, r17, 16, false); // {EVEX}imul r27, r17, 16 IID574 - __ eimulq(r30, r13, 256, true); // {NF}imul r30, r13, 256 IID575 - __ eorq(r19, r15, 16777216, false); // {EVEX}or r19, r15, 16777216 IID576 - __ eorq(r16, r28, 268435456, true); // {NF}or r16, r28, 268435456 IID577 - __ erclq(rbx, r24, 2); // {EVEX}rcl rbx, r24, 2 IID578 - __ erolq(r15, r20, 16, false); // {EVEX}rol r15, r20, 16 IID579 - __ erolq(r11, rcx, 16, true); // {NF}rol r11, rcx, 16 IID580 - __ erorq(r13, r26, 16, false); // {EVEX}ror r13, r26, 16 IID581 - __ erorq(r19, r20, 4, true); // {NF}ror r19, r20, 4 IID582 - __ esalq(r19, r28, 16, false); // {EVEX}sal r19, r28, 16 IID583 - __ esalq(r25, r18, 4, true); // {NF}sal r25, r18, 4 IID584 - __ esarq(r10, r27, 4, false); // {EVEX}sar r10, r27, 4 IID585 - __ esarq(rdx, r22, 8, true); // {NF}sar rdx, r22, 8 IID586 - __ eshlq(r28, r15, 1, false); // {EVEX}shl r28, r15, 1 IID587 - __ eshlq(rbx, r12, 4, true); // {NF}shl rbx, r12, 4 IID588 - __ eshrq(r26, r11, 1, false); // {EVEX}shr r26, r11, 1 IID589 - __ eshrq(rdx, r31, 8, true); // {NF}shr rdx, r31, 8 IID590 - __ esubq(r21, rbx, 1048576, false); // {EVEX}sub r21, rbx, 1048576 IID591 - __ esubq(r25, r28, 65536, true); // {NF}sub r25, r28, 65536 IID592 - __ exorq(r22, r14, 1, false); // {EVEX}xor r22, r14, 1 IID593 - __ exorq(r11, r30, 1048576, true); // {NF}xor r11, r30, 1048576 IID594 - __ eorq_imm32(r20, r19, 1048576, false); // {EVEX}or r20, r19, 1048576 IID595 - __ eorq_imm32(r25, r13, 268435456, false); // {EVEX}or r25, r13, 268435456 IID596 - __ esubq_imm32(r25, r25, 268435456, false); // {EVEX}sub r25, r25, 268435456 IID597 - __ esubq_imm32(r18, r11, 4194304, true); // {NF}sub r18, r11, 4194304 IID598 - __ eaddq(r10, r18, Address(r20, +0x756f453), false); // {EVEX}add r10, r18, qword ptr [r20+0x756f453] IID599 - __ eaddq(rbx, r27, Address(r22, r21, (Address::ScaleFactor)0, -0x25abeab7), true); // {NF}add rbx, r27, qword ptr [r22+r21*1-0x25abeab7] IID600 - __ eandq(rdx, r31, Address(r9, r20, (Address::ScaleFactor)3, -0x4cfe39c), false); // {EVEX}and rdx, r31, qword ptr [r9+r20*8-0x4cfe39c] IID601 - __ eandq(r16, r25, Address(r14, r27, (Address::ScaleFactor)0, +0x7c6654d9), true); // {NF}and r16, r25, qword ptr [r14+r27*1+0x7c6654d9] IID602 - __ eorq(r29, rcx, Address(r15, r23, (Address::ScaleFactor)0, +0x45b7f72d), false); // {EVEX}or r29, rcx, qword ptr [r15+r23*1+0x45b7f72d] IID603 - __ eorq(r19, r17, Address(r13, r22, (Address::ScaleFactor)1, -0x750c1996), true); // {NF}or r19, r17, qword ptr [r13+r22*2-0x750c1996] IID604 - __ eimulq(r13, r8, Address(r31, r23, (Address::ScaleFactor)1, -0x2211b6b2), false); // {EVEX}imul r13, r8, qword ptr [r31+r23*2-0x2211b6b2] IID605 - __ eimulq(r11, r28, Address(r13, r11, (Address::ScaleFactor)3, +0x5c0013ab), true); // {NF}imul r11, r28, qword ptr [r13+r11*8+0x5c0013ab] IID606 - __ esubq(rdx, r18, Address(r18, rcx, (Address::ScaleFactor)0, +0x59557e71), false); // {EVEX}sub rdx, r18, qword ptr [r18+rcx*1+0x59557e71] IID607 - __ esubq(r27, r11, Address(r22, -0x28469649), true); // {NF}sub r27, r11, qword ptr [r22-0x28469649] IID608 - __ exorq(r10, r9, Address(r24, +0x49691d54), false); // {EVEX}xor r10, r9, qword ptr [r24+0x49691d54] IID609 - __ exorq(r24, r12, Address(r19, +0x22d529aa), true); // {NF}xor r24, r12, qword ptr [r19+0x22d529aa] IID610 - __ eaddq(r20, r9, r10, false); // {load}{EVEX}add r20, r9, r10 IID611 - __ eaddq(r18, r17, r26, true); // {load}{NF}add r18, r17, r26 IID612 - __ eadcxq(r21, r16, r19); // {load}{EVEX}adcx r21, r16, r19 IID613 - __ eadoxq(rbx, r14, r27); // {load}{EVEX}adox rbx, r14, r27 IID614 - __ eandq(r9, r12, r22, false); // {load}{EVEX}and r9, r12, r22 IID615 - __ eandq(r17, r25, r10, true); // {load}{NF}and r17, r25, r10 IID616 - __ eimulq(r12, r15, r14, false); // {load}{EVEX}imul r12, r15, r14 IID617 - __ eimulq(r29, r18, r16, true); // {load}{NF}imul r29, r18, r16 IID618 - __ eorq(r11, r9, r10, false); // {load}{EVEX}or r11, r9, r10 IID619 - __ eorq(r25, r13, r16, true); // {load}{NF}or r25, r13, r16 IID620 - __ esubq(r11, r21, r25, false); // {load}{EVEX}sub r11, r21, r25 IID621 - __ esubq(rdx, r20, rbx, true); // {load}{NF}sub rdx, r20, rbx IID622 - __ exorq(r25, r21, r26, false); // {load}{EVEX}xor r25, r21, r26 IID623 - __ exorq(r23, r27, r21, true); // {load}{NF}xor r23, r27, r21 IID624 - __ eshldq(r10, r12, r31, 2, false); // {EVEX}shld r10, r12, r31, 2 IID625 - __ eshldq(r23, r16, r29, 2, true); // {NF}shld r23, r16, r29, 2 IID626 - __ eshrdq(r19, r24, r23, 4, false); // {EVEX}shrd r19, r24, r23, 4 IID627 - __ eshrdq(r21, r15, r25, 4, true); // {NF}shrd r21, r15, r25, 4 IID628 - __ ecmovq (Assembler::Condition::overflow, r9, r29, rdx); // cmovo r9, r29, rdx IID629 - __ ecmovq (Assembler::Condition::noOverflow, r11, r25, r19); // cmovno r11, r25, r19 IID630 - __ ecmovq (Assembler::Condition::below, r10, r16, r17); // cmovb r10, r16, r17 IID631 - __ ecmovq (Assembler::Condition::aboveEqual, r8, r23, r31); // cmovae r8, r23, r31 IID632 - __ ecmovq (Assembler::Condition::zero, r9, r31, rbx); // cmovz r9, r31, rbx IID633 - __ ecmovq (Assembler::Condition::notZero, r16, r29, r9); // cmovnz r16, r29, r9 IID634 - __ ecmovq (Assembler::Condition::belowEqual, r24, r10, r9); // cmovbe r24, r10, r9 IID635 - __ ecmovq (Assembler::Condition::above, r22, r28, r26); // cmova r22, r28, r26 IID636 - __ ecmovq (Assembler::Condition::negative, r18, r25, r20); // cmovs r18, r25, r20 IID637 - __ ecmovq (Assembler::Condition::positive, r16, r21, rbx); // cmovns r16, r21, rbx IID638 - __ ecmovq (Assembler::Condition::parity, r28, r22, r19); // cmovp r28, r22, r19 IID639 - __ ecmovq (Assembler::Condition::noParity, r13, r15, rdx); // cmovnp r13, r15, rdx IID640 - __ ecmovq (Assembler::Condition::less, r8, r22, r14); // cmovl r8, r22, r14 IID641 - __ ecmovq (Assembler::Condition::greaterEqual, r12, r24, r14); // cmovge r12, r24, r14 IID642 - __ ecmovq (Assembler::Condition::lessEqual, r24, r13, r21); // cmovle r24, r13, r21 IID643 - __ ecmovq (Assembler::Condition::greater, rbx, rbx, r27); // cmovg rbx, rbx, r27 IID644 - __ ecmovq (Assembler::Condition::overflow, r14, r17, Address(r24, r27, (Address::ScaleFactor)3, +0x9d508f0)); // cmovo r14, r17, qword ptr [r24+r27*8+0x9d508f0] IID645 - __ ecmovq (Assembler::Condition::noOverflow, r13, r15, Address(r31, r21, (Address::ScaleFactor)2, +0x6ef2c74a)); // cmovno r13, r15, qword ptr [r31+r21*4+0x6ef2c74a] IID646 - __ ecmovq (Assembler::Condition::below, r13, r27, Address(r31, r25, (Address::ScaleFactor)1, +0x734fe9ab)); // cmovb r13, r27, qword ptr [r31+r25*2+0x734fe9ab] IID647 - __ ecmovq (Assembler::Condition::aboveEqual, r15, r22, Address(r14, r29, (Address::ScaleFactor)2, -0x67d8bdfb)); // cmovae r15, r22, qword ptr [r14+r29*4-0x67d8bdfb] IID648 - __ ecmovq (Assembler::Condition::zero, r30, r23, Address(r15, r28, (Address::ScaleFactor)1, -0x2686219)); // cmovz r30, r23, qword ptr [r15+r28*2-0x2686219] IID649 - __ ecmovq (Assembler::Condition::notZero, r12, r9, Address(r9, r25, (Address::ScaleFactor)3, +0x52aab6b)); // cmovnz r12, r9, qword ptr [r9+r25*8+0x52aab6b] IID650 - __ ecmovq (Assembler::Condition::belowEqual, r9, r25, Address(r8, r8, (Address::ScaleFactor)3, -0x1e42bd95)); // cmovbe r9, r25, qword ptr [r8+r8*8-0x1e42bd95] IID651 - __ ecmovq (Assembler::Condition::above, rcx, r20, Address(r27, rbx, (Address::ScaleFactor)2, +0x46823c58)); // cmova rcx, r20, qword ptr [r27+rbx*4+0x46823c58] IID652 - __ ecmovq (Assembler::Condition::negative, rbx, r12, Address(r21, -0x635b8c8)); // cmovs rbx, r12, qword ptr [r21-0x635b8c8] IID653 - __ ecmovq (Assembler::Condition::positive, r23, rbx, Address(r27, r26, (Address::ScaleFactor)3, +0x922bcc0)); // cmovns r23, rbx, qword ptr [r27+r26*8+0x922bcc0] IID654 - __ ecmovq (Assembler::Condition::parity, r25, r9, Address(r23, +0xd2a14ec)); // cmovp r25, r9, qword ptr [r23+0xd2a14ec] IID655 - __ ecmovq (Assembler::Condition::noParity, r11, r19, Address(r11, -0xfb95a9d)); // cmovnp r11, r19, qword ptr [r11-0xfb95a9d] IID656 - __ ecmovq (Assembler::Condition::less, r13, r18, Address(r28, r19, (Address::ScaleFactor)0, +0x716b9b7e)); // cmovl r13, r18, qword ptr [r28+r19*1+0x716b9b7e] IID657 - __ ecmovq (Assembler::Condition::greaterEqual, r21, r16, Address(rcx, r29, (Address::ScaleFactor)0, -0x5af0441e)); // cmovge r21, r16, qword ptr [rcx+r29*1-0x5af0441e] IID658 - __ ecmovq (Assembler::Condition::lessEqual, r12, r31, Address(r20, r26, (Address::ScaleFactor)0, +0xe0b7fb1)); // cmovle r12, r31, qword ptr [r20+r26*1+0xe0b7fb1] IID659 - __ ecmovq (Assembler::Condition::greater, r15, r24, Address(r30, +0x2d3b7b4f)); // cmovg r15, r24, qword ptr [r30+0x2d3b7b4f] IID660 + __ adcq(r27, rcx); // {load}adc r27, rcx IID378 + __ cmpq(r22, r15); // {load}cmp r22, r15 IID379 + __ imulq(r31, r30); // {load}imul r31, r30 IID380 + __ popcntq(r19, r19); // {load}popcnt r19, r19 IID381 + __ sbbq(r26, r21); // {load}sbb r26, r21 IID382 + __ subq(r14, r26); // {load}sub r14, r26 IID383 + __ tzcntq(r20, r15); // {load}tzcnt r20, r15 IID384 + __ lzcntq(r12, r13); // {load}lzcnt r12, r13 IID385 + __ addq(r23, r28); // {load}add r23, r28 IID386 + __ andq(r20, r20); // {load}and r20, r20 IID387 + __ orq(r24, r11); // {load}or r24, r11 IID388 + __ xorq(r10, r15); // {load}xor r10, r15 IID389 + __ movq(r19, r20); // {load}mov r19, r20 IID390 + __ bsfq(r23, r15); // {load}bsf r23, r15 IID391 + __ bsrq(r26, r19); // {load}bsr r26, r19 IID392 + __ btq(r24, r23); // {load}bt r24, r23 IID393 + __ xchgq(r28, r11); // {load}xchg r28, r11 IID394 + __ testq(r13, r13); // {load}test r13, r13 IID395 + __ addq(Address(r31, r23, (Address::ScaleFactor)3, +0x59da0437), rdx); // add qword ptr [r31+r23*8+0x59da0437], rdx IID396 + __ andq(Address(r21, r20, (Address::ScaleFactor)3, +0x6fd0d557), r27); // and qword ptr [r21+r20*8+0x6fd0d557], r27 IID397 + __ cmpq(Address(r21, +0x23ef6744), r11); // cmp qword ptr [r21+0x23ef6744], r11 IID398 + __ orq(Address(r10, rcx, (Address::ScaleFactor)3, +0x7e8544ab), rcx); // or qword ptr [r10+rcx*8+0x7e8544ab], rcx IID399 + __ xorq(Address(rcx, r24, (Address::ScaleFactor)3, -0x79ca4889), rbx); // xor qword ptr [rcx+r24*8-0x79ca4889], rbx IID400 + __ subq(Address(r27, r31, (Address::ScaleFactor)0, +0x11f85f9a), r27); // sub qword ptr [r27+r31*1+0x11f85f9a], r27 IID401 + __ movq(Address(r20, r16, (Address::ScaleFactor)3, +0x72158dda), r17); // mov qword ptr [r20+r16*8+0x72158dda], r17 IID402 + __ xaddq(Address(r29, r9, (Address::ScaleFactor)2, +0x6e8febd1), r12); // xadd qword ptr [r29+r9*4+0x6e8febd1], r12 IID403 + __ andq(Address(r15, -0x47c94ecd), 268435456); // and qword ptr [r15-0x47c94ecd], 268435456 IID404 + __ addq(Address(r23, r19, (Address::ScaleFactor)1, +0x32bfde3f), 256); // add qword ptr [r23+r19*2+0x32bfde3f], 256 IID405 + __ cmpq(Address(r15, r11, (Address::ScaleFactor)3, +0x548e7560), 4096); // cmp qword ptr [r15+r11*8+0x548e7560], 4096 IID406 + __ sarq(Address(r20, r14, (Address::ScaleFactor)1, +0x1b43fc34), 2); // sar qword ptr [r20+r14*2+0x1b43fc34], 2 IID407 + __ salq(Address(r26, r21, (Address::ScaleFactor)0, -0x3bae50c3), 8); // sal qword ptr [r26+r21*1-0x3bae50c3], 8 IID408 + __ sbbq(Address(r22, r10, (Address::ScaleFactor)3, +0x47e1403), 65536); // sbb qword ptr [r22+r10*8+0x47e1403], 65536 IID409 + __ shrq(Address(rcx, rdx, (Address::ScaleFactor)2, +0x7ea3924d), 16); // shr qword ptr [rcx+rdx*4+0x7ea3924d], 16 IID410 + __ subq(Address(rcx, r26, (Address::ScaleFactor)3, -0x356ea53e), 16); // sub qword ptr [rcx+r26*8-0x356ea53e], 16 IID411 + __ xorq(Address(r30, r26, (Address::ScaleFactor)2, +0x78a12f5c), 16); // xor qword ptr [r30+r26*4+0x78a12f5c], 16 IID412 + __ orq(Address(r11, r10, (Address::ScaleFactor)1, +0x3713b5b5), 268435456); // or qword ptr [r11+r10*2+0x3713b5b5], 268435456 IID413 + __ movq(Address(r30, r30, (Address::ScaleFactor)3, +0x2541a10), 65536); // mov qword ptr [r30+r30*8+0x2541a10], 65536 IID414 + __ testq(Address(r16, r15, (Address::ScaleFactor)3, +0x558e3251), -16); // test qword ptr [r16+r15*8+0x558e3251], -16 IID415 + __ addq(r27, Address(r8, r10, (Address::ScaleFactor)2, +0x635f732d)); // add r27, qword ptr [r8+r10*4+0x635f732d] IID416 + __ andq(r21, Address(r12, r31, (Address::ScaleFactor)0, -0x75e8c4a0)); // and r21, qword ptr [r12+r31*1-0x75e8c4a0] IID417 + __ cmpq(r18, Address(r19, r16, (Address::ScaleFactor)2, -0x120ae81e)); // cmp r18, qword ptr [r19+r16*4-0x120ae81e] IID418 + __ lzcntq(rbx, Address(r31, r30, (Address::ScaleFactor)0, +0x1ec3265d)); // lzcnt rbx, qword ptr [r31+r30*1+0x1ec3265d] IID419 + __ orq(r16, Address(rdx, r26, (Address::ScaleFactor)0, +0x3586831b)); // or r16, qword ptr [rdx+r26*1+0x3586831b] IID420 + __ adcq(r12, Address(r18, -0x3c3e9f7a)); // adc r12, qword ptr [r18-0x3c3e9f7a] IID421 + __ imulq(rcx, Address(r8, r21, (Address::ScaleFactor)3, +0x6b1515ab)); // imul rcx, qword ptr [r8+r21*8+0x6b1515ab] IID422 + __ popcntq(r29, Address(rcx, r23, (Address::ScaleFactor)2, +0x4ff06c4d)); // popcnt r29, qword ptr [rcx+r23*4+0x4ff06c4d] IID423 + __ sbbq(r26, Address(r24, r10, (Address::ScaleFactor)1, -0x75d9a189)); // sbb r26, qword ptr [r24+r10*2-0x75d9a189] IID424 + __ subq(r17, Address(rbx, rbx, (Address::ScaleFactor)0, +0x4033d59c)); // sub r17, qword ptr [rbx+rbx*1+0x4033d59c] IID425 + __ tzcntq(r18, Address(r22, r12, (Address::ScaleFactor)3, -0x3893347d)); // tzcnt r18, qword ptr [r22+r12*8-0x3893347d] IID426 + __ xorq(r12, Address(r20, r23, (Address::ScaleFactor)3, +0x4b311560)); // xor r12, qword ptr [r20+r23*8+0x4b311560] IID427 + __ movq(r29, Address(r10, r28, (Address::ScaleFactor)2, +0x5c3a2657)); // mov r29, qword ptr [r10+r28*4+0x5c3a2657] IID428 + __ leaq(r22, Address(r13, r25, (Address::ScaleFactor)3, +0x1a3d6f3f)); // lea r22, qword ptr [r13+r25*8+0x1a3d6f3f] IID429 + __ cvttsd2siq(r25, Address(r17, r24, (Address::ScaleFactor)3, -0x35addbd8)); // cvttsd2si r25, qword ptr [r17+r24*8-0x35addbd8] IID430 + __ xchgq(r18, Address(r25, +0x632184c3)); // xchg r18, qword ptr [r25+0x632184c3] IID431 + __ testq(r29, Address(r18, r13, (Address::ScaleFactor)1, -0x5039fd8a)); // test r29, qword ptr [r18+r13*2-0x5039fd8a] IID432 + __ addq(r20, 4096); // add r20, 4096 IID433 + __ andq(r9, 16); // and r9, 16 IID434 + __ adcq(rdx, 256); // adc rdx, 256 IID435 + __ cmpq(r22, 16777216); // cmp r22, 16777216 IID436 + __ rclq(r17, 1); // rcl r17, 1 IID437 + __ rcrq(r31, 1); // rcr r31, 1 IID438 + __ rolq(r27, 4); // rol r27, 4 IID439 + __ rorq(r28, 2); // ror r28, 2 IID440 + __ sarq(rcx, 16); // sar rcx, 16 IID441 + __ salq(r31, 8); // sal r31, 8 IID442 + __ sbbq(r27, 1048576); // sbb r27, 1048576 IID443 + __ shlq(r20, 16); // shl r20, 16 IID444 + __ shrq(r31, 8); // shr r31, 8 IID445 + __ subq(r27, 1048576); // sub r27, 1048576 IID446 + __ xorq(r22, 4096); // xor r22, 4096 IID447 + __ movq(r8, 4096); // mov r8, 4096 IID448 + __ mov64(r28, 1099511627776); // mov r28, 1099511627776 IID449 + __ btq(r13, 1); // bt r13, 1 IID450 + __ testq(r16, -1048576); // test r16, -1048576 IID451 + __ orq_imm32(r20, 262144); // or r20, 262144 IID452 + __ subq_imm32(r18, 1048576); // sub r18, 1048576 IID453 + __ cmovq(Assembler::Condition::overflow, rbx, Address(r29, r8, (Address::ScaleFactor)0, +0x1d022615)); // cmovo rbx, qword ptr [r29+r8*1+0x1d022615] IID454 + __ cmovq(Assembler::Condition::noOverflow, rdx, Address(r12, r28, (Address::ScaleFactor)1, -0x34c898e2)); // cmovno rdx, qword ptr [r12+r28*2-0x34c898e2] IID455 + __ cmovq(Assembler::Condition::below, r27, Address(r10, rcx, (Address::ScaleFactor)3, -0x1ef7abf1)); // cmovb r27, qword ptr [r10+rcx*8-0x1ef7abf1] IID456 + __ cmovq(Assembler::Condition::aboveEqual, r14, Address(r13, r29, (Address::ScaleFactor)2, -0x7c4c8369)); // cmovae r14, qword ptr [r13+r29*4-0x7c4c8369] IID457 + __ cmovq(Assembler::Condition::zero, r15, Address(r23, rcx, (Address::ScaleFactor)2, -0x6bd22ccf)); // cmovz r15, qword ptr [r23+rcx*4-0x6bd22ccf] IID458 + __ cmovq(Assembler::Condition::notZero, r24, Address(r15, r10, (Address::ScaleFactor)1, -0x7ffb3d09)); // cmovnz r24, qword ptr [r15+r10*2-0x7ffb3d09] IID459 + __ cmovq(Assembler::Condition::belowEqual, r23, Address(r11, +0x276a863b)); // cmovbe r23, qword ptr [r11+0x276a863b] IID460 + __ cmovq(Assembler::Condition::above, r28, Address(r29, +0x3fb4396e)); // cmova r28, qword ptr [r29+0x3fb4396e] IID461 + __ cmovq(Assembler::Condition::negative, r26, Address(r27, rcx, (Address::ScaleFactor)3, +0x4ddea61c)); // cmovs r26, qword ptr [r27+rcx*8+0x4ddea61c] IID462 + __ cmovq(Assembler::Condition::positive, r10, Address(r22, r19, (Address::ScaleFactor)1, +0x2a126966)); // cmovns r10, qword ptr [r22+r19*2+0x2a126966] IID463 + __ cmovq(Assembler::Condition::parity, r12, Address(r10, +0x3d7c59f)); // cmovp r12, qword ptr [r10+0x3d7c59f] IID464 + __ cmovq(Assembler::Condition::noParity, r10, Address(r8, r8, (Address::ScaleFactor)3, -0xe61862d)); // cmovnp r10, qword ptr [r8+r8*8-0xe61862d] IID465 + __ cmovq(Assembler::Condition::less, r23, Address(r29, -0x777ed96d)); // cmovl r23, qword ptr [r29-0x777ed96d] IID466 + __ cmovq(Assembler::Condition::greaterEqual, rcx, Address(rbx, r19, (Address::ScaleFactor)1, +0x53c601cb)); // cmovge rcx, qword ptr [rbx+r19*2+0x53c601cb] IID467 + __ cmovq(Assembler::Condition::lessEqual, r14, Address(r17, rbx, (Address::ScaleFactor)0, -0x768bf073)); // cmovle r14, qword ptr [r17+rbx*1-0x768bf073] IID468 + __ cmovq(Assembler::Condition::greater, r29, Address(r10, r19, (Address::ScaleFactor)1, +0x30c98d3c)); // cmovg r29, qword ptr [r10+r19*2+0x30c98d3c] IID469 + __ call(r10); // call r10 IID470 + __ divq(r16); // div r16 IID471 + __ idivq(r27); // idiv r27 IID472 + __ imulq(r9); // imul r9 IID473 + __ mulq(r13); // mul r13 IID474 + __ negq(r14); // neg r14 IID475 + __ notq(r18); // not r18 IID476 + __ rolq(r28); // rol r28, cl IID477 + __ rorq(r28); // ror r28, cl IID478 + __ sarq(r22); // sar r22, cl IID479 + __ salq(r8); // sal r8, cl IID480 + __ shlq(r12); // shl r12, cl IID481 + __ shrq(rbx); // shr rbx, cl IID482 + __ incrementq(rcx); // inc rcx IID483 + __ decrementq(r23); // dec r23 IID484 + __ pushp(rcx); // pushp rcx IID485 + __ popp(r26); // popp r26 IID486 + __ call(Address(r29, r10, (Address::ScaleFactor)0, +0x5655bc9f)); // call qword ptr [r29+r10*1+0x5655bc9f] IID487 + __ mulq(Address(rdx, r21, (Address::ScaleFactor)3, -0x6798a630)); // mul qword ptr [rdx+r21*8-0x6798a630] IID488 + __ negq(Address(r31, r24, (Address::ScaleFactor)0, -0x20071802)); // neg qword ptr [r31+r24*1-0x20071802] IID489 + __ sarq(Address(r21, rdx, (Address::ScaleFactor)2, -0x343cb9e5)); // sar qword ptr [r21+rdx*4-0x343cb9e5], cl IID490 + __ salq(Address(r20, r24, (Address::ScaleFactor)3, +0xa667574)); // sal qword ptr [r20+r24*8+0xa667574], cl IID491 + __ shrq(Address(r27, +0x76b77974)); // shr qword ptr [r27+0x76b77974], cl IID492 + __ incrementq(Address(r25, -0x534e8d31)); // inc qword ptr [r25-0x534e8d31] IID493 + __ decrementq(Address(r20, -0x180d3ea1)); // dec qword ptr [r20-0x180d3ea1] IID494 + __ imulq(r17, Address(r16, -0x2af2fd58), 4096); // imul r17, qword ptr [r16-0x2af2fd58], 4096 IID495 + __ imulq(r28, r25, 16); // imul r28, r25, 16 IID496 + __ shldq(r27, r13, 16); // shld r27, r13, 16 IID497 + __ shrdq(r8, r10, 16); // shrd r8, r10, 16 IID498 + __ pop2(r14, r8); // {load}pop2 r8, r14 IID499 + __ pop2p(r18, rbx); // {load}pop2p rbx, r18 IID500 + __ push2(r23, r19); // {load}push2 r19, r23 IID501 + __ push2p(r12, rbx); // {load}push2p rbx, r12 IID502 + __ movzbq(r9, Address(r14, r23, (Address::ScaleFactor)3, -0x428d2646)); // movzx r9, byte ptr [r14+r23*8-0x428d2646] IID503 + __ movzwq(r28, Address(r9, rcx, (Address::ScaleFactor)2, -0x72611661)); // movzx r28, word ptr [r9+rcx*4-0x72611661] IID504 + __ movsbq(rbx, Address(r24, r21, (Address::ScaleFactor)2, +0x3a6be990)); // movsx rbx, byte ptr [r24+r21*4+0x3a6be990] IID505 + __ movswq(r16, Address(r22, r10, (Address::ScaleFactor)0, +0x7ef8bdd)); // movsx r16, word ptr [r22+r10*1+0x7ef8bdd] IID506 + __ movzbq(r28, r14); // movzx r28, r14b IID507 + __ movzwq(r13, r28); // movzx r13, r28w IID508 + __ movsbq(r11, rdx); // movsx r11, dl IID509 + __ movswq(r12, r26); // movsx r12, r26w IID510 + __ cmpxchgq(r20, Address(r10, -0xbd2a8da)); // cmpxchg qword ptr [r10-0xbd2a8da], r20 IID511 + __ eidivq(r15, false); // {EVEX}idiv r15 IID512 + __ eidivq(r23, true); // {NF}idiv r23 IID513 + __ edivq(r14, false); // {EVEX}div r14 IID514 + __ edivq(r14, true); // {NF}div r14 IID515 + __ eimulq(r15, false); // {EVEX}imul r15 IID516 + __ eimulq(r20, true); // {NF}imul r20 IID517 + __ emulq(rcx, false); // {EVEX}mul rcx IID518 + __ emulq(r21, true); // {NF}mul r21 IID519 + __ emulq(Address(r16, r10, (Address::ScaleFactor)3, +0x5f66ac1e), false); // {EVEX}mul qword ptr [r16+r10*8+0x5f66ac1e] IID520 + __ emulq(Address(r21, r22, (Address::ScaleFactor)3, -0xbbc807d), true); // {NF}mul qword ptr [r21+r22*8-0xbbc807d] IID521 + __ eimulq(r22, r26, false); // {EVEX}imul r22, r26 IID522 + __ eimulq(r25, r21, true); // {NF}imul r25, r21 IID523 + __ elzcntq(r20, r13, false); // {EVEX}lzcnt r20, r13 IID524 + __ elzcntq(r25, r19, true); // {NF}lzcnt r25, r19 IID525 + __ enegq(r21, r30, false); // {EVEX}neg r21, r30 IID526 + __ enegq(r29, r11, true); // {NF}neg r29, r11 IID527 + __ enotq(r22, r8); // {EVEX}not r22, r8 IID528 + __ epopcntq(r12, r19, false); // {EVEX}popcnt r12, r19 IID529 + __ epopcntq(r29, r23, true); // {NF}popcnt r29, r23 IID530 + __ erolq(r28, r24, false); // {EVEX}rol r28, r24, cl IID531 + __ erolq(rdx, r20, true); // {NF}rol rdx, r20, cl IID532 + __ erorq(rbx, r30, false); // {EVEX}ror rbx, r30, cl IID533 + __ erorq(r10, r15, true); // {NF}ror r10, r15, cl IID534 + __ esalq(r17, r13, false); // {EVEX}sal r17, r13, cl IID535 + __ esalq(r21, r24, true); // {NF}sal r21, r24, cl IID536 + __ esarq(r31, r12, false); // {EVEX}sar r31, r12, cl IID537 + __ esarq(rdx, r24, true); // {NF}sar rdx, r24, cl IID538 + __ edecq(r21, r24, false); // {EVEX}dec r21, r24 IID539 + __ edecq(r15, r31, true); // {NF}dec r15, r31 IID540 + __ eincq(r10, rbx, false); // {EVEX}inc r10, rbx IID541 + __ eincq(r18, r8, true); // {NF}inc r18, r8 IID542 + __ eshlq(r10, r26, false); // {EVEX}shl r10, r26, cl IID543 + __ eshlq(r28, r14, true); // {NF}shl r28, r14, cl IID544 + __ eshrq(r10, r19, false); // {EVEX}shr r10, r19, cl IID545 + __ eshrq(r28, r21, true); // {NF}shr r28, r21, cl IID546 + __ etzcntq(r21, r22, false); // {EVEX}tzcnt r21, r22 IID547 + __ etzcntq(r16, r23, true); // {NF}tzcnt r16, r23 IID548 + __ eimulq(r11, Address(r18, r9, (Address::ScaleFactor)2, -0x132285a1), false); // {EVEX}imul r11, qword ptr [r18+r9*4-0x132285a1] IID549 + __ eimulq(r13, Address(r24, r15, (Address::ScaleFactor)3, +0x48f50ca0), true); // {NF}imul r13, qword ptr [r24+r15*8+0x48f50ca0] IID550 + __ elzcntq(r9, Address(r13, +0x2115cf0e), false); // {EVEX}lzcnt r9, qword ptr [r13+0x2115cf0e] IID551 + __ elzcntq(r27, Address(r30, +0x49cabbb), true); // {NF}lzcnt r27, qword ptr [r30+0x49cabbb] IID552 + __ enegq(r21, Address(r13, r31, (Address::ScaleFactor)2, +0x50a8f4d2), false); // {EVEX}neg r21, qword ptr [r13+r31*4+0x50a8f4d2] IID553 + __ enegq(r22, Address(r18, r20, (Address::ScaleFactor)1, -0x5da0584c), true); // {NF}neg r22, qword ptr [r18+r20*2-0x5da0584c] IID554 + __ epopcntq(r14, Address(rbx, r22, (Address::ScaleFactor)2, -0x606349d1), false); // {EVEX}popcnt r14, qword ptr [rbx+r22*4-0x606349d1] IID555 + __ epopcntq(r26, Address(r23, r22, (Address::ScaleFactor)3, -0x72c66c23), true); // {NF}popcnt r26, qword ptr [r23+r22*8-0x72c66c23] IID556 + __ esalq(r26, Address(r9, +0x334aba09), false); // {EVEX}sal r26, qword ptr [r9+0x334aba09], cl IID557 + __ esalq(r9, Address(r9, r30, (Address::ScaleFactor)3, -0x219a6102), true); // {NF}sal r9, qword ptr [r9+r30*8-0x219a6102], cl IID558 + __ esarq(r25, Address(r20, -0x2131bab1), false); // {EVEX}sar r25, qword ptr [r20-0x2131bab1], cl IID559 + __ esarq(r16, Address(r28, r16, (Address::ScaleFactor)1, +0x48c483b9), true); // {NF}sar r16, qword ptr [r28+r16*2+0x48c483b9], cl IID560 + __ edecq(r30, Address(r9, r16, (Address::ScaleFactor)0, -0x88ce84f), false); // {EVEX}dec r30, qword ptr [r9+r16*1-0x88ce84f] IID561 + __ edecq(r11, Address(r30, r29, (Address::ScaleFactor)2, +0x3eeb8fd0), true); // {NF}dec r11, qword ptr [r30+r29*4+0x3eeb8fd0] IID562 + __ eincq(r26, Address(r29, r10, (Address::ScaleFactor)3, +0x3ef4822e), false); // {EVEX}inc r26, qword ptr [r29+r10*8+0x3ef4822e] IID563 + __ eincq(r29, Address(r19, r20, (Address::ScaleFactor)2, -0x3f0f3db9), true); // {NF}inc r29, qword ptr [r19+r20*4-0x3f0f3db9] IID564 + __ eshrq(r8, Address(r30, r20, (Address::ScaleFactor)0, +0x15b56a17), false); // {EVEX}shr r8, qword ptr [r30+r20*1+0x15b56a17], cl IID565 + __ eshrq(r26, Address(r11, -0x2de86561), true); // {NF}shr r26, qword ptr [r11-0x2de86561], cl IID566 + __ etzcntq(r11, Address(rcx, r30, (Address::ScaleFactor)1, -0x32ffb1c2), false); // {EVEX}tzcnt r11, qword ptr [rcx+r30*2-0x32ffb1c2] IID567 + __ etzcntq(r23, Address(r9, r12, (Address::ScaleFactor)1, -0x54823e69), true); // {NF}tzcnt r23, qword ptr [r9+r12*2-0x54823e69] IID568 + __ eaddq(r20, Address(r13, rcx, (Address::ScaleFactor)3, -0x46116c0d), r15, false); // {EVEX}add r20, qword ptr [r13+rcx*8-0x46116c0d], r15 IID569 + __ eaddq(r13, Address(r9, r23, (Address::ScaleFactor)1, -0x286c7605), r16, true); // {NF}add r13, qword ptr [r9+r23*2-0x286c7605], r16 IID570 + __ eandq(r21, Address(r30, r17, (Address::ScaleFactor)0, +0xf4e30b2), r29, false); // {EVEX}and r21, qword ptr [r30+r17*1+0xf4e30b2], r29 IID571 + __ eandq(r30, Address(r17, r31, (Address::ScaleFactor)0, +0x3ab9dec4), r17, true); // {NF}and r30, qword ptr [r17+r31*1+0x3ab9dec4], r17 IID572 + __ eorq(r10, Address(r27, r30, (Address::ScaleFactor)1, -0x197f1266), r28, false); // {EVEX}or r10, qword ptr [r27+r30*2-0x197f1266], r28 IID573 + __ eorq(r9, Address(r29, r30, (Address::ScaleFactor)0, -0x24ea9b08), r11, true); // {NF}or r9, qword ptr [r29+r30*1-0x24ea9b08], r11 IID574 + __ esubq(r15, Address(r14, -0x4f44bf90), r16, false); // {EVEX}sub r15, qword ptr [r14-0x4f44bf90], r16 IID575 + __ esubq(rcx, Address(r21, r18, (Address::ScaleFactor)1, -0x11d0ac8f), r28, true); // {NF}sub rcx, qword ptr [r21+r18*2-0x11d0ac8f], r28 IID576 + __ exorq(r19, Address(r19, r18, (Address::ScaleFactor)0, -0xa5e55ec), r8, false); // {EVEX}xor r19, qword ptr [r19+r18*1-0xa5e55ec], r8 IID577 + __ exorq(r28, Address(r17, r28, (Address::ScaleFactor)1, -0x6eb42fe0), r16, true); // {NF}xor r28, qword ptr [r17+r28*2-0x6eb42fe0], r16 IID578 + __ eaddq(r17, Address(r18, -0x60ab1105), 16777216, false); // {EVEX}add r17, qword ptr [r18-0x60ab1105], 16777216 IID579 + __ eaddq(r25, Address(r19, r25, (Address::ScaleFactor)0, +0x122444d9), 65536, true); // {NF}add r25, qword ptr [r19+r25*1+0x122444d9], 65536 IID580 + __ eandq(r30, Address(r9, r28, (Address::ScaleFactor)1, -0x25b00cf3), 4096, false); // {EVEX}and r30, qword ptr [r9+r28*2-0x25b00cf3], 4096 IID581 + __ eandq(r9, Address(r22, rbx, (Address::ScaleFactor)1, -0x7e465026), 268435456, true); // {NF}and r9, qword ptr [r22+rbx*2-0x7e465026], 268435456 IID582 + __ eimulq(r12, Address(r25, r25, (Address::ScaleFactor)1, -0x432d68cc), 1, false); // {EVEX}imul r12, qword ptr [r25+r25*2-0x432d68cc], 1 IID583 + __ eimulq(r15, Address(r17, r31, (Address::ScaleFactor)3, -0x2b97565e), 16, true); // {NF}imul r15, qword ptr [r17+r31*8-0x2b97565e], 16 IID584 + __ eorq(r28, Address(rdx, r31, (Address::ScaleFactor)0, +0x3f1363b1), 256, false); // {EVEX}or r28, qword ptr [rdx+r31*1+0x3f1363b1], 256 IID585 + __ eorq(r16, Address(r12, r23, (Address::ScaleFactor)3, -0x1785863c), 16777216, true); // {NF}or r16, qword ptr [r12+r23*8-0x1785863c], 16777216 IID586 + __ esalq(r8, Address(r14, r24, (Address::ScaleFactor)2, -0x714290a5), 2, false); // {EVEX}sal r8, qword ptr [r14+r24*4-0x714290a5], 2 IID587 + __ esalq(r8, Address(r15, r14, (Address::ScaleFactor)2, +0x21f13243), 16, true); // {NF}sal r8, qword ptr [r15+r14*4+0x21f13243], 16 IID588 + __ esarq(r10, Address(r13, r29, (Address::ScaleFactor)0, +0x7d04cb72), 2, false); // {EVEX}sar r10, qword ptr [r13+r29*1+0x7d04cb72], 2 IID589 + __ esarq(r11, Address(r21, r31, (Address::ScaleFactor)3, -0x2176b4dc), 8, true); // {NF}sar r11, qword ptr [r21+r31*8-0x2176b4dc], 8 IID590 + __ eshrq(rcx, Address(r16, r12, (Address::ScaleFactor)1, +0x260c9a38), 4, false); // {EVEX}shr rcx, qword ptr [r16+r12*2+0x260c9a38], 4 IID591 + __ eshrq(r22, Address(r26, r9, (Address::ScaleFactor)0, -0x5e56bb62), 8, true); // {NF}shr r22, qword ptr [r26+r9*1-0x5e56bb62], 8 IID592 + __ esubq(r31, Address(rbx, r28, (Address::ScaleFactor)1, +0x2b00bb10), 1, false); // {EVEX}sub r31, qword ptr [rbx+r28*2+0x2b00bb10], 1 IID593 + __ esubq(r21, Address(r31, -0x6c10f4ad), 4096, true); // {NF}sub r21, qword ptr [r31-0x6c10f4ad], 4096 IID594 + __ exorq(r11, Address(r23, r30, (Address::ScaleFactor)1, +0x51a6026b), 65536, false); // {EVEX}xor r11, qword ptr [r23+r30*2+0x51a6026b], 65536 IID595 + __ exorq(r14, Address(r27, r10, (Address::ScaleFactor)2, -0x34ad9bab), 16, true); // {NF}xor r14, qword ptr [r27+r10*4-0x34ad9bab], 16 IID596 + __ eaddq(r20, r23, 16777216, false); // {EVEX}add r20, r23, 16777216 IID597 + __ eaddq(rax, r30, 16777216, false); // {EVEX}add rax, r30, 16777216 IID598 + __ eaddq(r9, r21, 4096, true); // {NF}add r9, r21, 4096 IID599 + __ eaddq(rax, rbx, 4096, true); // {NF}add rax, rbx, 4096 IID600 + __ eandq(rdx, r21, 268435456, false); // {EVEX}and rdx, r21, 268435456 IID601 + __ eandq(rax, r8, 268435456, false); // {EVEX}and rax, r8, 268435456 IID602 + __ eandq(r19, r31, 65536, true); // {NF}and r19, r31, 65536 IID603 + __ eandq(rax, rbx, 65536, true); // {NF}and rax, rbx, 65536 IID604 + __ eimulq(r21, r9, 16777216, false); // {EVEX}imul r21, r9, 16777216 IID605 + __ eimulq(rax, r30, 16777216, false); // {EVEX}imul rax, r30, 16777216 IID606 + __ eimulq(r30, r18, 65536, true); // {NF}imul r30, r18, 65536 IID607 + __ eimulq(rax, r19, 65536, true); // {NF}imul rax, r19, 65536 IID608 + __ eorq(r20, r16, 1048576, false); // {EVEX}or r20, r16, 1048576 IID609 + __ eorq(rax, r28, 1048576, false); // {EVEX}or rax, r28, 1048576 IID610 + __ eorq(rbx, r24, 4096, true); // {NF}or rbx, r24, 4096 IID611 + __ eorq(rax, r22, 4096, true); // {NF}or rax, r22, 4096 IID612 + __ erclq(r20, r30, 4); // {EVEX}rcl r20, r30, 4 IID613 + __ erclq(rax, r22, 4); // {EVEX}rcl rax, r22, 4 IID614 + __ erolq(rcx, r28, 2, false); // {EVEX}rol rcx, r28, 2 IID615 + __ erolq(rax, r21, 2, false); // {EVEX}rol rax, r21, 2 IID616 + __ erolq(r26, r15, 4, true); // {NF}rol r26, r15, 4 IID617 + __ erolq(rax, r19, 4, true); // {NF}rol rax, r19, 4 IID618 + __ erorq(r24, r19, 8, false); // {EVEX}ror r24, r19, 8 IID619 + __ erorq(rax, r28, 8, false); // {EVEX}ror rax, r28, 8 IID620 + __ erorq(r25, r18, 4, true); // {NF}ror r25, r18, 4 IID621 + __ erorq(rax, r13, 4, true); // {NF}ror rax, r13, 4 IID622 + __ esalq(r27, r17, 2, false); // {EVEX}sal r27, r17, 2 IID623 + __ esalq(rax, rdx, 2, false); // {EVEX}sal rax, rdx, 2 IID624 + __ esalq(rbx, r28, 16, true); // {NF}sal rbx, r28, 16 IID625 + __ esalq(rax, r15, 16, true); // {NF}sal rax, r15, 16 IID626 + __ esarq(rbx, r12, 4, false); // {EVEX}sar rbx, r12, 4 IID627 + __ esarq(rax, rbx, 4, false); // {EVEX}sar rax, rbx, 4 IID628 + __ esarq(r17, rdx, 2, true); // {NF}sar r17, rdx, 2 IID629 + __ esarq(rax, r31, 2, true); // {NF}sar rax, r31, 2 IID630 + __ eshlq(r21, rbx, 4, false); // {EVEX}shl r21, rbx, 4 IID631 + __ eshlq(rax, r24, 4, false); // {EVEX}shl rax, r24, 4 IID632 + __ eshlq(r27, r13, 16, true); // {NF}shl r27, r13, 16 IID633 + __ eshlq(rax, r25, 16, true); // {NF}shl rax, r25, 16 IID634 + __ eshrq(rcx, r22, 16, false); // {EVEX}shr rcx, r22, 16 IID635 + __ eshrq(rax, r14, 16, false); // {EVEX}shr rax, r14, 16 IID636 + __ eshrq(r11, r30, 4, true); // {NF}shr r11, r30, 4 IID637 + __ eshrq(rax, r24, 4, true); // {NF}shr rax, r24, 4 IID638 + __ esubq(r20, r19, 256, false); // {EVEX}sub r20, r19, 256 IID639 + __ esubq(rax, r17, 256, false); // {EVEX}sub rax, r17, 256 IID640 + __ esubq(r31, r30, 65536, true); // {NF}sub r31, r30, 65536 IID641 + __ esubq(rax, r18, 65536, true); // {NF}sub rax, r18, 65536 IID642 + __ exorq(r18, r11, 4096, false); // {EVEX}xor r18, r11, 4096 IID643 + __ exorq(rax, r10, 4096, false); // {EVEX}xor rax, r10, 4096 IID644 + __ exorq(r24, r18, 268435456, true); // {NF}xor r24, r18, 268435456 IID645 + __ exorq(rax, rbx, 268435456, true); // {NF}xor rax, rbx, 268435456 IID646 + __ eorq_imm32(r26, r21, 4194304, false); // {EVEX}or r26, r21, 4194304 IID647 + __ eorq_imm32(rax, r8, 4194304, false); // {EVEX}or rax, r8, 4194304 IID648 + __ eorq_imm32(r22, r21, 262144, false); // {EVEX}or r22, r21, 262144 IID649 + __ eorq_imm32(rax, r27, 262144, false); // {EVEX}or rax, r27, 262144 IID650 + __ esubq_imm32(r16, r8, 4194304, false); // {EVEX}sub r16, r8, 4194304 IID651 + __ esubq_imm32(rax, rdx, 4194304, false); // {EVEX}sub rax, rdx, 4194304 IID652 + __ esubq_imm32(r20, r31, 1048576, true); // {NF}sub r20, r31, 1048576 IID653 + __ esubq_imm32(rax, r21, 1048576, true); // {NF}sub rax, r21, 1048576 IID654 + __ eaddq(r20, r14, Address(rcx, r16, (Address::ScaleFactor)0, +0x7c6654d9), false); // {EVEX}add r20, r14, qword ptr [rcx+r16*1+0x7c6654d9] IID655 + __ eaddq(r29, rcx, Address(r15, r23, (Address::ScaleFactor)0, +0x45b7f72d), true); // {NF}add r29, rcx, qword ptr [r15+r23*1+0x45b7f72d] IID656 + __ eandq(r19, r17, Address(r13, r22, (Address::ScaleFactor)1, -0x750c1996), false); // {EVEX}and r19, r17, qword ptr [r13+r22*2-0x750c1996] IID657 + __ eandq(r13, r8, Address(r31, r23, (Address::ScaleFactor)1, -0x2211b6b2), true); // {NF}and r13, r8, qword ptr [r31+r23*2-0x2211b6b2] IID658 + __ eorq(r11, r28, Address(r13, r11, (Address::ScaleFactor)3, +0x5c0013ab), false); // {EVEX}or r11, r28, qword ptr [r13+r11*8+0x5c0013ab] IID659 + __ eorq(rdx, r18, Address(r18, rcx, (Address::ScaleFactor)0, +0x59557e71), true); // {NF}or rdx, r18, qword ptr [r18+rcx*1+0x59557e71] IID660 + __ eimulq(r27, r11, Address(r22, -0x28469649), false); // {EVEX}imul r27, r11, qword ptr [r22-0x28469649] IID661 + __ eimulq(r10, r9, Address(r24, +0x49691d54), true); // {NF}imul r10, r9, qword ptr [r24+0x49691d54] IID662 + __ esubq(r24, r12, Address(r19, +0x22d529aa), false); // {EVEX}sub r24, r12, qword ptr [r19+0x22d529aa] IID663 + __ esubq(r20, r18, Address(r9, r10, (Address::ScaleFactor)2, -0x264a7a48), true); // {NF}sub r20, r18, qword ptr [r9+r10*4-0x264a7a48] IID664 + __ exorq(rbx, r9, Address(r14, r27, (Address::ScaleFactor)0, +0xf71c02f), false); // {EVEX}xor rbx, r9, qword ptr [r14+r27*1+0xf71c02f] IID665 + __ exorq(r25, r15, Address(r10, r12, (Address::ScaleFactor)1, +0x732367bd), true); // {NF}xor r25, r15, qword ptr [r10+r12*2+0x732367bd] IID666 + __ eaddq(r11, r9, r10, false); // {load}{EVEX}add r11, r9, r10 IID667 + __ eaddq(r25, r13, r16, true); // {load}{NF}add r25, r13, r16 IID668 + __ eadcxq(r11, r21, r25); // {load}{EVEX}adcx r11, r21, r25 IID669 + __ eadoxq(rdx, r20, rbx); // {load}{EVEX}adox rdx, r20, rbx IID670 + __ eandq(r25, r21, r26, false); // {load}{EVEX}and r25, r21, r26 IID671 + __ eandq(r23, r27, r21, true); // {load}{NF}and r23, r27, r21 IID672 + __ eimulq(r10, r10, r12, false); // {load}{EVEX}imul r10, r10, r12 IID673 + __ eimulq(r31, r12, r23, true); // {load}{NF}imul r31, r12, r23 IID674 + __ eorq(r16, r29, r14, false); // {load}{EVEX}or r16, r29, r14 IID675 + __ eorq(r19, r24, r23, true); // {load}{NF}or r19, r24, r23 IID676 + __ esubq(r14, r21, r15, false); // {load}{EVEX}sub r14, r21, r15 IID677 + __ esubq(r25, r9, r29, true); // {load}{NF}sub r25, r9, r29 IID678 + __ exorq(rdx, r11, r25, false); // {load}{EVEX}xor rdx, r11, r25 IID679 + __ exorq(r19, r10, r16, true); // {load}{NF}xor r19, r10, r16 IID680 + __ eshldq(r8, r23, r31, 8, false); // {EVEX}shld r8, r23, r31, 8 IID681 + __ eshldq(r31, rbx, r16, 2, true); // {NF}shld r31, rbx, r16, 2 IID682 + __ eshrdq(r24, r10, r9, 2, false); // {EVEX}shrd r24, r10, r9, 2 IID683 + __ eshrdq(r28, r26, r18, 16, true); // {NF}shrd r28, r26, r18, 16 IID684 + __ ecmovq (Assembler::Condition::overflow, r25, r20, r16); // cmovo r25, r20, r16 IID685 + __ ecmovq (Assembler::Condition::noOverflow, r21, rbx, r28); // cmovno r21, rbx, r28 IID686 + __ ecmovq (Assembler::Condition::below, r22, r19, r13); // cmovb r22, r19, r13 IID687 + __ ecmovq (Assembler::Condition::aboveEqual, r15, rdx, r8); // cmovae r15, rdx, r8 IID688 + __ ecmovq (Assembler::Condition::zero, r22, r14, r12); // cmovz r22, r14, r12 IID689 + __ ecmovq (Assembler::Condition::notZero, r24, r14, r24); // cmovnz r24, r14, r24 IID690 + __ ecmovq (Assembler::Condition::belowEqual, r13, r21, rbx); // cmovbe r13, r21, rbx IID691 + __ ecmovq (Assembler::Condition::above, rbx, r27, r14); // cmova rbx, r27, r14 IID692 + __ ecmovq (Assembler::Condition::negative, r24, r27, r17); // cmovs r24, r27, r17 IID693 + __ ecmovq (Assembler::Condition::positive, r21, r27, r27); // cmovns r21, r27, r27 IID694 + __ ecmovq (Assembler::Condition::parity, r27, r14, r24); // cmovp r27, r14, r24 IID695 + __ ecmovq (Assembler::Condition::noParity, r28, r29, r22); // cmovnp r28, r29, r22 IID696 + __ ecmovq (Assembler::Condition::less, r15, r13, r31); // cmovl r15, r13, r31 IID697 + __ ecmovq (Assembler::Condition::greaterEqual, r21, r15, r30); // cmovge r21, r15, r30 IID698 + __ ecmovq (Assembler::Condition::lessEqual, r20, r8, r13); // cmovle r20, r8, r13 IID699 + __ ecmovq (Assembler::Condition::greater, r31, r25, r27); // cmovg r31, r25, r27 IID700 + __ ecmovq (Assembler::Condition::overflow, r31, r15, Address(r14, r13, (Address::ScaleFactor)1, -0x6e68556)); // cmovo r31, r15, qword ptr [r14+r13*2-0x6e68556] IID701 + __ ecmovq (Assembler::Condition::noOverflow, r12, r28, Address(r30, r15, (Address::ScaleFactor)3, +0x3ba33f9e)); // cmovno r12, r28, qword ptr [r30+r15*8+0x3ba33f9e] IID702 + __ ecmovq (Assembler::Condition::below, r16, r25, Address(r12, r9, (Address::ScaleFactor)0, -0x28e03b33)); // cmovb r16, r25, qword ptr [r12+r9*1-0x28e03b33] IID703 + __ ecmovq (Assembler::Condition::aboveEqual, r8, r27, Address(r8, r25, (Address::ScaleFactor)3, -0x1e42bd95)); // cmovae r8, r27, qword ptr [r8+r25*8-0x1e42bd95] IID704 + __ ecmovq (Assembler::Condition::zero, rcx, r20, Address(r27, rbx, (Address::ScaleFactor)2, +0x46823c58)); // cmovz rcx, r20, qword ptr [r27+rbx*4+0x46823c58] IID705 + __ ecmovq (Assembler::Condition::notZero, rbx, r12, Address(r21, -0x635b8c8)); // cmovnz rbx, r12, qword ptr [r21-0x635b8c8] IID706 + __ ecmovq (Assembler::Condition::belowEqual, r23, rbx, Address(r27, r26, (Address::ScaleFactor)3, +0x922bcc0)); // cmovbe r23, rbx, qword ptr [r27+r26*8+0x922bcc0] IID707 + __ ecmovq (Assembler::Condition::above, r25, r9, Address(r23, +0xd2a14ec)); // cmova r25, r9, qword ptr [r23+0xd2a14ec] IID708 + __ ecmovq (Assembler::Condition::negative, r11, r19, Address(r11, -0xfb95a9d)); // cmovs r11, r19, qword ptr [r11-0xfb95a9d] IID709 + __ ecmovq (Assembler::Condition::positive, r13, r18, Address(r28, r19, (Address::ScaleFactor)0, +0x716b9b7e)); // cmovns r13, r18, qword ptr [r28+r19*1+0x716b9b7e] IID710 + __ ecmovq (Assembler::Condition::parity, r21, r16, Address(rcx, r29, (Address::ScaleFactor)0, -0x5af0441e)); // cmovp r21, r16, qword ptr [rcx+r29*1-0x5af0441e] IID711 + __ ecmovq (Assembler::Condition::noParity, r12, r31, Address(r20, r26, (Address::ScaleFactor)0, +0xe0b7fb1)); // cmovnp r12, r31, qword ptr [r20+r26*1+0xe0b7fb1] IID712 + __ ecmovq (Assembler::Condition::less, r15, r24, Address(r30, +0x2d3b7b4f)); // cmovl r15, r24, qword ptr [r30+0x2d3b7b4f] IID713 + __ ecmovq (Assembler::Condition::greaterEqual, r12, r15, Address(r14, r21, (Address::ScaleFactor)2, -0x1222aee8)); // cmovge r12, r15, qword ptr [r14+r21*4-0x1222aee8] IID714 + __ ecmovq (Assembler::Condition::lessEqual, rbx, r31, Address(r23, r20, (Address::ScaleFactor)0, -0x96e4d6a)); // cmovle rbx, r31, qword ptr [r23+r20*1-0x96e4d6a] IID715 + __ ecmovq (Assembler::Condition::greater, rdx, rdx, Address(r10, rdx, (Address::ScaleFactor)3, +0x3875f17c)); // cmovg rdx, rdx, qword ptr [r10+rdx*8+0x3875f17c] IID716 #endif // _LP64 static const uint8_t insns[] = @@ -944,412 +1002,470 @@ 0x62, 0x4c, 0x34, 0x18, 0x30, 0xb7, 0x8e, 0xf5, 0xa4, 0x72, // IID252 0x62, 0x8c, 0x3c, 0x14, 0x30, 0x84, 0x39, 0x0a, 0x1a, 0xfc, 0x20, // IID253 0x62, 0xf4, 0x1c, 0x18, 0x81, 0xc3, 0x00, 0x00, 0x01, 0x00, // IID254 - 0x62, 0xdc, 0x5c, 0x14, 0x81, 0xc0, 0x00, 0x10, 0x00, 0x00, // IID255 - 0x62, 0xdc, 0x6c, 0x10, 0x81, 0xe2, 0x00, 0x00, 0x10, 0x00, // IID256 - 0x62, 0xd4, 0x14, 0x14, 0x83, 0xe5, 0x01, // IID257 - 0x62, 0xdc, 0x7c, 0x08, 0x69, 0xcf, 0x00, 0x00, 0x01, 0x00, // IID258 - 0x62, 0xcc, 0x7c, 0x0c, 0x69, 0xfd, 0x00, 0x00, 0x01, 0x00, // IID259 - 0x62, 0xfc, 0x44, 0x10, 0x81, 0xcf, 0x00, 0x00, 0x10, 0x00, // IID260 - 0x62, 0xd4, 0x54, 0x14, 0x81, 0xc9, 0x00, 0x00, 0x00, 0x10, // IID261 - 0x62, 0xf4, 0x14, 0x18, 0xc1, 0xd2, 0x04, // IID262 - 0x62, 0xdc, 0x04, 0x18, 0xc1, 0xc7, 0x08, // IID263 - 0x62, 0xd4, 0x3c, 0x1c, 0xc1, 0xc1, 0x02, // IID264 - 0x62, 0xd4, 0x34, 0x18, 0xc1, 0xcf, 0x08, // IID265 - 0x62, 0xd4, 0x54, 0x14, 0xc1, 0xcc, 0x08, // IID266 - 0x62, 0xdc, 0x64, 0x10, 0xd1, 0xe3, // IID267 - 0x62, 0xd4, 0x2c, 0x1c, 0xc1, 0xe3, 0x10, // IID268 - 0x62, 0xf4, 0x3c, 0x18, 0xc1, 0xfa, 0x08, // IID269 - 0x62, 0xdc, 0x4c, 0x14, 0xc1, 0xfe, 0x04, // IID270 - 0x62, 0xdc, 0x34, 0x10, 0xc1, 0xe7, 0x10, // IID271 - 0x62, 0xd4, 0x2c, 0x1c, 0xc1, 0xe1, 0x08, // IID272 - 0x62, 0xd4, 0x14, 0x18, 0xc1, 0xe8, 0x04, // IID273 - 0x62, 0xfc, 0x7c, 0x14, 0xc1, 0xed, 0x10, // IID274 - 0x62, 0xfc, 0x2c, 0x10, 0x81, 0xef, 0x00, 0x00, 0x00, 0x01, // IID275 - 0x62, 0xd4, 0x2c, 0x14, 0x81, 0xee, 0x00, 0x00, 0x10, 0x00, // IID276 - 0x62, 0xdc, 0x24, 0x10, 0x81, 0xf2, 0x00, 0x01, 0x00, 0x00, // IID277 - 0x62, 0xd4, 0x4c, 0x14, 0x83, 0xf1, 0x01, // IID278 - 0x62, 0xdc, 0x4c, 0x10, 0x81, 0xee, 0x00, 0x00, 0x00, 0x10, // IID279 - 0x62, 0xfc, 0x3c, 0x1c, 0x81, 0xe8, 0x00, 0x00, 0x40, 0x00, // IID280 - 0x62, 0x04, 0x5c, 0x10, 0x03, 0xac, 0x63, 0x80, 0x09, 0xac, 0x00, // IID281 - 0x62, 0xd4, 0x68, 0x14, 0x03, 0x9c, 0x51, 0x5d, 0x12, 0x4a, 0x43, // IID282 - 0x62, 0x54, 0x08, 0x18, 0x23, 0xbc, 0x9e, 0xee, 0xa5, 0xa5, 0x15, // IID283 - 0x62, 0x0c, 0x1c, 0x14, 0x23, 0xbc, 0xe0, 0x98, 0x81, 0x92, 0x92, // IID284 - 0x62, 0x1c, 0x38, 0x10, 0xaf, 0xac, 0xc8, 0xfd, 0x73, 0x46, 0x78, // IID285 - 0x62, 0x84, 0x3c, 0x14, 0xaf, 0xac, 0xa8, 0x77, 0xc7, 0x99, 0x9c, // IID286 - 0x62, 0x4c, 0x1c, 0x18, 0x0b, 0x86, 0xaa, 0x9a, 0xad, 0x98, // IID287 - 0x62, 0x34, 0x10, 0x1c, 0x0b, 0xac, 0x8b, 0x27, 0xb2, 0xc6, 0xa0, // IID288 - 0x62, 0x4c, 0x2c, 0x10, 0x2b, 0x8c, 0xd1, 0x66, 0x08, 0xc6, 0xd1, // IID289 - 0x62, 0x34, 0x18, 0x14, 0x2b, 0x84, 0xc2, 0xac, 0x65, 0x26, 0xf1, // IID290 - 0x62, 0xcc, 0x00, 0x10, 0x33, 0xb4, 0xe6, 0xbd, 0x1c, 0xc4, 0x3a, // IID291 - 0x62, 0x44, 0x38, 0x14, 0x33, 0xb4, 0x4d, 0xe3, 0xc2, 0xfd, 0x1e, // IID292 - 0x62, 0x84, 0x7c, 0x10, 0x32, 0x84, 0x79, 0x34, 0xeb, 0x9f, 0x76, // IID293 - 0x62, 0x44, 0x64, 0x14, 0x32, 0x8a, 0x29, 0xb4, 0x39, 0x22, // IID294 - 0x62, 0xac, 0x31, 0x10, 0x33, 0x9c, 0x40, 0xea, 0xfa, 0x71, 0x1c, // IID295 - 0x62, 0x5c, 0x65, 0x14, 0x33, 0x94, 0x24, 0x03, 0xf3, 0x65, 0xd6, // IID296 - 0x62, 0xcc, 0x64, 0x18, 0x03, 0xf8, // IID297 - 0x62, 0x5c, 0x1c, 0x14, 0x03, 0xf0, // IID298 - 0x62, 0x4c, 0x0c, 0x10, 0x23, 0xfa, // IID299 - 0x62, 0x6c, 0x1c, 0x1c, 0x23, 0xff, // IID300 - 0x62, 0xc4, 0x34, 0x18, 0xaf, 0xe2, // IID301 - 0x62, 0x44, 0x14, 0x1c, 0xaf, 0xf1, // IID302 - 0x62, 0xec, 0x35, 0x10, 0x0b, 0xdf, // IID303 - 0x62, 0xe4, 0x1d, 0x1c, 0x0b, 0xc2, // IID304 - 0x62, 0xc4, 0x04, 0x10, 0x0b, 0xc9, // IID305 - 0x62, 0x74, 0x04, 0x1c, 0x0b, 0xeb, // IID306 - 0x62, 0x64, 0x1c, 0x10, 0xa5, 0xeb, // IID307 - 0x62, 0x74, 0x4c, 0x14, 0xa5, 0xc3, // IID308 - 0x62, 0xc4, 0x3c, 0x18, 0xad, 0xc3, // IID309 - 0x62, 0x54, 0x14, 0x1c, 0xad, 0xfc, // IID310 - 0x62, 0xcc, 0x74, 0x10, 0x2b, 0xff, // IID311 - 0x62, 0xcc, 0x5c, 0x14, 0x2b, 0xf2, // IID312 - 0x62, 0x6c, 0x2c, 0x18, 0x33, 0xcb, // IID313 - 0x62, 0xcc, 0x24, 0x1c, 0x33, 0xde, // IID314 - 0x62, 0xd4, 0x1c, 0x18, 0x24, 0xd2, 0x01, // IID315 - 0x62, 0xcc, 0x5c, 0x14, 0x24, 0xd6, 0x10, // IID316 - 0x62, 0xcc, 0x6c, 0x10, 0x2c, 0xd1, 0x08, // IID317 - 0x62, 0x6c, 0x64, 0x14, 0x2c, 0xc8, 0x01, // IID318 - 0x62, 0x4c, 0x24, 0x18, 0x40, 0xf8, // IID319 - 0x62, 0x6c, 0x0c, 0x18, 0x41, 0xf0, // IID320 - 0x62, 0x5c, 0x34, 0x18, 0x42, 0xda, // IID321 - 0x62, 0xdc, 0x24, 0x10, 0x43, 0xd7, // IID322 - 0x62, 0x44, 0x3c, 0x10, 0x44, 0xea, // IID323 - 0x62, 0xc4, 0x74, 0x18, 0x45, 0xef, // IID324 - 0x62, 0xcc, 0x44, 0x10, 0x46, 0xca, // IID325 - 0x62, 0x44, 0x5c, 0x10, 0x47, 0xdd, // IID326 - 0x62, 0xc4, 0x04, 0x18, 0x48, 0xf7, // IID327 - 0x62, 0x6c, 0x14, 0x10, 0x49, 0xd2, // IID328 - 0x62, 0x7c, 0x34, 0x18, 0x4a, 0xce, // IID329 - 0x62, 0xc4, 0x0c, 0x10, 0x4b, 0xfb, // IID330 - 0x62, 0x74, 0x5c, 0x10, 0x4c, 0xdb, // IID331 - 0x62, 0xec, 0x1c, 0x10, 0x4d, 0xc4, // IID332 - 0x62, 0x6c, 0x74, 0x10, 0x4e, 0xc6, // IID333 - 0x62, 0x54, 0x7c, 0x10, 0x4f, 0xff, // IID334 - 0x62, 0x4c, 0x18, 0x10, 0x40, 0x8c, 0x85, 0x53, 0xef, 0x6e, 0xc3, // IID335 - 0x62, 0x34, 0x40, 0x10, 0x41, 0xbc, 0xf3, 0xbd, 0x58, 0xbc, 0x1c, // IID336 - 0x62, 0xd4, 0x2c, 0x10, 0x42, 0x9c, 0xcc, 0x1a, 0x58, 0x4e, 0x08, // IID337 - 0x62, 0x6c, 0x74, 0x18, 0x43, 0x81, 0x2d, 0xe9, 0xec, 0x5c, // IID338 - 0x62, 0x0c, 0x2c, 0x10, 0x44, 0x84, 0xe0, 0xa2, 0x46, 0x77, 0x50, // IID339 - 0x62, 0x74, 0x38, 0x18, 0x45, 0xbc, 0x19, 0x8a, 0xa3, 0xfc, 0xf0, // IID340 - 0x62, 0xac, 0x68, 0x18, 0x46, 0xbc, 0x1e, 0xcc, 0xca, 0x01, 0xed, // IID341 - 0x62, 0x84, 0x08, 0x10, 0x47, 0x9c, 0x25, 0x9d, 0xee, 0xb8, 0x73, // IID342 - 0x62, 0x6c, 0x4c, 0x10, 0x48, 0xb4, 0x08, 0x46, 0xc1, 0xaa, 0x22, // IID343 - 0x62, 0x2c, 0x74, 0x10, 0x49, 0xb4, 0x89, 0xb1, 0xb2, 0x9d, 0x07, // IID344 - 0x62, 0xd4, 0x28, 0x10, 0x4a, 0x94, 0x46, 0xef, 0xdf, 0xdb, 0xf7, // IID345 - 0x62, 0x84, 0x20, 0x18, 0x4b, 0x9c, 0x7e, 0x34, 0xae, 0x0d, 0xb0, // IID346 - 0x62, 0xc4, 0x58, 0x10, 0x4c, 0x94, 0x85, 0x1e, 0x39, 0x10, 0xe6, // IID347 - 0x62, 0x54, 0x60, 0x10, 0x4d, 0xac, 0x7d, 0x14, 0x77, 0x1b, 0x61, // IID348 - 0x62, 0x7c, 0x10, 0x10, 0x4e, 0xac, 0xc9, 0x3f, 0xa9, 0x94, 0x3a, // IID349 - 0x62, 0x44, 0x10, 0x18, 0x4f, 0xac, 0x7f, 0x32, 0x35, 0xd4, 0x76, // IID350 - 0x4d, 0x13, 0xfd, // IID351 - 0x4d, 0x3b, 0xcc, // IID352 - 0xd5, 0x9c, 0xaf, 0xfd, // IID353 - 0xf3, 0x4d, 0x0f, 0xb8, 0xe1, // IID354 - 0xd5, 0x58, 0x1b, 0xcf, // IID355 - 0xd5, 0x18, 0x2b, 0xd0, // IID356 - 0xf3, 0xd5, 0xcd, 0xbc, 0xea, // IID357 - 0xf3, 0xd5, 0xd8, 0xbd, 0xe9, // IID358 - 0xd5, 0x5c, 0x03, 0xea, // IID359 - 0xd5, 0x5d, 0x23, 0xe0, // IID360 - 0xd5, 0x1c, 0x0b, 0xd4, // IID361 - 0xd5, 0x4d, 0x33, 0xda, // IID362 - 0x4d, 0x8b, 0xf3, // IID363 - 0xd5, 0xcc, 0xbc, 0xd9, // IID364 - 0xd5, 0xc9, 0xbd, 0xf7, // IID365 - 0xd5, 0xdd, 0xa3, 0xf7, // IID366 - 0xd5, 0x58, 0x87, 0xdb, // IID367 - 0xd5, 0x5c, 0x85, 0xd5, // IID368 - 0xd5, 0x3d, 0x01, 0xb4, 0x62, 0x64, 0xeb, 0x69, 0xbf, // IID369 - 0xd5, 0x79, 0x21, 0xbc, 0xa4, 0x8a, 0x89, 0xd8, 0x1b, // IID370 - 0xd5, 0x2d, 0x39, 0x94, 0x9f, 0x31, 0xe6, 0xee, 0x39, // IID371 - 0x4d, 0x09, 0xac, 0xd5, 0x59, 0x98, 0xa4, 0x01, // IID372 - 0xd5, 0x5c, 0x31, 0x85, 0x36, 0x86, 0xfe, 0x05, // IID373 - 0xd5, 0x7d, 0x29, 0x8c, 0xbe, 0x3f, 0xc3, 0x9b, 0xa9, // IID374 - 0xd5, 0x7e, 0x89, 0xbc, 0xd5, 0xab, 0x44, 0x85, 0x7e, // IID375 - 0xd5, 0xaa, 0xc1, 0x9c, 0xc1, 0x77, 0xb7, 0x35, 0x86, // IID376 - 0xd5, 0x2b, 0x81, 0xa4, 0xfd, 0xd0, 0x4f, 0x8d, 0xf2, 0x00, 0x01, 0x00, 0x00, // IID377 - 0xd5, 0x18, 0x81, 0x80, 0x5e, 0x77, 0x4d, 0x53, 0x00, 0x00, 0x00, 0x10, // IID378 - 0xd5, 0x1a, 0x81, 0xbc, 0xbc, 0x89, 0xdd, 0x4d, 0x83, 0x00, 0x00, 0x00, 0x10, // IID379 - 0xd5, 0x29, 0xc1, 0xbc, 0xb9, 0x92, 0x27, 0x09, 0x8d, 0x04, // IID380 - 0xd5, 0x2b, 0xc1, 0xa4, 0x43, 0x6b, 0x90, 0x7d, 0xdd, 0x04, // IID381 - 0xd5, 0x2b, 0x81, 0x9c, 0x76, 0x34, 0xfc, 0x43, 0x1b, 0x00, 0x00, 0x00, 0x10, // IID382 - 0xd5, 0x39, 0xc1, 0xac, 0x2a, 0x3d, 0xaf, 0x51, 0xc4, 0x08, // IID383 - 0xd5, 0x1a, 0x81, 0xac, 0xd6, 0x03, 0x14, 0x7e, 0x04, 0x00, 0x00, 0x01, 0x00, // IID384 - 0xd5, 0x28, 0x83, 0xb4, 0xda, 0xe8, 0xac, 0xb5, 0x9b, 0x01, // IID385 - 0xd5, 0x3b, 0x81, 0x8c, 0x7e, 0x83, 0xc7, 0x93, 0x2c, 0x00, 0x01, 0x00, 0x00, // IID386 - 0xd5, 0x3b, 0xc7, 0x84, 0x82, 0xa1, 0x87, 0xcb, 0xfa, 0x00, 0x00, 0x01, 0x00, // IID387 - 0xd5, 0x2b, 0xf7, 0x84, 0x76, 0x47, 0xe1, 0x32, 0x39, 0x00, 0xff, 0xff, 0xff, // IID388 - 0xd5, 0x7f, 0x03, 0xb4, 0xc6, 0xa2, 0xdc, 0x1f, 0x99, // IID389 - 0xd5, 0x1d, 0x23, 0xba, 0x42, 0x6e, 0x45, 0x36, // IID390 - 0xd5, 0x1c, 0x3b, 0x92, 0xed, 0x4b, 0x04, 0x05, // IID391 - 0xf3, 0xd5, 0xcd, 0xbd, 0xbc, 0x94, 0x2c, 0x48, 0xf8, 0xe8, // IID392 - 0xd5, 0x78, 0x0b, 0x84, 0xbc, 0xd7, 0xc8, 0x87, 0xd9, // IID393 - 0xd5, 0x7f, 0x13, 0xbc, 0x3e, 0x5d, 0x26, 0xc3, 0x1e, // IID394 - 0xd5, 0xea, 0xaf, 0x84, 0x12, 0x1b, 0x83, 0x86, 0x35, // IID395 - 0xf3, 0xd5, 0x9c, 0xb8, 0xa2, 0x86, 0x60, 0xc1, 0xc3, // IID396 - 0xd5, 0x29, 0x1b, 0x8c, 0xe8, 0xab, 0x15, 0x15, 0x6b, // IID397 - 0xd5, 0x6c, 0x2b, 0xac, 0xb9, 0x4d, 0x6c, 0xf0, 0x4f, // IID398 - 0xf3, 0xd5, 0xdf, 0xbc, 0x94, 0x50, 0x77, 0x5e, 0x26, 0x8a, // IID399 - 0xd5, 0x48, 0x33, 0x8c, 0x1b, 0x9c, 0xd5, 0x33, 0x40, // IID400 - 0xd5, 0x5a, 0x8b, 0x94, 0xe6, 0x83, 0xcb, 0x6c, 0xc7, // IID401 - 0xd5, 0x3c, 0x8d, 0xa4, 0xfc, 0x60, 0x15, 0x31, 0x4b, // IID402 - 0xf2, 0xd5, 0xef, 0x2c, 0xac, 0xa2, 0x57, 0x26, 0x3a, 0x5c, // IID403 - 0xd5, 0x6b, 0x87, 0xb4, 0xcd, 0x3f, 0x6f, 0x3d, 0x1a, // IID404 - 0xd5, 0x7e, 0x85, 0x8c, 0xc1, 0x28, 0x24, 0x52, 0xca, // IID405 - 0xd5, 0x18, 0x83, 0xc2, 0x01, // IID406 - 0x49, 0x81, 0xe5, 0x00, 0x00, 0x00, 0x01, // IID407 - 0x49, 0x81, 0xd5, 0x00, 0x00, 0x01, 0x00, // IID408 - 0x49, 0x81, 0xfa, 0x00, 0x00, 0x01, 0x00, // IID409 - 0xd5, 0x18, 0xc1, 0xd4, 0x02, // IID410 - 0x49, 0xc1, 0xd9, 0x10, // IID411 - 0x49, 0xd1, 0xc0, // IID412 - 0xd5, 0x19, 0xc1, 0xc9, 0x02, // IID413 - 0xd5, 0x18, 0xc1, 0xfe, 0x08, // IID414 - 0xd5, 0x18, 0xd1, 0xe1, // IID415 - 0xd5, 0x19, 0x83, 0xdf, 0x10, // IID416 - 0xd5, 0x19, 0xc1, 0xe3, 0x04, // IID417 - 0xd5, 0x19, 0xc1, 0xec, 0x02, // IID418 - 0x48, 0x81, 0xe9, 0x00, 0x00, 0x00, 0x01, // IID419 - 0xd5, 0x19, 0x81, 0xf3, 0x00, 0x00, 0x10, 0x00, // IID420 - 0xd5, 0x18, 0xc7, 0xc4, 0x00, 0x00, 0x00, 0x10, // IID421 - 0xd5, 0x19, 0xbb, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, // IID422 - 0xd5, 0x98, 0xba, 0xe6, 0x04, // IID423 - 0x49, 0xf7, 0xc0, 0x00, 0xf0, 0xff, 0xff, // IID424 - 0xd5, 0x19, 0x81, 0xcc, 0x00, 0x00, 0x10, 0x00, // IID425 - 0x49, 0x81, 0xed, 0x00, 0x00, 0x01, 0x00, // IID426 - 0xd5, 0xd8, 0x40, 0x80, 0x15, 0x5c, 0x76, 0xec, // IID427 - 0xd5, 0x9b, 0x41, 0x9c, 0x05, 0x15, 0x26, 0x02, 0x1d, // IID428 - 0xd5, 0xab, 0x42, 0x94, 0x64, 0x1e, 0x67, 0x37, 0xcb, // IID429 - 0xd5, 0xcd, 0x43, 0x9c, 0xca, 0x0f, 0x54, 0x08, 0xe1, // IID430 - 0xd5, 0xaf, 0x44, 0xb4, 0xad, 0x97, 0x7c, 0xb3, 0x83, // IID431 - 0xd5, 0x9c, 0x45, 0xbc, 0x8f, 0x31, 0xd3, 0x2d, 0x94, // IID432 - 0xd5, 0xcf, 0x46, 0x84, 0x57, 0xf7, 0xc2, 0x04, 0x80, // IID433 - 0xd5, 0xc9, 0x47, 0xbb, 0x3b, 0x86, 0x6a, 0x27, // IID434 - 0xd5, 0xdd, 0x48, 0xa5, 0x6e, 0x39, 0xb4, 0x3f, // IID435 - 0xd5, 0xdd, 0x49, 0x94, 0xcb, 0x1c, 0xa6, 0xde, 0x4d, // IID436 - 0xd5, 0xbc, 0x4a, 0x94, 0x5e, 0x66, 0x69, 0x12, 0x2a, // IID437 - 0x4d, 0x0f, 0x4b, 0xa2, 0x9f, 0xc5, 0xd7, 0x03, // IID438 - 0x4f, 0x0f, 0x4c, 0x94, 0xc0, 0xd3, 0x79, 0x9e, 0xf1, // IID439 - 0xd5, 0xd9, 0x4d, 0xbd, 0x93, 0x26, 0x81, 0x88, // IID440 - 0xd5, 0xa8, 0x4e, 0x8c, 0x5b, 0xcb, 0x01, 0xc6, 0x53, // IID441 - 0xd5, 0x9c, 0x4f, 0xb4, 0x19, 0x8d, 0x0f, 0x74, 0x89, // IID442 - 0xd5, 0x11, 0xff, 0xd5, // IID443 - 0x49, 0xf7, 0xf2, // IID444 - 0xd5, 0x18, 0xf7, 0xfb, // IID445 - 0x49, 0xf7, 0xef, // IID446 - 0xd5, 0x19, 0xf7, 0xe3, // IID447 - 0xd5, 0x18, 0xf7, 0xdc, // IID448 - 0x49, 0xf7, 0xd2, // IID449 - 0xd5, 0x18, 0xd3, 0xc0, // IID450 - 0xd5, 0x19, 0xd3, 0xcb, // IID451 - 0x49, 0xd3, 0xf9, // IID452 - 0x49, 0xd3, 0xe5, // IID453 - 0x49, 0xd3, 0xe6, // IID454 - 0xd5, 0x18, 0xd3, 0xea, // IID455 - 0xd5, 0x19, 0xff, 0xc4, // IID456 - 0xd5, 0x19, 0xff, 0xcc, // IID457 - 0xd5, 0x18, 0x56, // IID458 - 0xd5, 0x09, 0x58, // IID459 - 0x41, 0xff, 0x94, 0x24, 0x4e, 0x42, 0xcc, 0x64, // IID460 - 0xd5, 0x3b, 0xf7, 0xa4, 0x2a, 0xa1, 0xf7, 0x90, 0xb9, // IID461 - 0xd5, 0x3a, 0xf7, 0x9c, 0x05, 0x0b, 0xdf, 0x37, 0x20, // IID462 - 0xd5, 0x2b, 0xd3, 0xbc, 0xfc, 0x56, 0xda, 0x2d, 0xa8, // IID463 - 0xd5, 0x18, 0xd3, 0xa4, 0x24, 0x70, 0xd0, 0x5f, 0xe1, // IID464 - 0xd5, 0x29, 0xd3, 0xac, 0xe5, 0xf2, 0x81, 0x10, 0x17, // IID465 - 0xd5, 0x19, 0xff, 0x87, 0xdb, 0x08, 0xa8, 0x13, // IID466 - 0xd5, 0x18, 0xff, 0x8b, 0x5f, 0xc1, 0xf2, 0xe7, // IID467 - 0xd5, 0x58, 0x69, 0x88, 0xa8, 0x02, 0x0d, 0xd5, 0x00, 0x10, 0x00, 0x00, // IID468 - 0xd5, 0x5d, 0x6b, 0xe1, 0x10, // IID469 - 0xd5, 0x9d, 0xa4, 0xeb, 0x10, // IID470 - 0x4d, 0x0f, 0xac, 0xd0, 0x10, // IID471 - 0x62, 0xd4, 0x3c, 0x18, 0x8f, 0xc6, // IID472 - 0x62, 0xfc, 0xe4, 0x18, 0x8f, 0xc2, // IID473 - 0x62, 0xfc, 0x64, 0x10, 0xff, 0xf7, // IID474 - 0x62, 0xd4, 0xe4, 0x18, 0xff, 0xf4, // IID475 - 0xd5, 0xad, 0xb6, 0x8c, 0xfe, 0xba, 0xd9, 0x72, 0xbd, // IID476 - 0xd5, 0xcd, 0xb7, 0xa4, 0x89, 0x9f, 0xe9, 0x9e, 0x8d, // IID477 - 0xd5, 0xb9, 0xbe, 0x9c, 0xa8, 0x90, 0xe9, 0x6b, 0x3a, // IID478 - 0xd5, 0xda, 0xbf, 0x84, 0x16, 0xdd, 0x8b, 0xef, 0x07, // IID479 - 0xd5, 0xcd, 0xb6, 0xe6, // IID480 - 0xd5, 0x9d, 0xb7, 0xec, // IID481 - 0x4c, 0x0f, 0xbe, 0xda, // IID482 - 0xd5, 0x9d, 0xbf, 0xe2, // IID483 - 0xd5, 0xc9, 0xb1, 0xa2, 0x26, 0x57, 0x2d, 0xf4, // IID484 - 0x62, 0xd4, 0xfc, 0x08, 0xf7, 0xff, // IID485 - 0x62, 0xfc, 0xfc, 0x0c, 0xf7, 0xff, // IID486 - 0x62, 0xd4, 0xfc, 0x08, 0xf7, 0xf6, // IID487 - 0x62, 0xd4, 0xfc, 0x0c, 0xf7, 0xf6, // IID488 - 0x62, 0xd4, 0xfc, 0x08, 0xf7, 0xef, // IID489 - 0x62, 0xfc, 0xfc, 0x0c, 0xf7, 0xec, // IID490 - 0x62, 0xf4, 0xfc, 0x08, 0xf7, 0xe1, // IID491 - 0x62, 0xfc, 0xfc, 0x0c, 0xf7, 0xe5, // IID492 - 0x62, 0xbc, 0xfc, 0x08, 0xf7, 0xa4, 0xd0, 0x1e, 0xac, 0x66, 0x5f, // IID493 - 0x62, 0xfc, 0xf8, 0x0c, 0xf7, 0xa4, 0xf5, 0x83, 0x7f, 0x43, 0xf4, // IID494 - 0x62, 0xcc, 0xfc, 0x08, 0xaf, 0xf2, // IID495 - 0x62, 0x6c, 0xfc, 0x0c, 0xaf, 0xcd, // IID496 - 0x62, 0xc4, 0xfc, 0x08, 0xf5, 0xe5, // IID497 - 0x62, 0x6c, 0xfc, 0x0c, 0xf5, 0xcb, // IID498 - 0x62, 0xdc, 0xd4, 0x10, 0xf7, 0xde, // IID499 - 0x62, 0xd4, 0x94, 0x14, 0xf7, 0xdb, // IID500 - 0x62, 0xd4, 0xcc, 0x10, 0xf7, 0xd0, // IID501 - 0x62, 0x7c, 0xfc, 0x08, 0x88, 0xe3, // IID502 - 0x62, 0x6c, 0xfc, 0x0c, 0x88, 0xef, // IID503 - 0x62, 0xdc, 0x9c, 0x10, 0xd3, 0xc0, // IID504 - 0x62, 0xfc, 0xec, 0x1c, 0xd3, 0xc4, // IID505 - 0x62, 0xdc, 0xe4, 0x18, 0xd3, 0xce, // IID506 - 0x62, 0xd4, 0xac, 0x1c, 0xd3, 0xcf, // IID507 - 0x62, 0xd4, 0xf4, 0x10, 0xd3, 0xe5, // IID508 - 0x62, 0xdc, 0xd4, 0x14, 0xd3, 0xe0, // IID509 - 0x62, 0xd4, 0x84, 0x10, 0xd3, 0xfc, // IID510 - 0x62, 0xdc, 0xec, 0x1c, 0xd3, 0xf8, // IID511 - 0x62, 0xdc, 0xd4, 0x10, 0xff, 0xc8, // IID512 - 0x62, 0xdc, 0x84, 0x1c, 0xff, 0xcf, // IID513 - 0x62, 0xf4, 0xac, 0x18, 0xff, 0xc3, // IID514 - 0x62, 0xd4, 0xec, 0x14, 0xff, 0xc0, // IID515 - 0x62, 0xdc, 0xac, 0x18, 0xd3, 0xe2, // IID516 - 0x62, 0xd4, 0x9c, 0x14, 0xd3, 0xe6, // IID517 - 0x62, 0xfc, 0xac, 0x18, 0xd3, 0xeb, // IID518 - 0x62, 0xfc, 0x9c, 0x14, 0xd3, 0xed, // IID519 - 0x62, 0xec, 0xfc, 0x08, 0xf4, 0xee, // IID520 - 0x62, 0xec, 0xfc, 0x0c, 0xf4, 0xc7, // IID521 - 0x62, 0x3c, 0xfc, 0x08, 0xaf, 0x9c, 0x8a, 0x5f, 0x7a, 0xdd, 0xec, // IID522 - 0x62, 0x1c, 0xfc, 0x0c, 0xaf, 0xac, 0xf8, 0xa0, 0x0c, 0xf5, 0x48, // IID523 - 0x62, 0x54, 0xfc, 0x08, 0xf5, 0x8d, 0x0e, 0xcf, 0x15, 0x21, // IID524 - 0x62, 0x4c, 0xfc, 0x0c, 0xf5, 0x9e, 0xbb, 0xab, 0x9c, 0x04, // IID525 - 0x62, 0x94, 0xd0, 0x10, 0xf7, 0x9c, 0xbd, 0xd2, 0xf4, 0xa8, 0x50, // IID526 - 0x62, 0xfc, 0xc8, 0x14, 0xf7, 0x9c, 0x62, 0xb4, 0xa7, 0x5f, 0xa2, // IID527 - 0x62, 0x74, 0xf8, 0x08, 0x88, 0xb4, 0xb3, 0x2f, 0xb6, 0x9c, 0x9f, // IID528 - 0x62, 0x6c, 0xf8, 0x0c, 0x88, 0x94, 0xf7, 0xdd, 0x93, 0x39, 0x8d, // IID529 - 0x62, 0xd4, 0xac, 0x10, 0xd3, 0xa1, 0x09, 0xba, 0x4a, 0x33, // IID530 - 0x62, 0x94, 0xb0, 0x1c, 0xd3, 0xa4, 0xf1, 0xfe, 0x9e, 0x65, 0xde, // IID531 - 0x62, 0xfc, 0xb4, 0x10, 0xd3, 0xbc, 0x24, 0x4f, 0x45, 0xce, 0xde, // IID532 - 0x62, 0xdc, 0xf8, 0x14, 0xd3, 0xbc, 0x44, 0xb9, 0x83, 0xc4, 0x48, // IID533 - 0x62, 0xd4, 0x88, 0x10, 0xff, 0x8c, 0x01, 0xb1, 0x17, 0x73, 0xf7, // IID534 - 0x62, 0x9c, 0xa0, 0x1c, 0xff, 0x8c, 0xae, 0xd0, 0x8f, 0xeb, 0x3e, // IID535 - 0x62, 0x9c, 0xac, 0x10, 0xff, 0x84, 0xd5, 0x2e, 0x82, 0xf4, 0x3e, // IID536 - 0x62, 0xfc, 0x90, 0x14, 0xff, 0x84, 0xa3, 0x47, 0xc2, 0xf0, 0xc0, // IID537 - 0x62, 0xdc, 0xb8, 0x18, 0xd3, 0xac, 0x26, 0x17, 0x6a, 0xb5, 0x15, // IID538 - 0x62, 0xd4, 0xac, 0x14, 0xd3, 0xab, 0x9f, 0x9a, 0x17, 0xd2, // IID539 - 0x62, 0x34, 0xf8, 0x08, 0xf4, 0x9c, 0x71, 0x3e, 0x4e, 0x00, 0xcd, // IID540 - 0x62, 0x84, 0xfc, 0x0c, 0xf4, 0xbc, 0x61, 0x97, 0xc1, 0x7d, 0xab, // IID541 - 0x62, 0x54, 0xdc, 0x10, 0x01, 0xbc, 0xcd, 0xf3, 0x93, 0xee, 0xb9, // IID542 - 0x62, 0xc4, 0x90, 0x1c, 0x01, 0x84, 0x79, 0xfb, 0x89, 0x93, 0xd7, // IID543 - 0x62, 0x4c, 0xd0, 0x10, 0x21, 0xac, 0x0e, 0xb2, 0x30, 0x4e, 0x0f, // IID544 - 0x62, 0xac, 0x88, 0x14, 0x21, 0x8c, 0x39, 0xc4, 0xde, 0xb9, 0x3a, // IID545 - 0x62, 0x0c, 0xa8, 0x18, 0x09, 0xa4, 0x73, 0x9a, 0xed, 0x80, 0xe6, // IID546 - 0x62, 0x1c, 0xb0, 0x1c, 0x09, 0x9c, 0x35, 0xf8, 0x64, 0x15, 0xdb, // IID547 - 0x62, 0xc4, 0x84, 0x18, 0x29, 0x86, 0x70, 0x40, 0xbb, 0xb0, // IID548 - 0x62, 0x6c, 0xf0, 0x1c, 0x29, 0xa4, 0x55, 0x71, 0x53, 0x2f, 0xee, // IID549 - 0x62, 0x7c, 0xe0, 0x10, 0x31, 0x84, 0x13, 0x14, 0xaa, 0xa1, 0xf5, // IID550 - 0x62, 0xac, 0x98, 0x14, 0x31, 0x84, 0x61, 0x20, 0xd0, 0x4b, 0x91, // IID551 - 0x62, 0xfc, 0xf4, 0x10, 0x81, 0x82, 0xfb, 0xee, 0x54, 0x9f, 0x00, 0x00, 0x00, 0x01, // IID552 - 0x62, 0xbc, 0xb0, 0x14, 0x81, 0x84, 0x0b, 0xd9, 0x44, 0x24, 0x12, 0x00, 0x00, 0x01, 0x00, // IID553 - 0x62, 0x94, 0x88, 0x10, 0x81, 0xa4, 0x61, 0x0d, 0xf3, 0x4f, 0xda, 0x00, 0x10, 0x00, 0x00, // IID554 - 0x62, 0xfc, 0xb4, 0x1c, 0x81, 0xa4, 0x5e, 0xda, 0xaf, 0xb9, 0x81, 0x00, 0x00, 0x00, 0x10, // IID555 - 0x62, 0x1c, 0xf8, 0x08, 0x6b, 0xa4, 0x49, 0x34, 0x97, 0xd2, 0xbc, 0x01, // IID556 - 0x62, 0x3c, 0xf8, 0x0c, 0x6b, 0xbc, 0xf9, 0xa2, 0xa9, 0x68, 0xd4, 0x10, // IID557 - 0x62, 0xb4, 0x98, 0x10, 0x81, 0x8c, 0x3a, 0xb1, 0x63, 0x13, 0x3f, 0x00, 0x01, 0x00, 0x00, // IID558 - 0x62, 0xd4, 0xf8, 0x14, 0x81, 0x8c, 0xfc, 0xc4, 0x79, 0x7a, 0xe8, 0x00, 0x00, 0x00, 0x01, // IID559 - 0x62, 0x94, 0xb8, 0x18, 0xc1, 0xa4, 0x86, 0x5b, 0x6f, 0xbd, 0x8e, 0x02, // IID560 - 0x62, 0x94, 0xbc, 0x1c, 0xc1, 0xa4, 0xb7, 0x43, 0x32, 0xf1, 0x21, 0x10, // IID561 - 0x62, 0x94, 0xa8, 0x18, 0xc1, 0xbc, 0x2d, 0x72, 0xcb, 0x04, 0x7d, 0x02, // IID562 - 0x62, 0xbc, 0xa0, 0x1c, 0xc1, 0xbc, 0xfd, 0x24, 0x4b, 0x89, 0xde, 0x08, // IID563 - 0x62, 0xbc, 0xf4, 0x18, 0xc1, 0xac, 0x60, 0x38, 0x9a, 0x0c, 0x26, 0x04, // IID564 - 0x62, 0x9c, 0xcc, 0x14, 0xc1, 0xac, 0x0a, 0x9e, 0x44, 0xa9, 0xa1, 0x08, // IID565 - 0x62, 0xb4, 0x80, 0x10, 0x83, 0xac, 0x63, 0x10, 0xbb, 0x00, 0x2b, 0x01, // IID566 - 0x62, 0xdc, 0xd4, 0x14, 0x81, 0xaf, 0x53, 0x0b, 0xef, 0x93, 0x00, 0x10, 0x00, 0x00, // IID567 - 0x62, 0xbc, 0xa0, 0x18, 0x81, 0xb4, 0x77, 0x6b, 0x02, 0xa6, 0x51, 0x00, 0x00, 0x01, 0x00, // IID568 - 0x62, 0x9c, 0x8c, 0x1c, 0x83, 0xb4, 0x93, 0x55, 0x64, 0x52, 0xcb, 0x10, // IID569 - 0x62, 0xfc, 0xdc, 0x10, 0x81, 0xc7, 0x00, 0x00, 0x00, 0x01, // IID570 - 0x62, 0xfc, 0xb4, 0x1c, 0x81, 0xc5, 0x00, 0x10, 0x00, 0x00, // IID571 - 0x62, 0xf4, 0xdc, 0x10, 0x83, 0xe2, 0x10, // IID572 - 0x62, 0xfc, 0x8c, 0x1c, 0x83, 0xe3, 0x10, // IID573 - 0x62, 0x6c, 0xfc, 0x08, 0x6b, 0xd9, 0x10, // IID574 - 0x62, 0x44, 0xfc, 0x0c, 0x69, 0xf5, 0x00, 0x01, 0x00, 0x00, // IID575 - 0x62, 0xd4, 0xe4, 0x10, 0x81, 0xcf, 0x00, 0x00, 0x00, 0x01, // IID576 - 0x62, 0xdc, 0xfc, 0x14, 0x81, 0xcc, 0x00, 0x00, 0x00, 0x10, // IID577 - 0x62, 0xdc, 0xe4, 0x18, 0xc1, 0xd0, 0x02, // IID578 - 0x62, 0xfc, 0x84, 0x18, 0xc1, 0xc4, 0x10, // IID579 - 0x62, 0xf4, 0xa4, 0x1c, 0xc1, 0xc1, 0x10, // IID580 - 0x62, 0xdc, 0x94, 0x18, 0xc1, 0xca, 0x10, // IID581 - 0x62, 0xfc, 0xe4, 0x14, 0xc1, 0xcc, 0x04, // IID582 - 0x62, 0xdc, 0xe4, 0x10, 0xc1, 0xe4, 0x10, // IID583 - 0x62, 0xfc, 0xb4, 0x14, 0xc1, 0xe2, 0x04, // IID584 - 0x62, 0xdc, 0xac, 0x18, 0xc1, 0xfb, 0x04, // IID585 - 0x62, 0xfc, 0xec, 0x1c, 0xc1, 0xfe, 0x08, // IID586 - 0x62, 0xd4, 0x9c, 0x10, 0xd1, 0xe7, // IID587 - 0x62, 0xd4, 0xe4, 0x1c, 0xc1, 0xe4, 0x04, // IID588 - 0x62, 0xd4, 0xac, 0x10, 0xd1, 0xeb, // IID589 - 0x62, 0xdc, 0xec, 0x1c, 0xc1, 0xef, 0x08, // IID590 - 0x62, 0xf4, 0xd4, 0x10, 0x81, 0xeb, 0x00, 0x00, 0x10, 0x00, // IID591 - 0x62, 0xdc, 0xb4, 0x14, 0x81, 0xec, 0x00, 0x00, 0x01, 0x00, // IID592 - 0x62, 0xd4, 0xcc, 0x10, 0x83, 0xf6, 0x01, // IID593 - 0x62, 0xdc, 0xa4, 0x1c, 0x81, 0xf6, 0x00, 0x00, 0x10, 0x00, // IID594 - 0x62, 0xfc, 0xdc, 0x10, 0x81, 0xcb, 0x00, 0x00, 0x10, 0x00, // IID595 - 0x62, 0xd4, 0xb4, 0x10, 0x81, 0xcd, 0x00, 0x00, 0x00, 0x10, // IID596 - 0x62, 0xdc, 0xb4, 0x10, 0x81, 0xe9, 0x00, 0x00, 0x00, 0x10, // IID597 - 0x62, 0xd4, 0xec, 0x14, 0x81, 0xeb, 0x00, 0x00, 0x40, 0x00, // IID598 - 0x62, 0xec, 0xac, 0x18, 0x03, 0x94, 0x24, 0x53, 0xf4, 0x56, 0x07, // IID599 - 0x62, 0x6c, 0xe0, 0x1c, 0x03, 0x9c, 0x2e, 0x49, 0x15, 0x54, 0xda, // IID600 - 0x62, 0x44, 0xe8, 0x18, 0x23, 0xbc, 0xe1, 0x64, 0x1c, 0x30, 0xfb, // IID601 - 0x62, 0x04, 0xf8, 0x14, 0x23, 0x8c, 0x1e, 0xd9, 0x54, 0x66, 0x7c, // IID602 - 0x62, 0xd4, 0x90, 0x10, 0x0b, 0x8c, 0x3f, 0x2d, 0xf7, 0xb7, 0x45, // IID603 - 0x62, 0xc4, 0xe0, 0x14, 0x0b, 0x8c, 0x75, 0x6a, 0xe6, 0xf3, 0x8a, // IID604 - 0x62, 0x5c, 0x90, 0x18, 0xaf, 0x84, 0x7f, 0x4e, 0x49, 0xee, 0xdd, // IID605 - 0x62, 0x04, 0xa4, 0x1c, 0xaf, 0xa4, 0xdd, 0xab, 0x13, 0x00, 0x5c, // IID606 - 0x62, 0xec, 0xec, 0x18, 0x2b, 0x94, 0x0a, 0x71, 0x7e, 0x55, 0x59, // IID607 - 0x62, 0x7c, 0xa4, 0x14, 0x2b, 0x9e, 0xb7, 0x69, 0xb9, 0xd7, // IID608 - 0x62, 0x5c, 0xac, 0x18, 0x33, 0x88, 0x54, 0x1d, 0x69, 0x49, // IID609 - 0x62, 0x7c, 0xbc, 0x14, 0x33, 0xa3, 0xaa, 0x29, 0xd5, 0x22, // IID610 - 0x62, 0x54, 0xdc, 0x10, 0x03, 0xca, // IID611 - 0x62, 0xcc, 0xec, 0x14, 0x03, 0xca, // IID612 - 0x62, 0xec, 0xd5, 0x10, 0x66, 0xc3, // IID613 - 0x62, 0x5c, 0xe6, 0x18, 0x66, 0xf3, // IID614 - 0x62, 0x7c, 0xb4, 0x18, 0x23, 0xe6, // IID615 - 0x62, 0x44, 0xf4, 0x14, 0x23, 0xca, // IID616 - 0x62, 0x54, 0x9c, 0x18, 0xaf, 0xfe, // IID617 - 0x62, 0xec, 0x94, 0x14, 0xaf, 0xd0, // IID618 - 0x62, 0x54, 0xa4, 0x18, 0x0b, 0xca, // IID619 - 0x62, 0x7c, 0xb4, 0x14, 0x0b, 0xe8, // IID620 - 0x62, 0xcc, 0xa4, 0x18, 0x2b, 0xe9, // IID621 - 0x62, 0xe4, 0xec, 0x1c, 0x2b, 0xe3, // IID622 - 0x62, 0xcc, 0xb4, 0x10, 0x33, 0xea, // IID623 - 0x62, 0x6c, 0xc4, 0x14, 0x33, 0xdd, // IID624 - 0x62, 0x44, 0xac, 0x18, 0x24, 0xfc, 0x02, // IID625 - 0x62, 0x6c, 0xc4, 0x14, 0x24, 0xe8, 0x02, // IID626 - 0x62, 0xcc, 0xe4, 0x10, 0x2c, 0xf8, 0x04, // IID627 - 0x62, 0x44, 0xd4, 0x14, 0x2c, 0xcf, 0x04, // IID628 - 0x62, 0x64, 0xb4, 0x18, 0x40, 0xea, // IID629 - 0x62, 0x6c, 0xa4, 0x18, 0x41, 0xcb, // IID630 - 0x62, 0xec, 0xac, 0x18, 0x42, 0xc1, // IID631 - 0x62, 0xcc, 0xbc, 0x18, 0x43, 0xff, // IID632 - 0x62, 0x64, 0xb4, 0x18, 0x44, 0xfb, // IID633 - 0x62, 0x44, 0xfc, 0x10, 0x45, 0xe9, // IID634 - 0x62, 0x54, 0xbc, 0x10, 0x46, 0xd1, // IID635 - 0x62, 0x4c, 0xcc, 0x10, 0x47, 0xe2, // IID636 - 0x62, 0x6c, 0xec, 0x10, 0x48, 0xcc, // IID637 - 0x62, 0xe4, 0xfc, 0x10, 0x49, 0xeb, // IID638 - 0x62, 0xec, 0x9c, 0x10, 0x4a, 0xf3, // IID639 - 0x62, 0x74, 0x94, 0x18, 0x4b, 0xfa, // IID640 - 0x62, 0xc4, 0xbc, 0x18, 0x4c, 0xf6, // IID641 - 0x62, 0x44, 0x9c, 0x18, 0x4d, 0xc6, // IID642 - 0x62, 0x7c, 0xbc, 0x10, 0x4e, 0xed, // IID643 - 0x62, 0xdc, 0xe4, 0x18, 0x4f, 0xdb, // IID644 - 0x62, 0x8c, 0x88, 0x18, 0x40, 0x8c, 0xd8, 0xf0, 0x08, 0xd5, 0x09, // IID645 - 0x62, 0x5c, 0x90, 0x18, 0x41, 0xbc, 0xaf, 0x4a, 0xc7, 0xf2, 0x6e, // IID646 - 0x62, 0x0c, 0x90, 0x18, 0x42, 0x9c, 0x4f, 0xab, 0xe9, 0x4f, 0x73, // IID647 - 0x62, 0x84, 0x80, 0x18, 0x43, 0xb4, 0xae, 0x05, 0x42, 0x27, 0x98, // IID648 - 0x62, 0x84, 0x88, 0x10, 0x44, 0xbc, 0x67, 0xe7, 0x9d, 0x97, 0xfd, // IID649 - 0x62, 0x14, 0x98, 0x18, 0x45, 0x8c, 0xc9, 0x6b, 0xab, 0x2a, 0x05, // IID650 - 0x62, 0x04, 0xb4, 0x18, 0x46, 0x8c, 0xc0, 0x6b, 0x42, 0xbd, 0xe1, // IID651 - 0x62, 0xcc, 0xf4, 0x18, 0x47, 0xa4, 0x9b, 0x58, 0x3c, 0x82, 0x46, // IID652 - 0x62, 0x7c, 0xe4, 0x18, 0x48, 0xa5, 0x38, 0x47, 0xca, 0xf9, // IID653 - 0x62, 0x9c, 0xc0, 0x10, 0x49, 0x9c, 0xd3, 0xc0, 0xbc, 0x22, 0x09, // IID654 - 0x62, 0x7c, 0xb4, 0x10, 0x4a, 0x8f, 0xec, 0x14, 0x2a, 0x0d, // IID655 - 0x62, 0xc4, 0xa4, 0x18, 0x4b, 0x9b, 0x63, 0xa5, 0x46, 0xf0, // IID656 - 0x62, 0xcc, 0x90, 0x18, 0x4c, 0x94, 0x1c, 0x7e, 0x9b, 0x6b, 0x71, // IID657 - 0x62, 0xa4, 0xd0, 0x10, 0x4d, 0x84, 0x29, 0xe2, 0xbb, 0x0f, 0xa5, // IID658 - 0x62, 0x2c, 0x98, 0x18, 0x4e, 0xbc, 0x14, 0xb1, 0x7f, 0x0b, 0x0e, // IID659 - 0x62, 0x4c, 0x84, 0x18, 0x4f, 0x86, 0x4f, 0x7b, 0x3b, 0x2d, // IID660 + 0x62, 0xd4, 0x7c, 0x18, 0x81, 0xc3, 0x00, 0x00, 0x01, 0x00, // IID255 + 0x62, 0xfc, 0x3c, 0x14, 0x81, 0xc0, 0x00, 0x00, 0x00, 0x10, // IID256 + 0x62, 0xfc, 0x7c, 0x1c, 0x81, 0xc2, 0x00, 0x00, 0x00, 0x10, // IID257 + 0x62, 0xd4, 0x14, 0x10, 0x83, 0xe5, 0x01, // IID258 + 0x62, 0xd4, 0x7c, 0x18, 0x83, 0xe5, 0x01, // IID259 + 0x62, 0xfc, 0x04, 0x14, 0x83, 0xe6, 0x01, // IID260 + 0x62, 0xdc, 0x7c, 0x1c, 0x83, 0xe5, 0x01, // IID261 + 0x62, 0xcc, 0x7c, 0x08, 0x69, 0xfd, 0x00, 0x00, 0x01, 0x00, // IID262 + 0x62, 0xd4, 0x7c, 0x08, 0x69, 0xc7, 0x00, 0x00, 0x01, 0x00, // IID263 + 0x62, 0xc4, 0x7c, 0x0c, 0x69, 0xe9, 0x00, 0x00, 0x00, 0x10, // IID264 + 0x62, 0xd4, 0x7c, 0x0c, 0x69, 0xc7, 0x00, 0x00, 0x00, 0x10, // IID265 + 0x62, 0xfc, 0x6c, 0x18, 0x81, 0xca, 0x00, 0x00, 0x01, 0x00, // IID266 + 0x62, 0xd4, 0x7c, 0x18, 0x81, 0xcf, 0x00, 0x00, 0x01, 0x00, // IID267 + 0x62, 0xd4, 0x3c, 0x1c, 0x81, 0xc9, 0x00, 0x01, 0x00, 0x00, // IID268 + 0x62, 0xdc, 0x7c, 0x1c, 0x81, 0xcb, 0x00, 0x01, 0x00, 0x00, // IID269 + 0x62, 0xd4, 0x34, 0x18, 0xc1, 0xd7, 0x08, // IID270 + 0x62, 0xfc, 0x7c, 0x18, 0xc1, 0xd2, 0x08, // IID271 + 0x62, 0xf4, 0x1c, 0x18, 0xc1, 0xc3, 0x10, // IID272 + 0x62, 0xfc, 0x7c, 0x18, 0xc1, 0xc3, 0x10, // IID273 + 0x62, 0xd4, 0x2c, 0x1c, 0xc1, 0xc3, 0x10, // IID274 + 0x62, 0xfc, 0x7c, 0x1c, 0xc1, 0xc2, 0x10, // IID275 + 0x62, 0xd4, 0x6c, 0x18, 0xd1, 0xce, // IID276 + 0x62, 0xfc, 0x7c, 0x18, 0xd1, 0xce, // IID277 + 0x62, 0xdc, 0x34, 0x14, 0xc1, 0xcf, 0x10, // IID278 + 0x62, 0xfc, 0x7c, 0x1c, 0xc1, 0xcb, 0x10, // IID279 + 0x62, 0xd4, 0x34, 0x18, 0xc1, 0xe7, 0x02, // IID280 + 0x62, 0xd4, 0x7c, 0x18, 0xc1, 0xe5, 0x02, // IID281 + 0x62, 0xfc, 0x54, 0x14, 0xd1, 0xe0, // IID282 + 0x62, 0xfc, 0x7c, 0x1c, 0xd1, 0xe5, // IID283 + 0x62, 0xfc, 0x2c, 0x10, 0xc1, 0xff, 0x08, // IID284 + 0x62, 0xdc, 0x7c, 0x18, 0xc1, 0xfc, 0x08, // IID285 + 0x62, 0xd4, 0x2c, 0x14, 0xc1, 0xfe, 0x04, // IID286 + 0x62, 0xd4, 0x7c, 0x1c, 0xc1, 0xfa, 0x04, // IID287 + 0x62, 0xd4, 0x4c, 0x10, 0xd1, 0xe1, // IID288 + 0x62, 0xfc, 0x7c, 0x18, 0xd1, 0xe2, // IID289 + 0x62, 0xdc, 0x0c, 0x14, 0xc1, 0xe0, 0x10, // IID290 + 0x62, 0xfc, 0x7c, 0x1c, 0xc1, 0xe7, 0x10, // IID291 + 0x62, 0xd4, 0x24, 0x18, 0xc1, 0xe8, 0x10, // IID292 + 0x62, 0xfc, 0x7c, 0x18, 0xc1, 0xe8, 0x10, // IID293 + 0x62, 0xd4, 0x24, 0x1c, 0xc1, 0xec, 0x08, // IID294 + 0x62, 0xdc, 0x7c, 0x1c, 0xc1, 0xed, 0x08, // IID295 + 0x62, 0xfc, 0x7c, 0x10, 0x81, 0xed, 0x00, 0x00, 0x10, 0x00, // IID296 + 0x62, 0xd4, 0x7c, 0x18, 0x81, 0xef, 0x00, 0x00, 0x10, 0x00, // IID297 + 0x62, 0xfc, 0x34, 0x1c, 0x81, 0xea, 0x00, 0x00, 0x00, 0x01, // IID298 +#endif // _LP64 + 0x62, 0xf4, 0x7c, 0x1c, 0x81, 0xeb, 0x00, 0x00, 0x00, 0x01, // IID299 +#ifdef _LP64 + 0x62, 0xfc, 0x64, 0x10, 0x81, 0xf7, 0x00, 0x00, 0x01, 0x00, // IID300 + 0x62, 0xfc, 0x7c, 0x18, 0x81, 0xf1, 0x00, 0x00, 0x01, 0x00, // IID301 + 0x62, 0xfc, 0x14, 0x14, 0x81, 0xf2, 0x00, 0x00, 0x10, 0x00, // IID302 + 0x62, 0xd4, 0x7c, 0x1c, 0x81, 0xf6, 0x00, 0x00, 0x10, 0x00, // IID303 + 0x62, 0xd4, 0x64, 0x10, 0x81, 0xef, 0x00, 0x00, 0x00, 0x01, // IID304 + 0x62, 0xdc, 0x7c, 0x18, 0x81, 0xeb, 0x00, 0x00, 0x00, 0x01, // IID305 + 0x62, 0xdc, 0x44, 0x14, 0x81, 0xeb, 0x00, 0x00, 0x00, 0x40, // IID306 + 0x62, 0xfc, 0x7c, 0x1c, 0x81, 0xef, 0x00, 0x00, 0x00, 0x40, // IID307 + 0x62, 0x1c, 0x38, 0x18, 0x03, 0xa4, 0xc4, 0x98, 0x81, 0x92, 0x92, // IID308 + 0x62, 0x1c, 0x38, 0x14, 0x03, 0xac, 0xc8, 0xfd, 0x73, 0x46, 0x78, // IID309 + 0x62, 0x84, 0x3c, 0x10, 0x23, 0xac, 0xa8, 0x77, 0xc7, 0x99, 0x9c, // IID310 + 0x62, 0x4c, 0x1c, 0x1c, 0x23, 0x86, 0xaa, 0x9a, 0xad, 0x98, // IID311 + 0x62, 0x34, 0x10, 0x18, 0xaf, 0xac, 0x8b, 0x27, 0xb2, 0xc6, 0xa0, // IID312 + 0x62, 0x4c, 0x2c, 0x14, 0xaf, 0x8c, 0xd1, 0x66, 0x08, 0xc6, 0xd1, // IID313 + 0x62, 0x34, 0x18, 0x10, 0x0b, 0x84, 0xc2, 0xac, 0x65, 0x26, 0xf1, // IID314 + 0x62, 0xcc, 0x00, 0x14, 0x0b, 0xb4, 0xe6, 0xbd, 0x1c, 0xc4, 0x3a, // IID315 + 0x62, 0x44, 0x38, 0x10, 0x2b, 0xb4, 0x4d, 0xe3, 0xc2, 0xfd, 0x1e, // IID316 + 0x62, 0x84, 0x7c, 0x14, 0x2b, 0x84, 0x79, 0x34, 0xeb, 0x9f, 0x76, // IID317 + 0x62, 0x44, 0x64, 0x10, 0x33, 0x8a, 0x29, 0xb4, 0x39, 0x22, // IID318 + 0x62, 0xac, 0x30, 0x14, 0x33, 0x9c, 0x40, 0xea, 0xfa, 0x71, 0x1c, // IID319 + 0x62, 0x5c, 0x64, 0x10, 0x32, 0x94, 0x24, 0x03, 0xf3, 0x65, 0xd6, // IID320 + 0x62, 0x2c, 0x60, 0x1c, 0x32, 0xa4, 0x47, 0x27, 0x22, 0x87, 0xa2, // IID321 + 0x62, 0x14, 0x29, 0x18, 0x33, 0x8c, 0xb5, 0x88, 0x11, 0x15, 0x11, // IID322 + 0x62, 0xa4, 0x79, 0x14, 0x33, 0x8c, 0x3a, 0xe7, 0x6c, 0x93, 0x61, // IID323 + 0x62, 0xdc, 0x14, 0x18, 0x03, 0xdc, // IID324 + 0x62, 0x6c, 0x64, 0x1c, 0x03, 0xee, // IID325 + 0x62, 0x54, 0x64, 0x18, 0x23, 0xc0, // IID326 + 0x62, 0xc4, 0x24, 0x1c, 0x23, 0xc5, // IID327 + 0x62, 0x7c, 0x1c, 0x18, 0xaf, 0xf9, // IID328 + 0x62, 0x6c, 0x44, 0x14, 0xaf, 0xfc, // IID329 + 0x62, 0x44, 0x4d, 0x10, 0x0b, 0xd2, // IID330 + 0x62, 0xc4, 0x35, 0x14, 0x0b, 0xdb, // IID331 + 0x62, 0x44, 0x64, 0x10, 0x0b, 0xf0, // IID332 + 0x62, 0x74, 0x1c, 0x1c, 0x0b, 0xd2, // IID333 + 0x62, 0x6c, 0x4c, 0x10, 0xa5, 0xf4, // IID334 + 0x62, 0xec, 0x6c, 0x14, 0xa5, 0xd3, // IID335 + 0x62, 0xfc, 0x34, 0x10, 0xad, 0xca, // IID336 + 0x62, 0x6c, 0x64, 0x14, 0xad, 0xc8, // IID337 + 0x62, 0x4c, 0x24, 0x18, 0x2b, 0xf8, // IID338 + 0x62, 0x6c, 0x0c, 0x1c, 0x2b, 0xf0, // IID339 + 0x62, 0x5c, 0x34, 0x18, 0x33, 0xda, // IID340 + 0x62, 0xdc, 0x24, 0x14, 0x33, 0xd7, // IID341 + 0x62, 0xd4, 0x14, 0x10, 0x24, 0xca, 0x10, // IID342 + 0x62, 0xec, 0x04, 0x1c, 0x24, 0xcf, 0x10, // IID343 + 0x62, 0x54, 0x24, 0x10, 0x2c, 0xfd, 0x08, // IID344 + 0x62, 0x4c, 0x04, 0x1c, 0x2c, 0xd5, 0x10, // IID345 + 0x62, 0x54, 0x6c, 0x10, 0x40, 0xc9, // IID346 + 0x62, 0x6c, 0x4c, 0x10, 0x41, 0xf7, // IID347 + 0x62, 0xc4, 0x24, 0x18, 0x42, 0xe3, // IID348 + 0x62, 0x6c, 0x64, 0x18, 0x43, 0xe0, // IID349 + 0x62, 0xcc, 0x5c, 0x10, 0x44, 0xc8, // IID350 + 0x62, 0xc4, 0x4c, 0x10, 0x45, 0xc7, // IID351 + 0x62, 0x4c, 0x04, 0x18, 0x46, 0xe5, // IID352 + 0x62, 0x4c, 0x7c, 0x10, 0x47, 0xc9, // IID353 + 0x62, 0x7c, 0x74, 0x10, 0x48, 0xe9, // IID354 + 0x62, 0xdc, 0x44, 0x10, 0x49, 0xde, // IID355 + 0x62, 0xc4, 0x04, 0x18, 0x4a, 0xf3, // IID356 + 0x62, 0xfc, 0x24, 0x10, 0x4b, 0xd6, // IID357 + 0x62, 0xcc, 0x34, 0x18, 0x4c, 0xcc, // IID358 + 0x62, 0x5c, 0x3c, 0x10, 0x4d, 0xda, // IID359 + 0x62, 0xf4, 0x1c, 0x18, 0x4e, 0xcb, // IID360 + 0x62, 0xec, 0x1c, 0x10, 0x4f, 0xf6, // IID361 + 0x62, 0x74, 0x28, 0x18, 0x40, 0xb4, 0xc9, 0xc3, 0x4d, 0xa8, 0x87, // IID362 + 0x62, 0x1c, 0x70, 0x10, 0x41, 0xa4, 0xc2, 0x23, 0x22, 0x64, 0x10, // IID363 + 0x62, 0x5c, 0x2c, 0x10, 0x42, 0x87, 0x1c, 0xd4, 0xd2, 0xf4, // IID364 + 0x62, 0xc4, 0x18, 0x18, 0x43, 0xa4, 0xb4, 0xd5, 0x08, 0x80, 0x99, // IID365 + 0x62, 0x5c, 0x48, 0x10, 0x44, 0x8c, 0xbb, 0x22, 0x4d, 0xce, 0x66, // IID366 + 0x62, 0x1c, 0x18, 0x18, 0x45, 0x84, 0xde, 0x1f, 0x89, 0x69, 0xd4, // IID367 + 0x62, 0x84, 0x70, 0x10, 0x46, 0xa4, 0xf1, 0x21, 0xdd, 0xef, 0xca, // IID368 + 0x62, 0x54, 0x6c, 0x18, 0x47, 0x86, 0x59, 0x7a, 0x6b, 0x3d, // IID369 + 0x62, 0x04, 0x74, 0x18, 0x48, 0xbc, 0xb3, 0xf2, 0x85, 0xd5, 0x2c, // IID370 + 0x62, 0x8c, 0x34, 0x10, 0x49, 0x94, 0x98, 0xcc, 0x63, 0x96, 0xc0, // IID371 + 0x62, 0x7c, 0x68, 0x10, 0x4a, 0x84, 0x8b, 0x3b, 0x5b, 0xf2, 0xc6, // IID372 + 0x62, 0x4c, 0x24, 0x18, 0x4b, 0xac, 0x95, 0x3f, 0xa9, 0x94, 0x3a, // IID373 + 0x62, 0x44, 0x10, 0x18, 0x4c, 0xac, 0x7f, 0x32, 0x35, 0xd4, 0x76, // IID374 + 0x62, 0x14, 0x04, 0x18, 0x4d, 0xa4, 0x4d, 0x5b, 0x7a, 0x6f, 0x01, // IID375 + 0x62, 0xfc, 0x30, 0x18, 0x4e, 0x94, 0x79, 0xe1, 0xbf, 0xb6, 0x43, // IID376 + 0x62, 0x8c, 0x1c, 0x10, 0x4f, 0xa4, 0x10, 0xd1, 0x7f, 0x91, 0xcd, // IID377 + 0xd5, 0x4c, 0x13, 0xd9, // IID378 + 0xd5, 0x49, 0x3b, 0xf7, // IID379 + 0xd5, 0xdd, 0xaf, 0xfe, // IID380 + 0xf3, 0xd5, 0xd8, 0xb8, 0xdb, // IID381 + 0xd5, 0x5c, 0x1b, 0xd5, // IID382 + 0xd5, 0x1d, 0x2b, 0xf2, // IID383 + 0xf3, 0xd5, 0xc9, 0xbc, 0xe7, // IID384 + 0xf3, 0x4d, 0x0f, 0xbd, 0xe5, // IID385 + 0xd5, 0x59, 0x03, 0xfc, // IID386 + 0xd5, 0x58, 0x23, 0xe4, // IID387 + 0xd5, 0x4d, 0x0b, 0xc3, // IID388 + 0x4d, 0x33, 0xd7, // IID389 + 0xd5, 0x58, 0x8b, 0xdc, // IID390 + 0xd5, 0xc9, 0xbc, 0xff, // IID391 + 0xd5, 0xdc, 0xbd, 0xd3, // IID392 + 0xd5, 0xd9, 0xa3, 0xf8, // IID393 + 0xd5, 0x4d, 0x87, 0xe3, // IID394 + 0x4d, 0x85, 0xed, // IID395 + 0xd5, 0x39, 0x01, 0x94, 0xff, 0x37, 0x04, 0xda, 0x59, // IID396 + 0xd5, 0x7c, 0x21, 0x9c, 0xe5, 0x57, 0xd5, 0xd0, 0x6f, // IID397 + 0xd5, 0x1c, 0x39, 0x9d, 0x44, 0x67, 0xef, 0x23, // IID398 + 0x49, 0x09, 0x8c, 0xca, 0xab, 0x44, 0x85, 0x7e, // IID399 + 0xd5, 0x2a, 0x31, 0x9c, 0xc1, 0x77, 0xb7, 0x35, 0x86, // IID400 + 0xd5, 0x7f, 0x29, 0x9c, 0x3b, 0x9a, 0x5f, 0xf8, 0x11, // IID401 + 0xd5, 0x78, 0x89, 0x8c, 0xc4, 0xda, 0x8d, 0x15, 0x72, // IID402 + 0xd5, 0x9f, 0xc1, 0xa4, 0x8d, 0xd1, 0xeb, 0x8f, 0x6e, // IID403 + 0x49, 0x81, 0xa7, 0x33, 0xb1, 0x36, 0xb8, 0x00, 0x00, 0x00, 0x10, // IID404 + 0xd5, 0x38, 0x81, 0x84, 0x5f, 0x3f, 0xde, 0xbf, 0x32, 0x00, 0x01, 0x00, 0x00, // IID405 + 0x4b, 0x81, 0xbc, 0xdf, 0x60, 0x75, 0x8e, 0x54, 0x00, 0x10, 0x00, 0x00, // IID406 + 0xd5, 0x1a, 0xc1, 0xbc, 0x74, 0x34, 0xfc, 0x43, 0x1b, 0x02, // IID407 + 0xd5, 0x39, 0xc1, 0xa4, 0x2a, 0x3d, 0xaf, 0x51, 0xc4, 0x08, // IID408 + 0xd5, 0x1a, 0x81, 0x9c, 0xd6, 0x03, 0x14, 0x7e, 0x04, 0x00, 0x00, 0x01, 0x00, // IID409 + 0x48, 0xc1, 0xac, 0x91, 0x4d, 0x92, 0xa3, 0x7e, 0x10, // IID410 + 0xd5, 0x2a, 0x83, 0xac, 0xd1, 0xc2, 0x5a, 0x91, 0xca, 0x10, // IID411 + 0xd5, 0x3b, 0x83, 0xb4, 0x96, 0x5c, 0x2f, 0xa1, 0x78, 0x10, // IID412 + 0x4b, 0x81, 0x8c, 0x53, 0xb5, 0xb5, 0x13, 0x37, 0x00, 0x00, 0x00, 0x10, // IID413 + 0xd5, 0x3b, 0xc7, 0x84, 0xf6, 0x10, 0x1a, 0x54, 0x02, 0x00, 0x00, 0x01, 0x00, // IID414 + 0xd5, 0x1a, 0xf7, 0x84, 0xf8, 0x51, 0x32, 0x8e, 0x55, 0xf0, 0xff, 0xff, 0xff, // IID415 + 0xd5, 0x4f, 0x03, 0x9c, 0x90, 0x2d, 0x73, 0x5f, 0x63, // IID416 + 0xd5, 0x6b, 0x23, 0xac, 0x3c, 0x60, 0x3b, 0x17, 0x8a, // IID417 + 0xd5, 0x78, 0x3b, 0x94, 0x83, 0xe2, 0x17, 0xf5, 0xed, // IID418 + 0xf3, 0xd5, 0xbb, 0xbd, 0x9c, 0x37, 0x5d, 0x26, 0xc3, 0x1e, // IID419 + 0xd5, 0x6a, 0x0b, 0x84, 0x12, 0x1b, 0x83, 0x86, 0x35, // IID420 + 0xd5, 0x1c, 0x13, 0xa2, 0x86, 0x60, 0xc1, 0xc3, // IID421 + 0xd5, 0xa9, 0xaf, 0x8c, 0xe8, 0xab, 0x15, 0x15, 0x6b, // IID422 + 0xf3, 0xd5, 0xec, 0xb8, 0xac, 0xb9, 0x4d, 0x6c, 0xf0, 0x4f, // IID423 + 0xd5, 0x5f, 0x1b, 0x94, 0x50, 0x77, 0x5e, 0x26, 0x8a, // IID424 + 0xd5, 0x48, 0x2b, 0x8c, 0x1b, 0x9c, 0xd5, 0x33, 0x40, // IID425 + 0xf3, 0xd5, 0xda, 0xbc, 0x94, 0xe6, 0x83, 0xcb, 0x6c, 0xc7, // IID426 + 0xd5, 0x3c, 0x33, 0xa4, 0xfc, 0x60, 0x15, 0x31, 0x4b, // IID427 + 0xd5, 0x6f, 0x8b, 0xac, 0xa2, 0x57, 0x26, 0x3a, 0x5c, // IID428 + 0xd5, 0x6b, 0x8d, 0xb4, 0xcd, 0x3f, 0x6f, 0x3d, 0x1a, // IID429 + 0xf2, 0xd5, 0xfe, 0x2c, 0x8c, 0xc1, 0x28, 0x24, 0x52, 0xca, // IID430 + 0xd5, 0x59, 0x87, 0x91, 0xc3, 0x84, 0x21, 0x63, // IID431 + 0xd5, 0x5e, 0x85, 0xac, 0x6a, 0x76, 0x02, 0xc6, 0xaf, // IID432 + 0xd5, 0x18, 0x81, 0xc4, 0x00, 0x10, 0x00, 0x00, // IID433 + 0x49, 0x83, 0xe1, 0x10, // IID434 + 0x48, 0x81, 0xd2, 0x00, 0x01, 0x00, 0x00, // IID435 + 0xd5, 0x18, 0x81, 0xfe, 0x00, 0x00, 0x00, 0x01, // IID436 + 0xd5, 0x18, 0xd1, 0xd1, // IID437 + 0xd5, 0x19, 0xd1, 0xdf, // IID438 + 0xd5, 0x19, 0xc1, 0xc3, 0x04, // IID439 + 0xd5, 0x19, 0xc1, 0xcc, 0x02, // IID440 + 0x48, 0xc1, 0xf9, 0x10, // IID441 + 0xd5, 0x19, 0xc1, 0xe7, 0x08, // IID442 + 0xd5, 0x19, 0x81, 0xdb, 0x00, 0x00, 0x10, 0x00, // IID443 + 0xd5, 0x18, 0xc1, 0xe4, 0x10, // IID444 + 0xd5, 0x19, 0xc1, 0xef, 0x08, // IID445 + 0xd5, 0x19, 0x81, 0xeb, 0x00, 0x00, 0x10, 0x00, // IID446 + 0xd5, 0x18, 0x81, 0xf6, 0x00, 0x10, 0x00, 0x00, // IID447 + 0x49, 0xc7, 0xc0, 0x00, 0x10, 0x00, 0x00, // IID448 + 0xd5, 0x19, 0xbc, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, // IID449 + 0x49, 0x0f, 0xba, 0xe5, 0x01, // IID450 + 0xd5, 0x18, 0xf7, 0xc0, 0x00, 0x00, 0xf0, 0xff, // IID451 + 0xd5, 0x18, 0x81, 0xcc, 0x00, 0x00, 0x04, 0x00, // IID452 + 0xd5, 0x18, 0x81, 0xea, 0x00, 0x00, 0x10, 0x00, // IID453 + 0xd5, 0x9b, 0x40, 0x9c, 0x05, 0x15, 0x26, 0x02, 0x1d, // IID454 + 0xd5, 0xab, 0x41, 0x94, 0x64, 0x1e, 0x67, 0x37, 0xcb, // IID455 + 0xd5, 0xcd, 0x42, 0x9c, 0xca, 0x0f, 0x54, 0x08, 0xe1, // IID456 + 0xd5, 0xaf, 0x43, 0xb4, 0xad, 0x97, 0x7c, 0xb3, 0x83, // IID457 + 0xd5, 0x9c, 0x44, 0xbc, 0x8f, 0x31, 0xd3, 0x2d, 0x94, // IID458 + 0xd5, 0xcf, 0x45, 0x84, 0x57, 0xf7, 0xc2, 0x04, 0x80, // IID459 + 0xd5, 0xc9, 0x46, 0xbb, 0x3b, 0x86, 0x6a, 0x27, // IID460 + 0xd5, 0xdd, 0x47, 0xa5, 0x6e, 0x39, 0xb4, 0x3f, // IID461 + 0xd5, 0xdd, 0x48, 0x94, 0xcb, 0x1c, 0xa6, 0xde, 0x4d, // IID462 + 0xd5, 0xbc, 0x49, 0x94, 0x5e, 0x66, 0x69, 0x12, 0x2a, // IID463 + 0x4d, 0x0f, 0x4a, 0xa2, 0x9f, 0xc5, 0xd7, 0x03, // IID464 + 0x4f, 0x0f, 0x4b, 0x94, 0xc0, 0xd3, 0x79, 0x9e, 0xf1, // IID465 + 0xd5, 0xd9, 0x4c, 0xbd, 0x93, 0x26, 0x81, 0x88, // IID466 + 0xd5, 0xa8, 0x4d, 0x8c, 0x5b, 0xcb, 0x01, 0xc6, 0x53, // IID467 + 0xd5, 0x9c, 0x4e, 0xb4, 0x19, 0x8d, 0x0f, 0x74, 0x89, // IID468 + 0xd5, 0xed, 0x4f, 0xac, 0x5a, 0x3c, 0x8d, 0xc9, 0x30, // IID469 + 0x41, 0xff, 0xd2, // IID470 + 0xd5, 0x18, 0xf7, 0xf0, // IID471 + 0xd5, 0x19, 0xf7, 0xfb, // IID472 + 0x49, 0xf7, 0xe9, // IID473 + 0x49, 0xf7, 0xe5, // IID474 + 0x49, 0xf7, 0xde, // IID475 + 0xd5, 0x18, 0xf7, 0xd2, // IID476 + 0xd5, 0x19, 0xd3, 0xc4, // IID477 + 0xd5, 0x19, 0xd3, 0xcc, // IID478 + 0xd5, 0x18, 0xd3, 0xfe, // IID479 + 0x49, 0xd3, 0xe0, // IID480 + 0x49, 0xd3, 0xe4, // IID481 + 0x48, 0xd3, 0xeb, // IID482 + 0x48, 0xff, 0xc1, // IID483 + 0xd5, 0x18, 0xff, 0xcf, // IID484 + 0xd5, 0x08, 0x51, // IID485 + 0xd5, 0x19, 0x5a, // IID486 + 0xd5, 0x13, 0xff, 0x94, 0x15, 0x9f, 0xbc, 0x55, 0x56, // IID487 + 0xd5, 0x28, 0xf7, 0xa4, 0xea, 0xd0, 0x59, 0x67, 0x98, // IID488 + 0xd5, 0x3b, 0xf7, 0x9c, 0x07, 0xfe, 0xe7, 0xf8, 0xdf, // IID489 + 0xd5, 0x18, 0xd3, 0xbc, 0x95, 0x1b, 0x46, 0xc3, 0xcb, // IID490 + 0xd5, 0x3a, 0xd3, 0xa4, 0xc4, 0x74, 0x75, 0x66, 0x0a, // IID491 + 0xd5, 0x19, 0xd3, 0xab, 0x74, 0x79, 0xb7, 0x76, // IID492 + 0xd5, 0x19, 0xff, 0x81, 0xcf, 0x72, 0xb1, 0xac, // IID493 + 0xd5, 0x18, 0xff, 0x8c, 0x24, 0x5f, 0xc1, 0xf2, 0xe7, // IID494 + 0xd5, 0x58, 0x69, 0x88, 0xa8, 0x02, 0x0d, 0xd5, 0x00, 0x10, 0x00, 0x00, // IID495 + 0xd5, 0x5d, 0x6b, 0xe1, 0x10, // IID496 + 0xd5, 0x9d, 0xa4, 0xeb, 0x10, // IID497 + 0x4d, 0x0f, 0xac, 0xd0, 0x10, // IID498 + 0x62, 0xd4, 0x3c, 0x18, 0x8f, 0xc6, // IID499 + 0x62, 0xfc, 0xe4, 0x18, 0x8f, 0xc2, // IID500 + 0x62, 0xfc, 0x64, 0x10, 0xff, 0xf7, // IID501 + 0x62, 0xd4, 0xe4, 0x18, 0xff, 0xf4, // IID502 + 0xd5, 0xad, 0xb6, 0x8c, 0xfe, 0xba, 0xd9, 0x72, 0xbd, // IID503 + 0xd5, 0xcd, 0xb7, 0xa4, 0x89, 0x9f, 0xe9, 0x9e, 0x8d, // IID504 + 0xd5, 0xb9, 0xbe, 0x9c, 0xa8, 0x90, 0xe9, 0x6b, 0x3a, // IID505 + 0xd5, 0xda, 0xbf, 0x84, 0x16, 0xdd, 0x8b, 0xef, 0x07, // IID506 + 0xd5, 0xcd, 0xb6, 0xe6, // IID507 + 0xd5, 0x9d, 0xb7, 0xec, // IID508 + 0x4c, 0x0f, 0xbe, 0xda, // IID509 + 0xd5, 0x9d, 0xbf, 0xe2, // IID510 + 0xd5, 0xc9, 0xb1, 0xa2, 0x26, 0x57, 0x2d, 0xf4, // IID511 + 0x62, 0xd4, 0xfc, 0x08, 0xf7, 0xff, // IID512 + 0x62, 0xfc, 0xfc, 0x0c, 0xf7, 0xff, // IID513 + 0x62, 0xd4, 0xfc, 0x08, 0xf7, 0xf6, // IID514 + 0x62, 0xd4, 0xfc, 0x0c, 0xf7, 0xf6, // IID515 + 0x62, 0xd4, 0xfc, 0x08, 0xf7, 0xef, // IID516 + 0x62, 0xfc, 0xfc, 0x0c, 0xf7, 0xec, // IID517 + 0x62, 0xf4, 0xfc, 0x08, 0xf7, 0xe1, // IID518 + 0x62, 0xfc, 0xfc, 0x0c, 0xf7, 0xe5, // IID519 + 0x62, 0xbc, 0xfc, 0x08, 0xf7, 0xa4, 0xd0, 0x1e, 0xac, 0x66, 0x5f, // IID520 + 0x62, 0xfc, 0xf8, 0x0c, 0xf7, 0xa4, 0xf5, 0x83, 0x7f, 0x43, 0xf4, // IID521 + 0x62, 0xcc, 0xfc, 0x08, 0xaf, 0xf2, // IID522 + 0x62, 0x6c, 0xfc, 0x0c, 0xaf, 0xcd, // IID523 + 0x62, 0xc4, 0xfc, 0x08, 0xf5, 0xe5, // IID524 + 0x62, 0x6c, 0xfc, 0x0c, 0xf5, 0xcb, // IID525 + 0x62, 0xdc, 0xd4, 0x10, 0xf7, 0xde, // IID526 + 0x62, 0xd4, 0x94, 0x14, 0xf7, 0xdb, // IID527 + 0x62, 0xd4, 0xcc, 0x10, 0xf7, 0xd0, // IID528 + 0x62, 0x7c, 0xfc, 0x08, 0x88, 0xe3, // IID529 + 0x62, 0x6c, 0xfc, 0x0c, 0x88, 0xef, // IID530 + 0x62, 0xdc, 0x9c, 0x10, 0xd3, 0xc0, // IID531 + 0x62, 0xfc, 0xec, 0x1c, 0xd3, 0xc4, // IID532 + 0x62, 0xdc, 0xe4, 0x18, 0xd3, 0xce, // IID533 + 0x62, 0xd4, 0xac, 0x1c, 0xd3, 0xcf, // IID534 + 0x62, 0xd4, 0xf4, 0x10, 0xd3, 0xe5, // IID535 + 0x62, 0xdc, 0xd4, 0x14, 0xd3, 0xe0, // IID536 + 0x62, 0xd4, 0x84, 0x10, 0xd3, 0xfc, // IID537 + 0x62, 0xdc, 0xec, 0x1c, 0xd3, 0xf8, // IID538 + 0x62, 0xdc, 0xd4, 0x10, 0xff, 0xc8, // IID539 + 0x62, 0xdc, 0x84, 0x1c, 0xff, 0xcf, // IID540 + 0x62, 0xf4, 0xac, 0x18, 0xff, 0xc3, // IID541 + 0x62, 0xd4, 0xec, 0x14, 0xff, 0xc0, // IID542 + 0x62, 0xdc, 0xac, 0x18, 0xd3, 0xe2, // IID543 + 0x62, 0xd4, 0x9c, 0x14, 0xd3, 0xe6, // IID544 + 0x62, 0xfc, 0xac, 0x18, 0xd3, 0xeb, // IID545 + 0x62, 0xfc, 0x9c, 0x14, 0xd3, 0xed, // IID546 + 0x62, 0xec, 0xfc, 0x08, 0xf4, 0xee, // IID547 + 0x62, 0xec, 0xfc, 0x0c, 0xf4, 0xc7, // IID548 + 0x62, 0x3c, 0xfc, 0x08, 0xaf, 0x9c, 0x8a, 0x5f, 0x7a, 0xdd, 0xec, // IID549 + 0x62, 0x1c, 0xfc, 0x0c, 0xaf, 0xac, 0xf8, 0xa0, 0x0c, 0xf5, 0x48, // IID550 + 0x62, 0x54, 0xfc, 0x08, 0xf5, 0x8d, 0x0e, 0xcf, 0x15, 0x21, // IID551 + 0x62, 0x4c, 0xfc, 0x0c, 0xf5, 0x9e, 0xbb, 0xab, 0x9c, 0x04, // IID552 + 0x62, 0x94, 0xd0, 0x10, 0xf7, 0x9c, 0xbd, 0xd2, 0xf4, 0xa8, 0x50, // IID553 + 0x62, 0xfc, 0xc8, 0x14, 0xf7, 0x9c, 0x62, 0xb4, 0xa7, 0x5f, 0xa2, // IID554 + 0x62, 0x74, 0xf8, 0x08, 0x88, 0xb4, 0xb3, 0x2f, 0xb6, 0x9c, 0x9f, // IID555 + 0x62, 0x6c, 0xf8, 0x0c, 0x88, 0x94, 0xf7, 0xdd, 0x93, 0x39, 0x8d, // IID556 + 0x62, 0xd4, 0xac, 0x10, 0xd3, 0xa1, 0x09, 0xba, 0x4a, 0x33, // IID557 + 0x62, 0x94, 0xb0, 0x1c, 0xd3, 0xa4, 0xf1, 0xfe, 0x9e, 0x65, 0xde, // IID558 + 0x62, 0xfc, 0xb4, 0x10, 0xd3, 0xbc, 0x24, 0x4f, 0x45, 0xce, 0xde, // IID559 + 0x62, 0xdc, 0xf8, 0x14, 0xd3, 0xbc, 0x44, 0xb9, 0x83, 0xc4, 0x48, // IID560 + 0x62, 0xd4, 0x88, 0x10, 0xff, 0x8c, 0x01, 0xb1, 0x17, 0x73, 0xf7, // IID561 + 0x62, 0x9c, 0xa0, 0x1c, 0xff, 0x8c, 0xae, 0xd0, 0x8f, 0xeb, 0x3e, // IID562 + 0x62, 0x9c, 0xac, 0x10, 0xff, 0x84, 0xd5, 0x2e, 0x82, 0xf4, 0x3e, // IID563 + 0x62, 0xfc, 0x90, 0x14, 0xff, 0x84, 0xa3, 0x47, 0xc2, 0xf0, 0xc0, // IID564 + 0x62, 0xdc, 0xb8, 0x18, 0xd3, 0xac, 0x26, 0x17, 0x6a, 0xb5, 0x15, // IID565 + 0x62, 0xd4, 0xac, 0x14, 0xd3, 0xab, 0x9f, 0x9a, 0x17, 0xd2, // IID566 + 0x62, 0x34, 0xf8, 0x08, 0xf4, 0x9c, 0x71, 0x3e, 0x4e, 0x00, 0xcd, // IID567 + 0x62, 0x84, 0xfc, 0x0c, 0xf4, 0xbc, 0x61, 0x97, 0xc1, 0x7d, 0xab, // IID568 + 0x62, 0x54, 0xdc, 0x10, 0x01, 0xbc, 0xcd, 0xf3, 0x93, 0xee, 0xb9, // IID569 + 0x62, 0xc4, 0x90, 0x1c, 0x01, 0x84, 0x79, 0xfb, 0x89, 0x93, 0xd7, // IID570 + 0x62, 0x4c, 0xd0, 0x10, 0x21, 0xac, 0x0e, 0xb2, 0x30, 0x4e, 0x0f, // IID571 + 0x62, 0xac, 0x88, 0x14, 0x21, 0x8c, 0x39, 0xc4, 0xde, 0xb9, 0x3a, // IID572 + 0x62, 0x0c, 0xa8, 0x18, 0x09, 0xa4, 0x73, 0x9a, 0xed, 0x80, 0xe6, // IID573 + 0x62, 0x1c, 0xb0, 0x1c, 0x09, 0x9c, 0x35, 0xf8, 0x64, 0x15, 0xdb, // IID574 + 0x62, 0xc4, 0x84, 0x18, 0x29, 0x86, 0x70, 0x40, 0xbb, 0xb0, // IID575 + 0x62, 0x6c, 0xf0, 0x1c, 0x29, 0xa4, 0x55, 0x71, 0x53, 0x2f, 0xee, // IID576 + 0x62, 0x7c, 0xe0, 0x10, 0x31, 0x84, 0x13, 0x14, 0xaa, 0xa1, 0xf5, // IID577 + 0x62, 0xac, 0x98, 0x14, 0x31, 0x84, 0x61, 0x20, 0xd0, 0x4b, 0x91, // IID578 + 0x62, 0xfc, 0xf4, 0x10, 0x81, 0x82, 0xfb, 0xee, 0x54, 0x9f, 0x00, 0x00, 0x00, 0x01, // IID579 + 0x62, 0xbc, 0xb0, 0x14, 0x81, 0x84, 0x0b, 0xd9, 0x44, 0x24, 0x12, 0x00, 0x00, 0x01, 0x00, // IID580 + 0x62, 0x94, 0x88, 0x10, 0x81, 0xa4, 0x61, 0x0d, 0xf3, 0x4f, 0xda, 0x00, 0x10, 0x00, 0x00, // IID581 + 0x62, 0xfc, 0xb4, 0x1c, 0x81, 0xa4, 0x5e, 0xda, 0xaf, 0xb9, 0x81, 0x00, 0x00, 0x00, 0x10, // IID582 + 0x62, 0x1c, 0xf8, 0x08, 0x6b, 0xa4, 0x49, 0x34, 0x97, 0xd2, 0xbc, 0x01, // IID583 + 0x62, 0x3c, 0xf8, 0x0c, 0x6b, 0xbc, 0xf9, 0xa2, 0xa9, 0x68, 0xd4, 0x10, // IID584 + 0x62, 0xb4, 0x98, 0x10, 0x81, 0x8c, 0x3a, 0xb1, 0x63, 0x13, 0x3f, 0x00, 0x01, 0x00, 0x00, // IID585 + 0x62, 0xd4, 0xf8, 0x14, 0x81, 0x8c, 0xfc, 0xc4, 0x79, 0x7a, 0xe8, 0x00, 0x00, 0x00, 0x01, // IID586 + 0x62, 0x94, 0xb8, 0x18, 0xc1, 0xa4, 0x86, 0x5b, 0x6f, 0xbd, 0x8e, 0x02, // IID587 + 0x62, 0x94, 0xbc, 0x1c, 0xc1, 0xa4, 0xb7, 0x43, 0x32, 0xf1, 0x21, 0x10, // IID588 + 0x62, 0x94, 0xa8, 0x18, 0xc1, 0xbc, 0x2d, 0x72, 0xcb, 0x04, 0x7d, 0x02, // IID589 + 0x62, 0xbc, 0xa0, 0x1c, 0xc1, 0xbc, 0xfd, 0x24, 0x4b, 0x89, 0xde, 0x08, // IID590 + 0x62, 0xbc, 0xf4, 0x18, 0xc1, 0xac, 0x60, 0x38, 0x9a, 0x0c, 0x26, 0x04, // IID591 + 0x62, 0x9c, 0xcc, 0x14, 0xc1, 0xac, 0x0a, 0x9e, 0x44, 0xa9, 0xa1, 0x08, // IID592 + 0x62, 0xb4, 0x80, 0x10, 0x83, 0xac, 0x63, 0x10, 0xbb, 0x00, 0x2b, 0x01, // IID593 + 0x62, 0xdc, 0xd4, 0x14, 0x81, 0xaf, 0x53, 0x0b, 0xef, 0x93, 0x00, 0x10, 0x00, 0x00, // IID594 + 0x62, 0xbc, 0xa0, 0x18, 0x81, 0xb4, 0x77, 0x6b, 0x02, 0xa6, 0x51, 0x00, 0x00, 0x01, 0x00, // IID595 + 0x62, 0x9c, 0x8c, 0x1c, 0x83, 0xb4, 0x93, 0x55, 0x64, 0x52, 0xcb, 0x10, // IID596 + 0x62, 0xfc, 0xdc, 0x10, 0x81, 0xc7, 0x00, 0x00, 0x00, 0x01, // IID597 + 0x62, 0xdc, 0xfc, 0x18, 0x81, 0xc6, 0x00, 0x00, 0x00, 0x01, // IID598 + 0x62, 0xfc, 0xb4, 0x1c, 0x81, 0xc5, 0x00, 0x10, 0x00, 0x00, // IID599 + 0x62, 0xf4, 0xfc, 0x1c, 0x81, 0xc3, 0x00, 0x10, 0x00, 0x00, // IID600 + 0x62, 0xfc, 0xec, 0x18, 0x81, 0xe5, 0x00, 0x00, 0x00, 0x10, // IID601 + 0x62, 0xd4, 0xfc, 0x18, 0x81, 0xe0, 0x00, 0x00, 0x00, 0x10, // IID602 + 0x62, 0xdc, 0xe4, 0x14, 0x81, 0xe7, 0x00, 0x00, 0x01, 0x00, // IID603 + 0x62, 0xf4, 0xfc, 0x1c, 0x81, 0xe3, 0x00, 0x00, 0x01, 0x00, // IID604 + 0x62, 0xc4, 0xfc, 0x08, 0x69, 0xe9, 0x00, 0x00, 0x00, 0x01, // IID605 + 0x62, 0xdc, 0xfc, 0x08, 0x69, 0xc6, 0x00, 0x00, 0x00, 0x01, // IID606 + 0x62, 0x6c, 0xfc, 0x0c, 0x69, 0xf2, 0x00, 0x00, 0x01, 0x00, // IID607 + 0x62, 0xfc, 0xfc, 0x0c, 0x69, 0xc3, 0x00, 0x00, 0x01, 0x00, // IID608 + 0x62, 0xfc, 0xdc, 0x10, 0x81, 0xc8, 0x00, 0x00, 0x10, 0x00, // IID609 + 0x62, 0xdc, 0xfc, 0x18, 0x81, 0xcc, 0x00, 0x00, 0x10, 0x00, // IID610 + 0x62, 0xdc, 0xe4, 0x1c, 0x81, 0xc8, 0x00, 0x10, 0x00, 0x00, // IID611 + 0x62, 0xfc, 0xfc, 0x1c, 0x81, 0xce, 0x00, 0x10, 0x00, 0x00, // IID612 + 0x62, 0xdc, 0xdc, 0x10, 0xc1, 0xd6, 0x04, // IID613 + 0x62, 0xfc, 0xfc, 0x18, 0xc1, 0xd6, 0x04, // IID614 + 0x62, 0xdc, 0xf4, 0x18, 0xc1, 0xc4, 0x02, // IID615 + 0x62, 0xfc, 0xfc, 0x18, 0xc1, 0xc5, 0x02, // IID616 + 0x62, 0xd4, 0xac, 0x14, 0xc1, 0xc7, 0x04, // IID617 + 0x62, 0xfc, 0xfc, 0x1c, 0xc1, 0xc3, 0x04, // IID618 + 0x62, 0xfc, 0xbc, 0x10, 0xc1, 0xcb, 0x08, // IID619 + 0x62, 0xdc, 0xfc, 0x18, 0xc1, 0xcc, 0x08, // IID620 + 0x62, 0xfc, 0xb4, 0x14, 0xc1, 0xca, 0x04, // IID621 + 0x62, 0xd4, 0xfc, 0x1c, 0xc1, 0xcd, 0x04, // IID622 + 0x62, 0xfc, 0xa4, 0x10, 0xc1, 0xe1, 0x02, // IID623 + 0x62, 0xf4, 0xfc, 0x18, 0xc1, 0xe2, 0x02, // IID624 + 0x62, 0xdc, 0xe4, 0x1c, 0xc1, 0xe4, 0x10, // IID625 + 0x62, 0xd4, 0xfc, 0x1c, 0xc1, 0xe7, 0x10, // IID626 + 0x62, 0xd4, 0xe4, 0x18, 0xc1, 0xfc, 0x04, // IID627 + 0x62, 0xf4, 0xfc, 0x18, 0xc1, 0xfb, 0x04, // IID628 + 0x62, 0xf4, 0xf4, 0x14, 0xc1, 0xfa, 0x02, // IID629 + 0x62, 0xdc, 0xfc, 0x1c, 0xc1, 0xff, 0x02, // IID630 + 0x62, 0xf4, 0xd4, 0x10, 0xc1, 0xe3, 0x04, // IID631 + 0x62, 0xdc, 0xfc, 0x18, 0xc1, 0xe0, 0x04, // IID632 + 0x62, 0xd4, 0xa4, 0x14, 0xc1, 0xe5, 0x10, // IID633 + 0x62, 0xdc, 0xfc, 0x1c, 0xc1, 0xe1, 0x10, // IID634 + 0x62, 0xfc, 0xf4, 0x18, 0xc1, 0xee, 0x10, // IID635 + 0x62, 0xd4, 0xfc, 0x18, 0xc1, 0xee, 0x10, // IID636 + 0x62, 0xdc, 0xa4, 0x1c, 0xc1, 0xee, 0x04, // IID637 + 0x62, 0xdc, 0xfc, 0x1c, 0xc1, 0xe8, 0x04, // IID638 + 0x62, 0xfc, 0xdc, 0x10, 0x81, 0xeb, 0x00, 0x01, 0x00, 0x00, // IID639 + 0x62, 0xfc, 0xfc, 0x18, 0x81, 0xe9, 0x00, 0x01, 0x00, 0x00, // IID640 + 0x62, 0xdc, 0x84, 0x14, 0x81, 0xee, 0x00, 0x00, 0x01, 0x00, // IID641 + 0x62, 0xfc, 0xfc, 0x1c, 0x81, 0xea, 0x00, 0x00, 0x01, 0x00, // IID642 + 0x62, 0xd4, 0xec, 0x10, 0x81, 0xf3, 0x00, 0x10, 0x00, 0x00, // IID643 + 0x62, 0xd4, 0xfc, 0x18, 0x81, 0xf2, 0x00, 0x10, 0x00, 0x00, // IID644 + 0x62, 0xfc, 0xbc, 0x14, 0x81, 0xf2, 0x00, 0x00, 0x00, 0x10, // IID645 + 0x62, 0xf4, 0xfc, 0x1c, 0x81, 0xf3, 0x00, 0x00, 0x00, 0x10, // IID646 + 0x62, 0xfc, 0xac, 0x10, 0x81, 0xcd, 0x00, 0x00, 0x40, 0x00, // IID647 + 0x62, 0xd4, 0xfc, 0x18, 0x81, 0xc8, 0x00, 0x00, 0x40, 0x00, // IID648 + 0x62, 0xfc, 0xcc, 0x10, 0x81, 0xcd, 0x00, 0x00, 0x04, 0x00, // IID649 + 0x62, 0xdc, 0xfc, 0x18, 0x81, 0xcb, 0x00, 0x00, 0x04, 0x00, // IID650 + 0x62, 0xd4, 0xfc, 0x10, 0x81, 0xe8, 0x00, 0x00, 0x40, 0x00, // IID651 + 0x62, 0xf4, 0xfc, 0x18, 0x81, 0xea, 0x00, 0x00, 0x40, 0x00, // IID652 + 0x62, 0xdc, 0xdc, 0x14, 0x81, 0xef, 0x00, 0x00, 0x10, 0x00, // IID653 + 0x62, 0xfc, 0xfc, 0x1c, 0x81, 0xed, 0x00, 0x00, 0x10, 0x00, // IID654 + 0x62, 0x74, 0xd8, 0x10, 0x03, 0xb4, 0x01, 0xd9, 0x54, 0x66, 0x7c, // IID655 + 0x62, 0xd4, 0x90, 0x14, 0x03, 0x8c, 0x3f, 0x2d, 0xf7, 0xb7, 0x45, // IID656 + 0x62, 0xc4, 0xe0, 0x10, 0x23, 0x8c, 0x75, 0x6a, 0xe6, 0xf3, 0x8a, // IID657 + 0x62, 0x5c, 0x90, 0x1c, 0x23, 0x84, 0x7f, 0x4e, 0x49, 0xee, 0xdd, // IID658 + 0x62, 0x04, 0xa4, 0x18, 0x0b, 0xa4, 0xdd, 0xab, 0x13, 0x00, 0x5c, // IID659 + 0x62, 0xec, 0xec, 0x1c, 0x0b, 0x94, 0x0a, 0x71, 0x7e, 0x55, 0x59, // IID660 + 0x62, 0x7c, 0xa4, 0x10, 0xaf, 0x9e, 0xb7, 0x69, 0xb9, 0xd7, // IID661 + 0x62, 0x5c, 0xac, 0x1c, 0xaf, 0x88, 0x54, 0x1d, 0x69, 0x49, // IID662 + 0x62, 0x7c, 0xbc, 0x10, 0x2b, 0xa3, 0xaa, 0x29, 0xd5, 0x22, // IID663 + 0x62, 0x84, 0xdc, 0x14, 0x2b, 0x94, 0x91, 0xb8, 0x85, 0xb5, 0xd9, // IID664 + 0x62, 0x14, 0xe0, 0x18, 0x33, 0x8c, 0x1e, 0x2f, 0xc0, 0x71, 0x0f, // IID665 + 0x62, 0x14, 0xb4, 0x14, 0x33, 0xbc, 0x62, 0xbd, 0x67, 0x23, 0x73, // IID666 + 0x62, 0x54, 0xa4, 0x18, 0x03, 0xca, // IID667 + 0x62, 0x7c, 0xb4, 0x14, 0x03, 0xe8, // IID668 + 0x62, 0xcc, 0xa5, 0x18, 0x66, 0xe9, // IID669 + 0x62, 0xe4, 0xee, 0x18, 0x66, 0xe3, // IID670 + 0x62, 0xcc, 0xb4, 0x10, 0x23, 0xea, // IID671 + 0x62, 0x6c, 0xc4, 0x14, 0x23, 0xdd, // IID672 + 0x62, 0x54, 0xac, 0x18, 0xaf, 0xd4, // IID673 + 0x62, 0x7c, 0x84, 0x14, 0xaf, 0xe7, // IID674 + 0x62, 0x44, 0xfc, 0x10, 0x0b, 0xee, // IID675 + 0x62, 0x6c, 0xe4, 0x14, 0x0b, 0xc7, // IID676 + 0x62, 0xc4, 0x8c, 0x18, 0x2b, 0xef, // IID677 + 0x62, 0x5c, 0xb4, 0x14, 0x2b, 0xcd, // IID678 + 0x62, 0x5c, 0xec, 0x18, 0x33, 0xd9, // IID679 + 0x62, 0x7c, 0xe4, 0x14, 0x33, 0xd0, // IID680 + 0x62, 0x6c, 0xbc, 0x18, 0x24, 0xff, 0x08, // IID681 + 0x62, 0xe4, 0x84, 0x14, 0x24, 0xc3, 0x02, // IID682 + 0x62, 0x54, 0xbc, 0x10, 0x2c, 0xca, 0x02, // IID683 + 0x62, 0xcc, 0x9c, 0x14, 0x2c, 0xd2, 0x10, // IID684 + 0x62, 0xec, 0xb4, 0x10, 0x40, 0xe0, // IID685 + 0x62, 0xdc, 0xd4, 0x10, 0x41, 0xdc, // IID686 + 0x62, 0xc4, 0xcc, 0x10, 0x42, 0xdd, // IID687 + 0x62, 0xd4, 0x84, 0x18, 0x43, 0xd0, // IID688 + 0x62, 0x54, 0xcc, 0x10, 0x44, 0xf4, // IID689 + 0x62, 0x5c, 0xbc, 0x10, 0x45, 0xf0, // IID690 + 0x62, 0xe4, 0x94, 0x18, 0x46, 0xeb, // IID691 + 0x62, 0x44, 0xe4, 0x18, 0x47, 0xde, // IID692 + 0x62, 0x6c, 0xbc, 0x10, 0x48, 0xd9, // IID693 + 0x62, 0x4c, 0xd4, 0x10, 0x49, 0xdb, // IID694 + 0x62, 0x5c, 0xa4, 0x10, 0x4a, 0xf0, // IID695 + 0x62, 0x6c, 0x9c, 0x10, 0x4b, 0xee, // IID696 + 0x62, 0x5c, 0x84, 0x18, 0x4c, 0xef, // IID697 + 0x62, 0x5c, 0xd4, 0x10, 0x4d, 0xfe, // IID698 + 0x62, 0x54, 0xdc, 0x10, 0x4e, 0xc5, // IID699 + 0x62, 0x4c, 0x84, 0x10, 0x4f, 0xcb, // IID700 + 0x62, 0x14, 0x84, 0x10, 0x40, 0xbc, 0x6e, 0xaa, 0x7a, 0x19, 0xf9, // IID701 + 0x62, 0x0c, 0x9c, 0x18, 0x41, 0xa4, 0xfe, 0x9e, 0x3f, 0xa3, 0x3b, // IID702 + 0x62, 0x04, 0xfc, 0x10, 0x42, 0x8c, 0x0c, 0xcd, 0xc4, 0x1f, 0xd7, // IID703 + 0x62, 0x04, 0xb8, 0x18, 0x43, 0x9c, 0xc8, 0x6b, 0x42, 0xbd, 0xe1, // IID704 + 0x62, 0xcc, 0xf4, 0x18, 0x44, 0xa4, 0x9b, 0x58, 0x3c, 0x82, 0x46, // IID705 + 0x62, 0x7c, 0xe4, 0x18, 0x45, 0xa5, 0x38, 0x47, 0xca, 0xf9, // IID706 + 0x62, 0x9c, 0xc0, 0x10, 0x46, 0x9c, 0xd3, 0xc0, 0xbc, 0x22, 0x09, // IID707 + 0x62, 0x7c, 0xb4, 0x10, 0x47, 0x8f, 0xec, 0x14, 0x2a, 0x0d, // IID708 + 0x62, 0xc4, 0xa4, 0x18, 0x48, 0x9b, 0x63, 0xa5, 0x46, 0xf0, // IID709 + 0x62, 0xcc, 0x90, 0x18, 0x49, 0x94, 0x1c, 0x7e, 0x9b, 0x6b, 0x71, // IID710 + 0x62, 0xa4, 0xd0, 0x10, 0x4a, 0x84, 0x29, 0xe2, 0xbb, 0x0f, 0xa5, // IID711 + 0x62, 0x2c, 0x98, 0x18, 0x4b, 0xbc, 0x14, 0xb1, 0x7f, 0x0b, 0x0e, // IID712 + 0x62, 0x4c, 0x84, 0x18, 0x4c, 0x86, 0x4f, 0x7b, 0x3b, 0x2d, // IID713 + 0x62, 0x54, 0x98, 0x18, 0x4d, 0xbc, 0xae, 0x18, 0x51, 0xdd, 0xed, // IID714 + 0x62, 0x6c, 0xe0, 0x18, 0x4e, 0xbc, 0x27, 0x96, 0xb2, 0x91, 0xf6, // IID715 + 0x62, 0xd4, 0xec, 0x18, 0x4f, 0x94, 0xd2, 0x7c, 0xf1, 0x75, 0x38, // IID716 #endif // _LP64 }; @@ -1623,73 +1739,75 @@ 10, // IID254 10, // IID255 10, // IID256 - 7, // IID257 - 10, // IID258 - 10, // IID259 - 10, // IID260 - 10, // IID261 - 7, // IID262 - 7, // IID263 - 7, // IID264 - 7, // IID265 - 7, // IID266 - 6, // IID267 - 7, // IID268 - 7, // IID269 + 10, // IID257 + 7, // IID258 + 7, // IID259 + 7, // IID260 + 7, // IID261 + 10, // IID262 + 10, // IID263 + 10, // IID264 + 10, // IID265 + 10, // IID266 + 10, // IID267 + 10, // IID268 + 10, // IID269 7, // IID270 7, // IID271 7, // IID272 7, // IID273 7, // IID274 - 10, // IID275 - 10, // IID276 - 10, // IID277 + 7, // IID275 + 6, // IID276 + 6, // IID277 7, // IID278 - 10, // IID279 - 10, // IID280 - 11, // IID281 - 11, // IID282 - 11, // IID283 - 11, // IID284 - 11, // IID285 - 11, // IID286 - 10, // IID287 - 11, // IID288 - 11, // IID289 - 11, // IID290 - 11, // IID291 - 11, // IID292 - 11, // IID293 - 10, // IID294 - 11, // IID295 - 11, // IID296 - 6, // IID297 - 6, // IID298 - 6, // IID299 - 6, // IID300 - 6, // IID301 - 6, // IID302 - 6, // IID303 - 6, // IID304 - 6, // IID305 - 6, // IID306 - 6, // IID307 - 6, // IID308 - 6, // IID309 - 6, // IID310 - 6, // IID311 - 6, // IID312 - 6, // IID313 - 6, // IID314 - 7, // IID315 - 7, // IID316 - 7, // IID317 - 7, // IID318 - 6, // IID319 - 6, // IID320 - 6, // IID321 - 6, // IID322 - 6, // IID323 + 7, // IID279 + 7, // IID280 + 7, // IID281 + 6, // IID282 + 6, // IID283 + 7, // IID284 + 7, // IID285 + 7, // IID286 + 7, // IID287 + 6, // IID288 + 6, // IID289 + 7, // IID290 + 7, // IID291 + 7, // IID292 + 7, // IID293 + 7, // IID294 + 7, // IID295 + 10, // IID296 + 10, // IID297 + 10, // IID298 +#endif // _LP64 + 10, // IID299 +#ifdef _LP64 + 10, // IID300 + 10, // IID301 + 10, // IID302 + 10, // IID303 + 10, // IID304 + 10, // IID305 + 10, // IID306 + 10, // IID307 + 11, // IID308 + 11, // IID309 + 11, // IID310 + 10, // IID311 + 11, // IID312 + 11, // IID313 + 11, // IID314 + 11, // IID315 + 11, // IID316 + 11, // IID317 + 10, // IID318 + 11, // IID319 + 11, // IID320 + 11, // IID321 + 11, // IID322 + 11, // IID323 6, // IID324 6, // IID325 6, // IID326 @@ -1701,183 +1819,183 @@ 6, // IID332 6, // IID333 6, // IID334 - 11, // IID335 - 11, // IID336 - 11, // IID337 - 10, // IID338 - 11, // IID339 - 11, // IID340 - 11, // IID341 - 11, // IID342 - 11, // IID343 - 11, // IID344 - 11, // IID345 - 11, // IID346 - 11, // IID347 - 11, // IID348 - 11, // IID349 - 11, // IID350 - 3, // IID351 - 3, // IID352 - 4, // IID353 - 5, // IID354 - 4, // IID355 - 4, // IID356 - 5, // IID357 - 5, // IID358 - 4, // IID359 - 4, // IID360 - 4, // IID361 - 4, // IID362 - 3, // IID363 - 4, // IID364 - 4, // IID365 - 4, // IID366 - 4, // IID367 - 4, // IID368 - 9, // IID369 - 9, // IID370 - 9, // IID371 - 8, // IID372 - 8, // IID373 - 9, // IID374 - 9, // IID375 - 9, // IID376 - 13, // IID377 - 12, // IID378 - 13, // IID379 - 10, // IID380 - 10, // IID381 - 13, // IID382 - 10, // IID383 - 13, // IID384 - 10, // IID385 - 13, // IID386 - 13, // IID387 - 13, // IID388 - 9, // IID389 - 8, // IID390 - 8, // IID391 - 10, // IID392 - 9, // IID393 - 9, // IID394 - 9, // IID395 + 6, // IID335 + 6, // IID336 + 6, // IID337 + 6, // IID338 + 6, // IID339 + 6, // IID340 + 6, // IID341 + 7, // IID342 + 7, // IID343 + 7, // IID344 + 7, // IID345 + 6, // IID346 + 6, // IID347 + 6, // IID348 + 6, // IID349 + 6, // IID350 + 6, // IID351 + 6, // IID352 + 6, // IID353 + 6, // IID354 + 6, // IID355 + 6, // IID356 + 6, // IID357 + 6, // IID358 + 6, // IID359 + 6, // IID360 + 6, // IID361 + 11, // IID362 + 11, // IID363 + 10, // IID364 + 11, // IID365 + 11, // IID366 + 11, // IID367 + 11, // IID368 + 10, // IID369 + 11, // IID370 + 11, // IID371 + 11, // IID372 + 11, // IID373 + 11, // IID374 + 11, // IID375 + 11, // IID376 + 11, // IID377 + 4, // IID378 + 4, // IID379 + 4, // IID380 + 5, // IID381 + 4, // IID382 + 4, // IID383 + 5, // IID384 + 5, // IID385 + 4, // IID386 + 4, // IID387 + 4, // IID388 + 3, // IID389 + 4, // IID390 + 4, // IID391 + 4, // IID392 + 4, // IID393 + 4, // IID394 + 3, // IID395 9, // IID396 9, // IID397 - 9, // IID398 - 10, // IID399 + 8, // IID398 + 8, // IID399 9, // IID400 9, // IID401 9, // IID402 - 10, // IID403 - 9, // IID404 - 9, // IID405 - 5, // IID406 - 7, // IID407 - 7, // IID408 - 7, // IID409 - 5, // IID410 - 4, // IID411 - 3, // IID412 - 5, // IID413 - 5, // IID414 - 4, // IID415 - 5, // IID416 - 5, // IID417 - 5, // IID418 - 7, // IID419 - 8, // IID420 + 9, // IID403 + 11, // IID404 + 13, // IID405 + 12, // IID406 + 10, // IID407 + 10, // IID408 + 13, // IID409 + 9, // IID410 + 10, // IID411 + 10, // IID412 + 12, // IID413 + 13, // IID414 + 13, // IID415 + 9, // IID416 + 9, // IID417 + 9, // IID418 + 10, // IID419 + 9, // IID420 8, // IID421 - 11, // IID422 - 5, // IID423 - 7, // IID424 - 8, // IID425 - 7, // IID426 - 8, // IID427 + 9, // IID422 + 10, // IID423 + 9, // IID424 + 9, // IID425 + 10, // IID426 + 9, // IID427 9, // IID428 9, // IID429 - 9, // IID430 - 9, // IID431 + 10, // IID430 + 8, // IID431 9, // IID432 - 9, // IID433 - 8, // IID434 - 8, // IID435 - 9, // IID436 - 9, // IID437 - 8, // IID438 - 9, // IID439 - 8, // IID440 - 9, // IID441 - 9, // IID442 - 4, // IID443 - 3, // IID444 - 4, // IID445 - 3, // IID446 - 4, // IID447 - 4, // IID448 - 3, // IID449 - 4, // IID450 - 4, // IID451 - 3, // IID452 - 3, // IID453 - 3, // IID454 - 4, // IID455 - 4, // IID456 - 4, // IID457 - 3, // IID458 - 3, // IID459 + 8, // IID433 + 4, // IID434 + 7, // IID435 + 8, // IID436 + 4, // IID437 + 4, // IID438 + 5, // IID439 + 5, // IID440 + 4, // IID441 + 5, // IID442 + 8, // IID443 + 5, // IID444 + 5, // IID445 + 8, // IID446 + 8, // IID447 + 7, // IID448 + 11, // IID449 + 5, // IID450 + 8, // IID451 + 8, // IID452 + 8, // IID453 + 9, // IID454 + 9, // IID455 + 9, // IID456 + 9, // IID457 + 9, // IID458 + 9, // IID459 8, // IID460 - 9, // IID461 + 8, // IID461 9, // IID462 9, // IID463 - 9, // IID464 + 8, // IID464 9, // IID465 8, // IID466 - 8, // IID467 - 12, // IID468 - 5, // IID469 - 5, // IID470 - 5, // IID471 - 6, // IID472 - 6, // IID473 - 6, // IID474 - 6, // IID475 - 9, // IID476 - 9, // IID477 - 9, // IID478 - 9, // IID479 - 4, // IID480 - 4, // IID481 - 4, // IID482 - 4, // IID483 - 8, // IID484 - 6, // IID485 - 6, // IID486 - 6, // IID487 - 6, // IID488 - 6, // IID489 - 6, // IID490 - 6, // IID491 - 6, // IID492 - 11, // IID493 - 11, // IID494 - 6, // IID495 - 6, // IID496 - 6, // IID497 - 6, // IID498 + 9, // IID467 + 9, // IID468 + 9, // IID469 + 3, // IID470 + 4, // IID471 + 4, // IID472 + 3, // IID473 + 3, // IID474 + 3, // IID475 + 4, // IID476 + 4, // IID477 + 4, // IID478 + 4, // IID479 + 3, // IID480 + 3, // IID481 + 3, // IID482 + 3, // IID483 + 4, // IID484 + 3, // IID485 + 3, // IID486 + 9, // IID487 + 9, // IID488 + 9, // IID489 + 9, // IID490 + 9, // IID491 + 8, // IID492 + 8, // IID493 + 9, // IID494 + 12, // IID495 + 5, // IID496 + 5, // IID497 + 5, // IID498 6, // IID499 6, // IID500 6, // IID501 6, // IID502 - 6, // IID503 - 6, // IID504 - 6, // IID505 - 6, // IID506 - 6, // IID507 - 6, // IID508 - 6, // IID509 - 6, // IID510 - 6, // IID511 + 9, // IID503 + 9, // IID504 + 9, // IID505 + 9, // IID506 + 4, // IID507 + 4, // IID508 + 4, // IID509 + 4, // IID510 + 8, // IID511 6, // IID512 6, // IID513 6, // IID514 @@ -1886,147 +2004,203 @@ 6, // IID517 6, // IID518 6, // IID519 - 6, // IID520 - 6, // IID521 - 11, // IID522 - 11, // IID523 - 10, // IID524 - 10, // IID525 - 11, // IID526 - 11, // IID527 - 11, // IID528 - 11, // IID529 - 10, // IID530 - 11, // IID531 - 11, // IID532 - 11, // IID533 - 11, // IID534 - 11, // IID535 - 11, // IID536 - 11, // IID537 - 11, // IID538 - 10, // IID539 - 11, // IID540 - 11, // IID541 - 11, // IID542 - 11, // IID543 - 11, // IID544 - 11, // IID545 - 11, // IID546 - 11, // IID547 - 10, // IID548 + 11, // IID520 + 11, // IID521 + 6, // IID522 + 6, // IID523 + 6, // IID524 + 6, // IID525 + 6, // IID526 + 6, // IID527 + 6, // IID528 + 6, // IID529 + 6, // IID530 + 6, // IID531 + 6, // IID532 + 6, // IID533 + 6, // IID534 + 6, // IID535 + 6, // IID536 + 6, // IID537 + 6, // IID538 + 6, // IID539 + 6, // IID540 + 6, // IID541 + 6, // IID542 + 6, // IID543 + 6, // IID544 + 6, // IID545 + 6, // IID546 + 6, // IID547 + 6, // IID548 11, // IID549 11, // IID550 - 11, // IID551 - 14, // IID552 - 15, // IID553 - 15, // IID554 - 15, // IID555 - 12, // IID556 - 12, // IID557 - 15, // IID558 - 15, // IID559 - 12, // IID560 - 12, // IID561 - 12, // IID562 - 12, // IID563 - 12, // IID564 - 12, // IID565 - 12, // IID566 - 14, // IID567 - 15, // IID568 - 12, // IID569 - 10, // IID570 - 10, // IID571 - 7, // IID572 - 7, // IID573 - 7, // IID574 + 10, // IID551 + 10, // IID552 + 11, // IID553 + 11, // IID554 + 11, // IID555 + 11, // IID556 + 10, // IID557 + 11, // IID558 + 11, // IID559 + 11, // IID560 + 11, // IID561 + 11, // IID562 + 11, // IID563 + 11, // IID564 + 11, // IID565 + 10, // IID566 + 11, // IID567 + 11, // IID568 + 11, // IID569 + 11, // IID570 + 11, // IID571 + 11, // IID572 + 11, // IID573 + 11, // IID574 10, // IID575 - 10, // IID576 - 10, // IID577 - 7, // IID578 - 7, // IID579 - 7, // IID580 - 7, // IID581 - 7, // IID582 - 7, // IID583 - 7, // IID584 - 7, // IID585 - 7, // IID586 - 6, // IID587 - 7, // IID588 - 6, // IID589 - 7, // IID590 - 10, // IID591 - 10, // IID592 - 7, // IID593 - 10, // IID594 - 10, // IID595 - 10, // IID596 + 11, // IID576 + 11, // IID577 + 11, // IID578 + 14, // IID579 + 15, // IID580 + 15, // IID581 + 15, // IID582 + 12, // IID583 + 12, // IID584 + 15, // IID585 + 15, // IID586 + 12, // IID587 + 12, // IID588 + 12, // IID589 + 12, // IID590 + 12, // IID591 + 12, // IID592 + 12, // IID593 + 14, // IID594 + 15, // IID595 + 12, // IID596 10, // IID597 10, // IID598 - 11, // IID599 - 11, // IID600 - 11, // IID601 - 11, // IID602 - 11, // IID603 - 11, // IID604 - 11, // IID605 - 11, // IID606 - 11, // IID607 + 10, // IID599 + 10, // IID600 + 10, // IID601 + 10, // IID602 + 10, // IID603 + 10, // IID604 + 10, // IID605 + 10, // IID606 + 10, // IID607 10, // IID608 10, // IID609 10, // IID610 - 6, // IID611 - 6, // IID612 - 6, // IID613 - 6, // IID614 - 6, // IID615 - 6, // IID616 - 6, // IID617 - 6, // IID618 - 6, // IID619 - 6, // IID620 - 6, // IID621 - 6, // IID622 - 6, // IID623 - 6, // IID624 + 10, // IID611 + 10, // IID612 + 7, // IID613 + 7, // IID614 + 7, // IID615 + 7, // IID616 + 7, // IID617 + 7, // IID618 + 7, // IID619 + 7, // IID620 + 7, // IID621 + 7, // IID622 + 7, // IID623 + 7, // IID624 7, // IID625 7, // IID626 7, // IID627 7, // IID628 - 6, // IID629 - 6, // IID630 - 6, // IID631 - 6, // IID632 - 6, // IID633 - 6, // IID634 - 6, // IID635 - 6, // IID636 - 6, // IID637 - 6, // IID638 - 6, // IID639 - 6, // IID640 - 6, // IID641 - 6, // IID642 - 6, // IID643 - 6, // IID644 - 11, // IID645 - 11, // IID646 - 11, // IID647 - 11, // IID648 - 11, // IID649 - 11, // IID650 - 11, // IID651 - 11, // IID652 + 7, // IID629 + 7, // IID630 + 7, // IID631 + 7, // IID632 + 7, // IID633 + 7, // IID634 + 7, // IID635 + 7, // IID636 + 7, // IID637 + 7, // IID638 + 10, // IID639 + 10, // IID640 + 10, // IID641 + 10, // IID642 + 10, // IID643 + 10, // IID644 + 10, // IID645 + 10, // IID646 + 10, // IID647 + 10, // IID648 + 10, // IID649 + 10, // IID650 + 10, // IID651 + 10, // IID652 10, // IID653 - 11, // IID654 - 10, // IID655 - 10, // IID656 + 10, // IID654 + 11, // IID655 + 11, // IID656 11, // IID657 11, // IID658 11, // IID659 - 10, // IID660 + 11, // IID660 + 10, // IID661 + 10, // IID662 + 10, // IID663 + 11, // IID664 + 11, // IID665 + 11, // IID666 + 6, // IID667 + 6, // IID668 + 6, // IID669 + 6, // IID670 + 6, // IID671 + 6, // IID672 + 6, // IID673 + 6, // IID674 + 6, // IID675 + 6, // IID676 + 6, // IID677 + 6, // IID678 + 6, // IID679 + 6, // IID680 + 7, // IID681 + 7, // IID682 + 7, // IID683 + 7, // IID684 + 6, // IID685 + 6, // IID686 + 6, // IID687 + 6, // IID688 + 6, // IID689 + 6, // IID690 + 6, // IID691 + 6, // IID692 + 6, // IID693 + 6, // IID694 + 6, // IID695 + 6, // IID696 + 6, // IID697 + 6, // IID698 + 6, // IID699 + 6, // IID700 + 11, // IID701 + 11, // IID702 + 11, // IID703 + 11, // IID704 + 11, // IID705 + 10, // IID706 + 11, // IID707 + 10, // IID708 + 10, // IID709 + 11, // IID710 + 11, // IID711 + 11, // IID712 + 10, // IID713 + 11, // IID714 + 11, // IID715 + 11, // IID716 #endif // _LP64 }; @@ -2298,412 +2472,470 @@ "__ exorb(r9, Address(r31, +0x72a4f58e), r30, false);", // IID252 "__ exorb(r24, Address(r25, r15, (Address::ScaleFactor)0, +0x20fc1a0a), r16, true);", // IID253 "__ eaddl(r12, rbx, 65536, false);", // IID254 - "__ eaddl(r20, r24, 4096, true);", // IID255 - "__ eandl(r18, r26, 1048576, false);", // IID256 - "__ eandl(r29, r13, 1, true);", // IID257 - "__ eimull(rcx, r31, 65536, false);", // IID258 - "__ eimull(r23, r29, 65536, true);", // IID259 - "__ eorl(r23, r23, 1048576, false);", // IID260 - "__ eorl(r21, r9, 268435456, true);", // IID261 - "__ ercll(r13, rdx, 4);", // IID262 - "__ eroll(r15, r31, 8, false);", // IID263 - "__ eroll(r8, r9, 2, true);", // IID264 - "__ erorl(r9, r15, 8, false);", // IID265 - "__ erorl(r21, r12, 8, true);", // IID266 - "__ esall(r19, r27, 1, false);", // IID267 - "__ esall(r10, r11, 16, true);", // IID268 - "__ esarl(r8, rdx, 8, false);", // IID269 - "__ esarl(r22, r30, 4, true);", // IID270 - "__ eshll(r25, r31, 16, false);", // IID271 - "__ eshll(r10, r9, 8, true);", // IID272 - "__ eshrl(r13, r8, 4, false);", // IID273 - "__ eshrl(r16, r21, 16, true);", // IID274 - "__ esubl(r26, r23, 16777216, false);", // IID275 - "__ esubl(r26, r14, 1048576, true);", // IID276 - "__ exorl(r27, r26, 256, false);", // IID277 - "__ exorl(r22, r9, 1, true);", // IID278 - "__ esubl_imm32(r22, r30, 268435456, false);", // IID279 - "__ esubl_imm32(r8, r16, 4194304, true);", // IID280 - "__ eaddl(r20, r29, Address(r11, r12, (Address::ScaleFactor)1, +0xac0980), false);", // IID281 - "__ eaddl(r18, rbx, Address(r9, r18, (Address::ScaleFactor)1, +0x434a125d), true);", // IID282 - "__ eandl(r14, r15, Address(r14, r19, (Address::ScaleFactor)2, +0x15a5a5ee), false);", // IID283 - "__ eandl(r28, r31, Address(r24, r12, (Address::ScaleFactor)3, -0x6d6d7e68), true);", // IID284 - "__ eimull(r24, r13, Address(r24, r25, (Address::ScaleFactor)3, +0x784673fd), false);", // IID285 - "__ eimull(r24, r21, Address(r8, r13, (Address::ScaleFactor)2, -0x63663889), true);", // IID286 - "__ eorl(r12, r24, Address(r30, -0x67526556), false);", // IID287 - "__ eorl(r13, r13, Address(rbx, r25, (Address::ScaleFactor)2, -0x5f394dd9), true);", // IID288 - "__ esubl(r26, r25, Address(r25, rdx, (Address::ScaleFactor)3, -0x2e39f79a), false);", // IID289 - "__ esubl(r28, r8, Address(rdx, r24, (Address::ScaleFactor)3, -0xed99a54), true);", // IID290 - "__ exorl(r31, r22, Address(r30, r20, (Address::ScaleFactor)3, +0x3ac41cbd), false);", // IID291 - "__ exorl(r24, r30, Address(r13, r17, (Address::ScaleFactor)1, +0x1efdc2e3), true);", // IID292 - "__ exorb(r16, r16, Address(r9, r15, (Address::ScaleFactor)1, +0x769feb34), false);", // IID293 - "__ exorb(r19, r25, Address(r10, +0x2239b429), true);", // IID294 - "__ exorw(r25, r19, Address(r16, r24, (Address::ScaleFactor)1, +0x1c71faea), false);", // IID295 - "__ exorw(r19, r10, Address(r28, -0x299a0cfd), true);", // IID296 - "__ eaddl(rbx, r23, r24, false);", // IID297 - "__ eaddl(r28, r14, r24, true);", // IID298 - "__ eandl(r30, r31, r26, false);", // IID299 - "__ eandl(r12, r31, r23, true);", // IID300 - "__ eimull(r9, r20, r10, false);", // IID301 - "__ eimull(r13, r30, r9, true);", // IID302 - "__ eorw(r25, r19, r23, false);", // IID303 - "__ eorw(r12, r16, rdx, true);", // IID304 - "__ eorl(r31, r17, r9, false);", // IID305 - "__ eorl(r15, r13, rbx, true);", // IID306 - "__ eshldl(r28, rbx, r29, false);", // IID307 - "__ eshldl(r22, rbx, r8, true);", // IID308 - "__ eshrdl(r8, r11, r16, false);", // IID309 - "__ eshrdl(r13, r12, r15, true);", // IID310 - "__ esubl(r17, r23, r31, false);", // IID311 - "__ esubl(r20, r22, r26, true);", // IID312 - "__ exorl(r10, r25, r19, false);", // IID313 - "__ exorl(r11, r19, r30, true);", // IID314 - "__ eshldl(r12, r10, rdx, 1, false);", // IID315 - "__ eshldl(r20, r30, r18, 16, true);", // IID316 - "__ eshrdl(r18, r25, r18, 8, false);", // IID317 - "__ eshrdl(r19, r16, r25, 1, true);", // IID318 - "__ ecmovl (Assembler::Condition::overflow, r11, r31, r24);", // IID319 - "__ ecmovl (Assembler::Condition::noOverflow, r14, r30, r16);", // IID320 - "__ ecmovl (Assembler::Condition::below, r9, r11, r26);", // IID321 - "__ ecmovl (Assembler::Condition::aboveEqual, r27, rdx, r31);", // IID322 - "__ ecmovl (Assembler::Condition::zero, r24, r29, r10);", // IID323 - "__ ecmovl (Assembler::Condition::notZero, rcx, r21, r15);", // IID324 - "__ ecmovl (Assembler::Condition::belowEqual, r23, r17, r26);", // IID325 - "__ ecmovl (Assembler::Condition::above, r20, r27, r13);", // IID326 - "__ ecmovl (Assembler::Condition::negative, r15, r22, r15);", // IID327 - "__ ecmovl (Assembler::Condition::positive, r29, r26, r18);", // IID328 - "__ ecmovl (Assembler::Condition::parity, r9, r9, r22);", // IID329 - "__ ecmovl (Assembler::Condition::noParity, r30, r23, r11);", // IID330 - "__ ecmovl (Assembler::Condition::less, r20, r11, rbx);", // IID331 - "__ ecmovl (Assembler::Condition::greaterEqual, r28, r16, r20);", // IID332 - "__ ecmovl (Assembler::Condition::lessEqual, r17, r24, r22);", // IID333 - "__ ecmovl (Assembler::Condition::greater, r16, r15, r15);", // IID334 - "__ ecmovl (Assembler::Condition::overflow, r28, r25, Address(r29, r16, (Address::ScaleFactor)2, -0x3c9110ad));", // IID335 - "__ ecmovl (Assembler::Condition::noOverflow, r23, r15, Address(rbx, r30, (Address::ScaleFactor)3, +0x1cbc58bd));", // IID336 - "__ ecmovl (Assembler::Condition::below, r26, rbx, Address(r12, rcx, (Address::ScaleFactor)3, +0x84e581a));", // IID337 - "__ ecmovl (Assembler::Condition::aboveEqual, rcx, r24, Address(r17, +0x5cece92d));", // IID338 - "__ ecmovl (Assembler::Condition::zero, r26, r24, Address(r24, r12, (Address::ScaleFactor)3, +0x507746a2));", // IID339 - "__ ecmovl (Assembler::Condition::notZero, r8, r15, Address(rcx, r19, (Address::ScaleFactor)0, -0xf035c76));", // IID340 - "__ ecmovl (Assembler::Condition::belowEqual, rdx, r23, Address(r22, r27, (Address::ScaleFactor)0, -0x12fe3534));", // IID341 - "__ ecmovl (Assembler::Condition::above, r30, r19, Address(r13, r28, (Address::ScaleFactor)0, +0x73b8ee9d));", // IID342 - "__ ecmovl (Assembler::Condition::negative, r22, r30, Address(r16, rcx, (Address::ScaleFactor)0, +0x22aac146));", // IID343 - "__ ecmovl (Assembler::Condition::positive, r17, r30, Address(r17, r9, (Address::ScaleFactor)2, +0x79db2b1));", // IID344 - "__ ecmovl (Assembler::Condition::parity, r26, rdx, Address(r14, r16, (Address::ScaleFactor)1, -0x8242011));", // IID345 - "__ ecmovl (Assembler::Condition::noParity, r11, r19, Address(r14, r31, (Address::ScaleFactor)1, -0x4ff251cc));", // IID346 - "__ ecmovl (Assembler::Condition::less, r20, r18, Address(r13, r16, (Address::ScaleFactor)2, -0x19efc6e2));", // IID347 - "__ ecmovl (Assembler::Condition::greaterEqual, r19, r13, Address(r13, r23, (Address::ScaleFactor)1, +0x611b7714));", // IID348 - "__ ecmovl (Assembler::Condition::lessEqual, r29, r13, Address(r17, r17, (Address::ScaleFactor)3, +0x3a94a93f));", // IID349 - "__ ecmovl (Assembler::Condition::greater, r13, r29, Address(r15, r23, (Address::ScaleFactor)1, +0x76d43532));", // IID350 - "__ adcq(r15, r13);", // IID351 - "__ cmpq(r9, r12);", // IID352 - "__ imulq(r15, r21);", // IID353 - "__ popcntq(r12, r9);", // IID354 - "__ sbbq(r17, r23);", // IID355 - "__ subq(rdx, r16);", // IID356 - "__ tzcntq(r29, r10);", // IID357 - "__ lzcntq(r21, r17);", // IID358 - "__ addq(r29, r18);", // IID359 - "__ andq(r28, r24);", // IID360 - "__ orq(r10, r20);", // IID361 - "__ xorq(r27, r10);", // IID362 - "__ movq(r14, r11);", // IID363 - "__ bsfq(r27, rcx);", // IID364 - "__ bsrq(r22, r15);", // IID365 - "__ btq(r31, r30);", // IID366 - "__ xchgq(r19, r19);", // IID367 - "__ testq(r26, r21);", // IID368 - "__ addq(Address(r26, r20, (Address::ScaleFactor)1, -0x4096149c), r14);", // IID369 - "__ andq(Address(r28, r20, (Address::ScaleFactor)2, +0x1bd8898a), r23);", // IID370 - "__ cmpq(Address(r15, r19, (Address::ScaleFactor)2, +0x39eee631), r10);", // IID371 - "__ orq(Address(r13, rdx, (Address::ScaleFactor)3, +0x1a49859), r13);", // IID372 - "__ xorq(Address(r21, +0x5fe8636), r24);", // IID373 - "__ subq(Address(r30, r23, (Address::ScaleFactor)2, -0x56643cc1), r25);", // IID374 - "__ movq(Address(r21, r26, (Address::ScaleFactor)3, +0x7e8544ab), r31);", // IID375 - "__ xaddq(Address(rcx, r24, (Address::ScaleFactor)3, -0x79ca4889), rbx);", // IID376 - "__ andq(Address(r13, r31, (Address::ScaleFactor)3, -0xd72b030), 256);", // IID377 - "__ addq(Address(r16, +0x534d775e), 268435456);", // IID378 - "__ cmpq(Address(r20, r15, (Address::ScaleFactor)2, -0x7cb22277), 268435456);", // IID379 - "__ sarq(Address(r9, r23, (Address::ScaleFactor)2, -0x72f6d86e), 4);", // IID380 - "__ salq(Address(r11, r24, (Address::ScaleFactor)1, -0x22826f95), 4);", // IID381 - "__ sbbq(Address(r14, r30, (Address::ScaleFactor)1, +0x1b43fc34), 268435456);", // IID382 - "__ shrq(Address(r26, r21, (Address::ScaleFactor)0, -0x3bae50c3), 8);", // IID383 - "__ subq(Address(r22, r10, (Address::ScaleFactor)3, +0x47e1403), 65536);", // IID384 - "__ xorq(Address(rdx, r19, (Address::ScaleFactor)3, -0x644a5318), 1);", // IID385 - "__ orq(Address(r30, r31, (Address::ScaleFactor)1, +0x2c93c783), 256);", // IID386 - "__ movq(Address(r26, r24, (Address::ScaleFactor)2, -0x534785f), 65536);", // IID387 - "__ testq(Address(r14, r30, (Address::ScaleFactor)1, +0x3932e147), -256);", // IID388 - "__ addq(r30, Address(r30, r24, (Address::ScaleFactor)3, -0x66e0235e));", // IID389 - "__ andq(r15, Address(r26, +0x36456e42));", // IID390 - "__ cmpq(r10, Address(r18, +0x5044bed));", // IID391 - "__ lzcntq(r31, Address(r12, rdx, (Address::ScaleFactor)2, -0x1707b7d4));", // IID392 - "__ orq(r16, Address(r20, r23, (Address::ScaleFactor)2, -0x26783729));", // IID393 - "__ adcq(r31, Address(r30, r31, (Address::ScaleFactor)0, +0x1ec3265d));", // IID394 - "__ imulq(r16, Address(rdx, r26, (Address::ScaleFactor)0, +0x3586831b));", // IID395 - "__ popcntq(r12, Address(r18, -0x3c3e9f7a));", // IID396 - "__ sbbq(rcx, Address(r8, r21, (Address::ScaleFactor)3, +0x6b1515ab));", // IID397 - "__ subq(r29, Address(rcx, r23, (Address::ScaleFactor)2, +0x4ff06c4d));", // IID398 - "__ tzcntq(r26, Address(r24, r10, (Address::ScaleFactor)1, -0x75d9a189));", // IID399 - "__ xorq(r17, Address(rbx, rbx, (Address::ScaleFactor)0, +0x4033d59c));", // IID400 - "__ movq(r18, Address(r22, r12, (Address::ScaleFactor)3, -0x3893347d));", // IID401 - "__ leaq(r12, Address(r20, r23, (Address::ScaleFactor)3, +0x4b311560));", // IID402 - "__ cvttsd2siq(r29, Address(r10, r28, (Address::ScaleFactor)2, +0x5c3a2657));", // IID403 - "__ xchgq(r22, Address(r13, r25, (Address::ScaleFactor)3, +0x1a3d6f3f));", // IID404 - "__ testq(r25, Address(r17, r24, (Address::ScaleFactor)3, -0x35addbd8));", // IID405 - "__ addq(r18, 1);", // IID406 - "__ andq(r13, 16777216);", // IID407 - "__ adcq(r13, 65536);", // IID408 - "__ cmpq(r10, 65536);", // IID409 - "__ rclq(r20, 2);", // IID410 - "__ rcrq(r9, 16);", // IID411 - "__ rolq(r8, 1);", // IID412 - "__ rorq(r25, 2);", // IID413 - "__ sarq(r22, 8);", // IID414 - "__ salq(r17, 1);", // IID415 - "__ sbbq(r31, 16);", // IID416 - "__ shlq(r27, 4);", // IID417 - "__ shrq(r28, 2);", // IID418 - "__ subq(rcx, 16777216);", // IID419 - "__ xorq(r27, 1048576);", // IID420 - "__ movq(r20, 268435456);", // IID421 - "__ mov64(r27, 4503599627370496);", // IID422 - "__ btq(r22, 4);", // IID423 - "__ testq(r8, -4096);", // IID424 - "__ orq_imm32(r28, 1048576);", // IID425 - "__ subq_imm32(r13, 65536);", // IID426 - "__ cmovq(Assembler::Condition::overflow, r16, Address(r16, -0x1389a3eb));", // IID427 - "__ cmovq(Assembler::Condition::noOverflow, rbx, Address(r29, r8, (Address::ScaleFactor)0, +0x1d022615));", // IID428 - "__ cmovq(Assembler::Condition::below, rdx, Address(r12, r28, (Address::ScaleFactor)1, -0x34c898e2));", // IID429 - "__ cmovq(Assembler::Condition::aboveEqual, r27, Address(r10, rcx, (Address::ScaleFactor)3, -0x1ef7abf1));", // IID430 - "__ cmovq(Assembler::Condition::zero, r14, Address(r13, r29, (Address::ScaleFactor)2, -0x7c4c8369));", // IID431 - "__ cmovq(Assembler::Condition::notZero, r15, Address(r23, rcx, (Address::ScaleFactor)2, -0x6bd22ccf));", // IID432 - "__ cmovq(Assembler::Condition::belowEqual, r24, Address(r15, r10, (Address::ScaleFactor)1, -0x7ffb3d09));", // IID433 - "__ cmovq(Assembler::Condition::above, r23, Address(r11, +0x276a863b));", // IID434 - "__ cmovq(Assembler::Condition::negative, r28, Address(r29, +0x3fb4396e));", // IID435 - "__ cmovq(Assembler::Condition::positive, r26, Address(r27, rcx, (Address::ScaleFactor)3, +0x4ddea61c));", // IID436 - "__ cmovq(Assembler::Condition::parity, r10, Address(r22, r19, (Address::ScaleFactor)1, +0x2a126966));", // IID437 - "__ cmovq(Assembler::Condition::noParity, r12, Address(r10, +0x3d7c59f));", // IID438 - "__ cmovq(Assembler::Condition::less, r10, Address(r8, r8, (Address::ScaleFactor)3, -0xe61862d));", // IID439 - "__ cmovq(Assembler::Condition::greaterEqual, r23, Address(r29, -0x777ed96d));", // IID440 - "__ cmovq(Assembler::Condition::lessEqual, rcx, Address(rbx, r19, (Address::ScaleFactor)1, +0x53c601cb));", // IID441 - "__ cmovq(Assembler::Condition::greater, r14, Address(r17, rbx, (Address::ScaleFactor)0, -0x768bf073));", // IID442 - "__ call(r29);", // IID443 - "__ divq(r10);", // IID444 - "__ idivq(r19);", // IID445 - "__ imulq(r15);", // IID446 - "__ mulq(r27);", // IID447 - "__ negq(r20);", // IID448 - "__ notq(r10);", // IID449 - "__ rolq(r16);", // IID450 - "__ rorq(r27);", // IID451 - "__ sarq(r9);", // IID452 - "__ salq(r13);", // IID453 - "__ shlq(r14);", // IID454 - "__ shrq(r18);", // IID455 - "__ incrementq(r28);", // IID456 - "__ decrementq(r28);", // IID457 - "__ pushp(r22);", // IID458 - "__ popp(r8);", // IID459 - "__ call(Address(r12, +0x64cc424e));", // IID460 - "__ mulq(Address(r26, r29, (Address::ScaleFactor)0, -0x466f085f));", // IID461 - "__ negq(Address(r21, r24, (Address::ScaleFactor)0, +0x2037df0b));", // IID462 - "__ sarq(Address(r12, r31, (Address::ScaleFactor)3, -0x57d225aa));", // IID463 - "__ salq(Address(r20, -0x1ea02f90));", // IID464 - "__ shrq(Address(r13, r20, (Address::ScaleFactor)3, +0x171081f2));", // IID465 - "__ incrementq(Address(r31, +0x13a808db));", // IID466 - "__ decrementq(Address(r19, -0x180d3ea1));", // IID467 - "__ imulq(r17, Address(r16, -0x2af2fd58), 4096);", // IID468 - "__ imulq(r28, r25, 16);", // IID469 - "__ shldq(r27, r13, 16);", // IID470 - "__ shrdq(r8, r10, 16);", // IID471 - "__ pop2(r14, r8);", // IID472 - "__ pop2p(r18, rbx);", // IID473 - "__ push2(r23, r19);", // IID474 - "__ push2p(r12, rbx);", // IID475 - "__ movzbq(r9, Address(r14, r23, (Address::ScaleFactor)3, -0x428d2646));", // IID476 - "__ movzwq(r28, Address(r9, rcx, (Address::ScaleFactor)2, -0x72611661));", // IID477 - "__ movsbq(rbx, Address(r24, r21, (Address::ScaleFactor)2, +0x3a6be990));", // IID478 - "__ movswq(r16, Address(r22, r10, (Address::ScaleFactor)0, +0x7ef8bdd));", // IID479 - "__ movzbq(r28, r14);", // IID480 - "__ movzwq(r13, r28);", // IID481 - "__ movsbq(r11, rdx);", // IID482 - "__ movswq(r12, r26);", // IID483 - "__ cmpxchgq(r20, Address(r10, -0xbd2a8da));", // IID484 - "__ eidivq(r15, false);", // IID485 - "__ eidivq(r23, true);", // IID486 - "__ edivq(r14, false);", // IID487 - "__ edivq(r14, true);", // IID488 - "__ eimulq(r15, false);", // IID489 - "__ eimulq(r20, true);", // IID490 - "__ emulq(rcx, false);", // IID491 - "__ emulq(r21, true);", // IID492 - "__ emulq(Address(r16, r10, (Address::ScaleFactor)3, +0x5f66ac1e), false);", // IID493 - "__ emulq(Address(r21, r22, (Address::ScaleFactor)3, -0xbbc807d), true);", // IID494 - "__ eimulq(r22, r26, false);", // IID495 - "__ eimulq(r25, r21, true);", // IID496 - "__ elzcntq(r20, r13, false);", // IID497 - "__ elzcntq(r25, r19, true);", // IID498 - "__ enegq(r21, r30, false);", // IID499 - "__ enegq(r29, r11, true);", // IID500 - "__ enotq(r22, r8);", // IID501 - "__ epopcntq(r12, r19, false);", // IID502 - "__ epopcntq(r29, r23, true);", // IID503 - "__ erolq(r28, r24, false);", // IID504 - "__ erolq(rdx, r20, true);", // IID505 - "__ erorq(rbx, r30, false);", // IID506 - "__ erorq(r10, r15, true);", // IID507 - "__ esalq(r17, r13, false);", // IID508 - "__ esalq(r21, r24, true);", // IID509 - "__ esarq(r31, r12, false);", // IID510 - "__ esarq(rdx, r24, true);", // IID511 - "__ edecq(r21, r24, false);", // IID512 - "__ edecq(r15, r31, true);", // IID513 - "__ eincq(r10, rbx, false);", // IID514 - "__ eincq(r18, r8, true);", // IID515 - "__ eshlq(r10, r26, false);", // IID516 - "__ eshlq(r28, r14, true);", // IID517 - "__ eshrq(r10, r19, false);", // IID518 - "__ eshrq(r28, r21, true);", // IID519 - "__ etzcntq(r21, r22, false);", // IID520 - "__ etzcntq(r16, r23, true);", // IID521 - "__ eimulq(r11, Address(r18, r9, (Address::ScaleFactor)2, -0x132285a1), false);", // IID522 - "__ eimulq(r13, Address(r24, r15, (Address::ScaleFactor)3, +0x48f50ca0), true);", // IID523 - "__ elzcntq(r9, Address(r13, +0x2115cf0e), false);", // IID524 - "__ elzcntq(r27, Address(r30, +0x49cabbb), true);", // IID525 - "__ enegq(r21, Address(r13, r31, (Address::ScaleFactor)2, +0x50a8f4d2), false);", // IID526 - "__ enegq(r22, Address(r18, r20, (Address::ScaleFactor)1, -0x5da0584c), true);", // IID527 - "__ epopcntq(r14, Address(rbx, r22, (Address::ScaleFactor)2, -0x606349d1), false);", // IID528 - "__ epopcntq(r26, Address(r23, r22, (Address::ScaleFactor)3, -0x72c66c23), true);", // IID529 - "__ esalq(r26, Address(r9, +0x334aba09), false);", // IID530 - "__ esalq(r9, Address(r9, r30, (Address::ScaleFactor)3, -0x219a6102), true);", // IID531 - "__ esarq(r25, Address(r20, -0x2131bab1), false);", // IID532 - "__ esarq(r16, Address(r28, r16, (Address::ScaleFactor)1, +0x48c483b9), true);", // IID533 - "__ edecq(r30, Address(r9, r16, (Address::ScaleFactor)0, -0x88ce84f), false);", // IID534 - "__ edecq(r11, Address(r30, r29, (Address::ScaleFactor)2, +0x3eeb8fd0), true);", // IID535 - "__ eincq(r26, Address(r29, r10, (Address::ScaleFactor)3, +0x3ef4822e), false);", // IID536 - "__ eincq(r29, Address(r19, r20, (Address::ScaleFactor)2, -0x3f0f3db9), true);", // IID537 - "__ eshrq(r8, Address(r30, r20, (Address::ScaleFactor)0, +0x15b56a17), false);", // IID538 - "__ eshrq(r26, Address(r11, -0x2de86561), true);", // IID539 - "__ etzcntq(r11, Address(rcx, r30, (Address::ScaleFactor)1, -0x32ffb1c2), false);", // IID540 - "__ etzcntq(r23, Address(r9, r12, (Address::ScaleFactor)1, -0x54823e69), true);", // IID541 - "__ eaddq(r20, Address(r13, rcx, (Address::ScaleFactor)3, -0x46116c0d), r15, false);", // IID542 - "__ eaddq(r13, Address(r9, r23, (Address::ScaleFactor)1, -0x286c7605), r16, true);", // IID543 - "__ eandq(r21, Address(r30, r17, (Address::ScaleFactor)0, +0xf4e30b2), r29, false);", // IID544 - "__ eandq(r30, Address(r17, r31, (Address::ScaleFactor)0, +0x3ab9dec4), r17, true);", // IID545 - "__ eorq(r10, Address(r27, r30, (Address::ScaleFactor)1, -0x197f1266), r28, false);", // IID546 - "__ eorq(r9, Address(r29, r30, (Address::ScaleFactor)0, -0x24ea9b08), r11, true);", // IID547 - "__ esubq(r15, Address(r14, -0x4f44bf90), r16, false);", // IID548 - "__ esubq(rcx, Address(r21, r18, (Address::ScaleFactor)1, -0x11d0ac8f), r28, true);", // IID549 - "__ exorq(r19, Address(r19, r18, (Address::ScaleFactor)0, -0xa5e55ec), r8, false);", // IID550 - "__ exorq(r28, Address(r17, r28, (Address::ScaleFactor)1, -0x6eb42fe0), r16, true);", // IID551 - "__ eaddq(r17, Address(r18, -0x60ab1105), 16777216, false);", // IID552 - "__ eaddq(r25, Address(r19, r25, (Address::ScaleFactor)0, +0x122444d9), 65536, true);", // IID553 - "__ eandq(r30, Address(r9, r28, (Address::ScaleFactor)1, -0x25b00cf3), 4096, false);", // IID554 - "__ eandq(r9, Address(r22, rbx, (Address::ScaleFactor)1, -0x7e465026), 268435456, true);", // IID555 - "__ eimulq(r12, Address(r25, r25, (Address::ScaleFactor)1, -0x432d68cc), 1, false);", // IID556 - "__ eimulq(r15, Address(r17, r31, (Address::ScaleFactor)3, -0x2b97565e), 16, true);", // IID557 - "__ eorq(r28, Address(rdx, r31, (Address::ScaleFactor)0, +0x3f1363b1), 256, false);", // IID558 - "__ eorq(r16, Address(r12, r23, (Address::ScaleFactor)3, -0x1785863c), 16777216, true);", // IID559 - "__ esalq(r8, Address(r14, r24, (Address::ScaleFactor)2, -0x714290a5), 2, false);", // IID560 - "__ esalq(r8, Address(r15, r14, (Address::ScaleFactor)2, +0x21f13243), 16, true);", // IID561 - "__ esarq(r10, Address(r13, r29, (Address::ScaleFactor)0, +0x7d04cb72), 2, false);", // IID562 - "__ esarq(r11, Address(r21, r31, (Address::ScaleFactor)3, -0x2176b4dc), 8, true);", // IID563 - "__ eshrq(rcx, Address(r16, r12, (Address::ScaleFactor)1, +0x260c9a38), 4, false);", // IID564 - "__ eshrq(r22, Address(r26, r9, (Address::ScaleFactor)0, -0x5e56bb62), 8, true);", // IID565 - "__ esubq(r31, Address(rbx, r28, (Address::ScaleFactor)1, +0x2b00bb10), 1, false);", // IID566 - "__ esubq(r21, Address(r31, -0x6c10f4ad), 4096, true);", // IID567 - "__ exorq(r11, Address(r23, r30, (Address::ScaleFactor)1, +0x51a6026b), 65536, false);", // IID568 - "__ exorq(r14, Address(r27, r10, (Address::ScaleFactor)2, -0x34ad9bab), 16, true);", // IID569 - "__ eaddq(r20, r23, 16777216, false);", // IID570 - "__ eaddq(r9, r21, 4096, true);", // IID571 - "__ eandq(r20, rdx, 16, false);", // IID572 - "__ eandq(r14, r19, 16, true);", // IID573 - "__ eimulq(r27, r17, 16, false);", // IID574 - "__ eimulq(r30, r13, 256, true);", // IID575 - "__ eorq(r19, r15, 16777216, false);", // IID576 - "__ eorq(r16, r28, 268435456, true);", // IID577 - "__ erclq(rbx, r24, 2);", // IID578 - "__ erolq(r15, r20, 16, false);", // IID579 - "__ erolq(r11, rcx, 16, true);", // IID580 - "__ erorq(r13, r26, 16, false);", // IID581 - "__ erorq(r19, r20, 4, true);", // IID582 - "__ esalq(r19, r28, 16, false);", // IID583 - "__ esalq(r25, r18, 4, true);", // IID584 - "__ esarq(r10, r27, 4, false);", // IID585 - "__ esarq(rdx, r22, 8, true);", // IID586 - "__ eshlq(r28, r15, 1, false);", // IID587 - "__ eshlq(rbx, r12, 4, true);", // IID588 - "__ eshrq(r26, r11, 1, false);", // IID589 - "__ eshrq(rdx, r31, 8, true);", // IID590 - "__ esubq(r21, rbx, 1048576, false);", // IID591 - "__ esubq(r25, r28, 65536, true);", // IID592 - "__ exorq(r22, r14, 1, false);", // IID593 - "__ exorq(r11, r30, 1048576, true);", // IID594 - "__ eorq_imm32(r20, r19, 1048576, false);", // IID595 - "__ eorq_imm32(r25, r13, 268435456, false);", // IID596 - "__ esubq_imm32(r25, r25, 268435456, false);", // IID597 - "__ esubq_imm32(r18, r11, 4194304, true);", // IID598 - "__ eaddq(r10, r18, Address(r20, +0x756f453), false);", // IID599 - "__ eaddq(rbx, r27, Address(r22, r21, (Address::ScaleFactor)0, -0x25abeab7), true);", // IID600 - "__ eandq(rdx, r31, Address(r9, r20, (Address::ScaleFactor)3, -0x4cfe39c), false);", // IID601 - "__ eandq(r16, r25, Address(r14, r27, (Address::ScaleFactor)0, +0x7c6654d9), true);", // IID602 - "__ eorq(r29, rcx, Address(r15, r23, (Address::ScaleFactor)0, +0x45b7f72d), false);", // IID603 - "__ eorq(r19, r17, Address(r13, r22, (Address::ScaleFactor)1, -0x750c1996), true);", // IID604 - "__ eimulq(r13, r8, Address(r31, r23, (Address::ScaleFactor)1, -0x2211b6b2), false);", // IID605 - "__ eimulq(r11, r28, Address(r13, r11, (Address::ScaleFactor)3, +0x5c0013ab), true);", // IID606 - "__ esubq(rdx, r18, Address(r18, rcx, (Address::ScaleFactor)0, +0x59557e71), false);", // IID607 - "__ esubq(r27, r11, Address(r22, -0x28469649), true);", // IID608 - "__ exorq(r10, r9, Address(r24, +0x49691d54), false);", // IID609 - "__ exorq(r24, r12, Address(r19, +0x22d529aa), true);", // IID610 - "__ eaddq(r20, r9, r10, false);", // IID611 - "__ eaddq(r18, r17, r26, true);", // IID612 - "__ eadcxq(r21, r16, r19);", // IID613 - "__ eadoxq(rbx, r14, r27);", // IID614 - "__ eandq(r9, r12, r22, false);", // IID615 - "__ eandq(r17, r25, r10, true);", // IID616 - "__ eimulq(r12, r15, r14, false);", // IID617 - "__ eimulq(r29, r18, r16, true);", // IID618 - "__ eorq(r11, r9, r10, false);", // IID619 - "__ eorq(r25, r13, r16, true);", // IID620 - "__ esubq(r11, r21, r25, false);", // IID621 - "__ esubq(rdx, r20, rbx, true);", // IID622 - "__ exorq(r25, r21, r26, false);", // IID623 - "__ exorq(r23, r27, r21, true);", // IID624 - "__ eshldq(r10, r12, r31, 2, false);", // IID625 - "__ eshldq(r23, r16, r29, 2, true);", // IID626 - "__ eshrdq(r19, r24, r23, 4, false);", // IID627 - "__ eshrdq(r21, r15, r25, 4, true);", // IID628 - "__ ecmovq (Assembler::Condition::overflow, r9, r29, rdx);", // IID629 - "__ ecmovq (Assembler::Condition::noOverflow, r11, r25, r19);", // IID630 - "__ ecmovq (Assembler::Condition::below, r10, r16, r17);", // IID631 - "__ ecmovq (Assembler::Condition::aboveEqual, r8, r23, r31);", // IID632 - "__ ecmovq (Assembler::Condition::zero, r9, r31, rbx);", // IID633 - "__ ecmovq (Assembler::Condition::notZero, r16, r29, r9);", // IID634 - "__ ecmovq (Assembler::Condition::belowEqual, r24, r10, r9);", // IID635 - "__ ecmovq (Assembler::Condition::above, r22, r28, r26);", // IID636 - "__ ecmovq (Assembler::Condition::negative, r18, r25, r20);", // IID637 - "__ ecmovq (Assembler::Condition::positive, r16, r21, rbx);", // IID638 - "__ ecmovq (Assembler::Condition::parity, r28, r22, r19);", // IID639 - "__ ecmovq (Assembler::Condition::noParity, r13, r15, rdx);", // IID640 - "__ ecmovq (Assembler::Condition::less, r8, r22, r14);", // IID641 - "__ ecmovq (Assembler::Condition::greaterEqual, r12, r24, r14);", // IID642 - "__ ecmovq (Assembler::Condition::lessEqual, r24, r13, r21);", // IID643 - "__ ecmovq (Assembler::Condition::greater, rbx, rbx, r27);", // IID644 - "__ ecmovq (Assembler::Condition::overflow, r14, r17, Address(r24, r27, (Address::ScaleFactor)3, +0x9d508f0));", // IID645 - "__ ecmovq (Assembler::Condition::noOverflow, r13, r15, Address(r31, r21, (Address::ScaleFactor)2, +0x6ef2c74a));", // IID646 - "__ ecmovq (Assembler::Condition::below, r13, r27, Address(r31, r25, (Address::ScaleFactor)1, +0x734fe9ab));", // IID647 - "__ ecmovq (Assembler::Condition::aboveEqual, r15, r22, Address(r14, r29, (Address::ScaleFactor)2, -0x67d8bdfb));", // IID648 - "__ ecmovq (Assembler::Condition::zero, r30, r23, Address(r15, r28, (Address::ScaleFactor)1, -0x2686219));", // IID649 - "__ ecmovq (Assembler::Condition::notZero, r12, r9, Address(r9, r25, (Address::ScaleFactor)3, +0x52aab6b));", // IID650 - "__ ecmovq (Assembler::Condition::belowEqual, r9, r25, Address(r8, r8, (Address::ScaleFactor)3, -0x1e42bd95));", // IID651 - "__ ecmovq (Assembler::Condition::above, rcx, r20, Address(r27, rbx, (Address::ScaleFactor)2, +0x46823c58));", // IID652 - "__ ecmovq (Assembler::Condition::negative, rbx, r12, Address(r21, -0x635b8c8));", // IID653 - "__ ecmovq (Assembler::Condition::positive, r23, rbx, Address(r27, r26, (Address::ScaleFactor)3, +0x922bcc0));", // IID654 - "__ ecmovq (Assembler::Condition::parity, r25, r9, Address(r23, +0xd2a14ec));", // IID655 - "__ ecmovq (Assembler::Condition::noParity, r11, r19, Address(r11, -0xfb95a9d));", // IID656 - "__ ecmovq (Assembler::Condition::less, r13, r18, Address(r28, r19, (Address::ScaleFactor)0, +0x716b9b7e));", // IID657 - "__ ecmovq (Assembler::Condition::greaterEqual, r21, r16, Address(rcx, r29, (Address::ScaleFactor)0, -0x5af0441e));", // IID658 - "__ ecmovq (Assembler::Condition::lessEqual, r12, r31, Address(r20, r26, (Address::ScaleFactor)0, +0xe0b7fb1));", // IID659 - "__ ecmovq (Assembler::Condition::greater, r15, r24, Address(r30, +0x2d3b7b4f));", // IID660 + "__ eaddl(rax, r11, 65536, false);", // IID255 + "__ eaddl(r24, r16, 268435456, true);", // IID256 + "__ eaddl(rax, r18, 268435456, true);", // IID257 + "__ eandl(r29, r13, 1, false);", // IID258 + "__ eandl(rax, r13, 1, false);", // IID259 + "__ eandl(r31, r22, 1, true);", // IID260 + "__ eandl(rax, r29, 1, true);", // IID261 + "__ eimull(r23, r29, 65536, false);", // IID262 + "__ eimull(rax, r15, 65536, false);", // IID263 + "__ eimull(r21, r9, 268435456, true);", // IID264 + "__ eimull(rax, r15, 268435456, true);", // IID265 + "__ eorl(rdx, r18, 65536, false);", // IID266 + "__ eorl(rax, r15, 65536, false);", // IID267 + "__ eorl(r8, r9, 256, true);", // IID268 + "__ eorl(rax, r27, 256, true);", // IID269 + "__ ercll(r9, r15, 8);", // IID270 + "__ ercll(rax, r18, 8);", // IID271 + "__ eroll(r12, rbx, 16, false);", // IID272 + "__ eroll(rax, r19, 16, false);", // IID273 + "__ eroll(r10, r11, 16, true);", // IID274 + "__ eroll(rax, r18, 16, true);", // IID275 + "__ erorl(rdx, r14, 1, false);", // IID276 + "__ erorl(rax, r22, 1, false);", // IID277 + "__ erorl(r25, r31, 16, true);", // IID278 + "__ erorl(rax, r19, 16, true);", // IID279 + "__ esall(r9, r15, 2, false);", // IID280 + "__ esall(rax, r13, 2, false);", // IID281 + "__ esall(r21, r16, 1, true);", // IID282 + "__ esall(rax, r21, 1, true);", // IID283 + "__ esarl(r26, r23, 8, false);", // IID284 + "__ esarl(rax, r28, 8, false);", // IID285 + "__ esarl(r26, r14, 4, true);", // IID286 + "__ esarl(rax, r10, 4, true);", // IID287 + "__ eshll(r22, r9, 1, false);", // IID288 + "__ eshll(rax, r18, 1, false);", // IID289 + "__ eshll(r30, r24, 16, true);", // IID290 + "__ eshll(rax, r23, 16, true);", // IID291 + "__ eshrl(r11, r8, 16, false);", // IID292 + "__ eshrl(rax, r16, 16, false);", // IID293 + "__ eshrl(r11, r12, 8, true);", // IID294 + "__ eshrl(rax, r29, 8, true);", // IID295 + "__ esubl(r16, r21, 1048576, false);", // IID296 + "__ esubl(rax, r15, 1048576, false);", // IID297 + "__ esubl(r9, r18, 16777216, true);", // IID298 +#endif // _LP64 + "__ esubl(rax, rbx, 16777216, true);", // IID299 +#ifdef _LP64 + "__ exorl(r19, r23, 65536, false);", // IID300 + "__ exorl(rax, r17, 65536, false);", // IID301 + "__ exorl(r29, r18, 1048576, true);", // IID302 + "__ exorl(rax, r14, 1048576, true);", // IID303 + "__ esubl_imm32(r19, r15, 16777216, false);", // IID304 + "__ esubl_imm32(rax, r27, 16777216, false);", // IID305 + "__ esubl_imm32(r23, r27, 1073741824, true);", // IID306 + "__ esubl_imm32(rax, r23, 1073741824, true);", // IID307 + "__ eaddl(r8, r12, Address(r28, r24, (Address::ScaleFactor)3, -0x6d6d7e68), false);", // IID308 + "__ eaddl(r24, r13, Address(r24, r25, (Address::ScaleFactor)3, +0x784673fd), true);", // IID309 + "__ eandl(r24, r21, Address(r8, r13, (Address::ScaleFactor)2, -0x63663889), false);", // IID310 + "__ eandl(r12, r24, Address(r30, -0x67526556), true);", // IID311 + "__ eimull(r13, r13, Address(rbx, r25, (Address::ScaleFactor)2, -0x5f394dd9), false);", // IID312 + "__ eimull(r26, r25, Address(r25, rdx, (Address::ScaleFactor)3, -0x2e39f79a), true);", // IID313 + "__ eorl(r28, r8, Address(rdx, r24, (Address::ScaleFactor)3, -0xed99a54), false);", // IID314 + "__ eorl(r31, r22, Address(r30, r20, (Address::ScaleFactor)3, +0x3ac41cbd), true);", // IID315 + "__ esubl(r24, r30, Address(r13, r17, (Address::ScaleFactor)1, +0x1efdc2e3), false);", // IID316 + "__ esubl(r16, r16, Address(r9, r15, (Address::ScaleFactor)1, +0x769feb34), true);", // IID317 + "__ exorl(r19, r25, Address(r10, +0x2239b429), false);", // IID318 + "__ exorl(r25, r19, Address(r16, r24, (Address::ScaleFactor)1, +0x1c71faea), true);", // IID319 + "__ exorb(r19, r10, Address(r28, -0x299a0cfd), false);", // IID320 + "__ exorb(rbx, r28, Address(r23, r24, (Address::ScaleFactor)1, -0x5d78ddd9), true);", // IID321 + "__ exorw(r10, r9, Address(r13, r30, (Address::ScaleFactor)2, +0x11151188), false);", // IID322 + "__ exorw(r16, r17, Address(rdx, r31, (Address::ScaleFactor)0, +0x61936ce7), true);", // IID323 + "__ eaddl(r13, rbx, r28, false);", // IID324 + "__ eaddl(rbx, r29, r22, true);", // IID325 + "__ eandl(rbx, r8, r8, false);", // IID326 + "__ eandl(r11, r16, r13, true);", // IID327 + "__ eimull(r12, r15, r17, false);", // IID328 + "__ eimull(r23, r31, r20, true);", // IID329 + "__ eorw(r22, r26, r10, false);", // IID330 + "__ eorw(r25, r19, r11, true);", // IID331 + "__ eorl(r19, r30, r8, false);", // IID332 + "__ eorl(r12, r10, rdx, true);", // IID333 + "__ eshldl(r22, r20, r30, false);", // IID334 + "__ eshldl(r18, r19, r18, true);", // IID335 + "__ eshrdl(r25, r18, rcx, false);", // IID336 + "__ eshrdl(r19, r16, r25, true);", // IID337 + "__ esubl(r11, r31, r24, false);", // IID338 + "__ esubl(r14, r30, r16, true);", // IID339 + "__ exorl(r9, r11, r26, false);", // IID340 + "__ exorl(r27, rdx, r31, true);", // IID341 + "__ eshldl(r29, r10, rcx, 16, false);", // IID342 + "__ eshldl(r15, r23, r17, 16, true);", // IID343 + "__ eshrdl(r27, r13, r15, 8, false);", // IID344 + "__ eshrdl(r15, r29, r26, 16, true);", // IID345 + "__ ecmovl (Assembler::Condition::overflow, r18, r9, r9);", // IID346 + "__ ecmovl (Assembler::Condition::noOverflow, r22, r30, r23);", // IID347 + "__ ecmovl (Assembler::Condition::below, r11, r20, r11);", // IID348 + "__ ecmovl (Assembler::Condition::aboveEqual, rbx, r28, r16);", // IID349 + "__ ecmovl (Assembler::Condition::zero, r20, r17, r24);", // IID350 + "__ ecmovl (Assembler::Condition::notZero, r22, r16, r15);", // IID351 + "__ ecmovl (Assembler::Condition::belowEqual, r15, r28, r29);", // IID352 + "__ ecmovl (Assembler::Condition::above, r16, r25, r25);", // IID353 + "__ ecmovl (Assembler::Condition::negative, r17, r13, r17);", // IID354 + "__ ecmovl (Assembler::Condition::positive, r23, rbx, r30);", // IID355 + "__ ecmovl (Assembler::Condition::parity, r15, r22, r11);", // IID356 + "__ ecmovl (Assembler::Condition::noParity, r27, rdx, r22);", // IID357 + "__ ecmovl (Assembler::Condition::less, r9, r17, r28);", // IID358 + "__ ecmovl (Assembler::Condition::greaterEqual, r24, r11, r26);", // IID359 + "__ ecmovl (Assembler::Condition::lessEqual, r12, rcx, rbx);", // IID360 + "__ ecmovl (Assembler::Condition::greater, r28, r22, r22);", // IID361 + "__ ecmovl (Assembler::Condition::overflow, r10, r14, Address(rcx, r17, (Address::ScaleFactor)3, -0x7857b23d));", // IID362 + "__ ecmovl (Assembler::Condition::noOverflow, r17, r12, Address(r26, r24, (Address::ScaleFactor)3, +0x10642223));", // IID363 + "__ ecmovl (Assembler::Condition::below, r26, r8, Address(r31, -0xb2d2be4));", // IID364 + "__ ecmovl (Assembler::Condition::aboveEqual, r12, r20, Address(r12, r22, (Address::ScaleFactor)2, -0x667ff72b));", // IID365 + "__ ecmovl (Assembler::Condition::zero, r22, r9, Address(r27, r23, (Address::ScaleFactor)2, +0x66ce4d22));", // IID366 + "__ ecmovl (Assembler::Condition::notZero, r12, r8, Address(r30, r27, (Address::ScaleFactor)3, -0x2b9676e1));", // IID367 + "__ ecmovl (Assembler::Condition::belowEqual, r17, r20, Address(r9, r30, (Address::ScaleFactor)3, -0x351022df));", // IID368 + "__ ecmovl (Assembler::Condition::above, rdx, r8, Address(r14, +0x3d6b7a59));", // IID369 + "__ ecmovl (Assembler::Condition::negative, rcx, r31, Address(r11, r14, (Address::ScaleFactor)2, +0x2cd585f2));", // IID370 + "__ ecmovl (Assembler::Condition::positive, r25, r18, Address(r24, r11, (Address::ScaleFactor)2, -0x3f699c34));", // IID371 + "__ ecmovl (Assembler::Condition::parity, r18, r8, Address(r19, r17, (Address::ScaleFactor)2, -0x390da4c5));", // IID372 + "__ ecmovl (Assembler::Condition::noParity, r11, r29, Address(r29, rdx, (Address::ScaleFactor)2, +0x3a94a93f));", // IID373 + "__ ecmovl (Assembler::Condition::less, r13, r29, Address(r15, r23, (Address::ScaleFactor)1, +0x76d43532));", // IID374 + "__ ecmovl (Assembler::Condition::greaterEqual, r15, r12, Address(r13, r9, (Address::ScaleFactor)1, +0x16f7a5b));", // IID375 + "__ ecmovl (Assembler::Condition::lessEqual, r9, rdx, Address(r17, r23, (Address::ScaleFactor)1, +0x43b6bfe1));", // IID376 + "__ ecmovl (Assembler::Condition::greater, r28, r20, Address(r24, r10, (Address::ScaleFactor)0, -0x326e802f));", // IID377 + "__ adcq(r27, rcx);", // IID378 + "__ cmpq(r22, r15);", // IID379 + "__ imulq(r31, r30);", // IID380 + "__ popcntq(r19, r19);", // IID381 + "__ sbbq(r26, r21);", // IID382 + "__ subq(r14, r26);", // IID383 + "__ tzcntq(r20, r15);", // IID384 + "__ lzcntq(r12, r13);", // IID385 + "__ addq(r23, r28);", // IID386 + "__ andq(r20, r20);", // IID387 + "__ orq(r24, r11);", // IID388 + "__ xorq(r10, r15);", // IID389 + "__ movq(r19, r20);", // IID390 + "__ bsfq(r23, r15);", // IID391 + "__ bsrq(r26, r19);", // IID392 + "__ btq(r24, r23);", // IID393 + "__ xchgq(r28, r11);", // IID394 + "__ testq(r13, r13);", // IID395 + "__ addq(Address(r31, r23, (Address::ScaleFactor)3, +0x59da0437), rdx);", // IID396 + "__ andq(Address(r21, r20, (Address::ScaleFactor)3, +0x6fd0d557), r27);", // IID397 + "__ cmpq(Address(r21, +0x23ef6744), r11);", // IID398 + "__ orq(Address(r10, rcx, (Address::ScaleFactor)3, +0x7e8544ab), rcx);", // IID399 + "__ xorq(Address(rcx, r24, (Address::ScaleFactor)3, -0x79ca4889), rbx);", // IID400 + "__ subq(Address(r27, r31, (Address::ScaleFactor)0, +0x11f85f9a), r27);", // IID401 + "__ movq(Address(r20, r16, (Address::ScaleFactor)3, +0x72158dda), r17);", // IID402 + "__ xaddq(Address(r29, r9, (Address::ScaleFactor)2, +0x6e8febd1), r12);", // IID403 + "__ andq(Address(r15, -0x47c94ecd), 268435456);", // IID404 + "__ addq(Address(r23, r19, (Address::ScaleFactor)1, +0x32bfde3f), 256);", // IID405 + "__ cmpq(Address(r15, r11, (Address::ScaleFactor)3, +0x548e7560), 4096);", // IID406 + "__ sarq(Address(r20, r14, (Address::ScaleFactor)1, +0x1b43fc34), 2);", // IID407 + "__ salq(Address(r26, r21, (Address::ScaleFactor)0, -0x3bae50c3), 8);", // IID408 + "__ sbbq(Address(r22, r10, (Address::ScaleFactor)3, +0x47e1403), 65536);", // IID409 + "__ shrq(Address(rcx, rdx, (Address::ScaleFactor)2, +0x7ea3924d), 16);", // IID410 + "__ subq(Address(rcx, r26, (Address::ScaleFactor)3, -0x356ea53e), 16);", // IID411 + "__ xorq(Address(r30, r26, (Address::ScaleFactor)2, +0x78a12f5c), 16);", // IID412 + "__ orq(Address(r11, r10, (Address::ScaleFactor)1, +0x3713b5b5), 268435456);", // IID413 + "__ movq(Address(r30, r30, (Address::ScaleFactor)3, +0x2541a10), 65536);", // IID414 + "__ testq(Address(r16, r15, (Address::ScaleFactor)3, +0x558e3251), -16);", // IID415 + "__ addq(r27, Address(r8, r10, (Address::ScaleFactor)2, +0x635f732d));", // IID416 + "__ andq(r21, Address(r12, r31, (Address::ScaleFactor)0, -0x75e8c4a0));", // IID417 + "__ cmpq(r18, Address(r19, r16, (Address::ScaleFactor)2, -0x120ae81e));", // IID418 + "__ lzcntq(rbx, Address(r31, r30, (Address::ScaleFactor)0, +0x1ec3265d));", // IID419 + "__ orq(r16, Address(rdx, r26, (Address::ScaleFactor)0, +0x3586831b));", // IID420 + "__ adcq(r12, Address(r18, -0x3c3e9f7a));", // IID421 + "__ imulq(rcx, Address(r8, r21, (Address::ScaleFactor)3, +0x6b1515ab));", // IID422 + "__ popcntq(r29, Address(rcx, r23, (Address::ScaleFactor)2, +0x4ff06c4d));", // IID423 + "__ sbbq(r26, Address(r24, r10, (Address::ScaleFactor)1, -0x75d9a189));", // IID424 + "__ subq(r17, Address(rbx, rbx, (Address::ScaleFactor)0, +0x4033d59c));", // IID425 + "__ tzcntq(r18, Address(r22, r12, (Address::ScaleFactor)3, -0x3893347d));", // IID426 + "__ xorq(r12, Address(r20, r23, (Address::ScaleFactor)3, +0x4b311560));", // IID427 + "__ movq(r29, Address(r10, r28, (Address::ScaleFactor)2, +0x5c3a2657));", // IID428 + "__ leaq(r22, Address(r13, r25, (Address::ScaleFactor)3, +0x1a3d6f3f));", // IID429 + "__ cvttsd2siq(r25, Address(r17, r24, (Address::ScaleFactor)3, -0x35addbd8));", // IID430 + "__ xchgq(r18, Address(r25, +0x632184c3));", // IID431 + "__ testq(r29, Address(r18, r13, (Address::ScaleFactor)1, -0x5039fd8a));", // IID432 + "__ addq(r20, 4096);", // IID433 + "__ andq(r9, 16);", // IID434 + "__ adcq(rdx, 256);", // IID435 + "__ cmpq(r22, 16777216);", // IID436 + "__ rclq(r17, 1);", // IID437 + "__ rcrq(r31, 1);", // IID438 + "__ rolq(r27, 4);", // IID439 + "__ rorq(r28, 2);", // IID440 + "__ sarq(rcx, 16);", // IID441 + "__ salq(r31, 8);", // IID442 + "__ sbbq(r27, 1048576);", // IID443 + "__ shlq(r20, 16);", // IID444 + "__ shrq(r31, 8);", // IID445 + "__ subq(r27, 1048576);", // IID446 + "__ xorq(r22, 4096);", // IID447 + "__ movq(r8, 4096);", // IID448 + "__ mov64(r28, 1099511627776);", // IID449 + "__ btq(r13, 1);", // IID450 + "__ testq(r16, -1048576);", // IID451 + "__ orq_imm32(r20, 262144);", // IID452 + "__ subq_imm32(r18, 1048576);", // IID453 + "__ cmovq(Assembler::Condition::overflow, rbx, Address(r29, r8, (Address::ScaleFactor)0, +0x1d022615));", // IID454 + "__ cmovq(Assembler::Condition::noOverflow, rdx, Address(r12, r28, (Address::ScaleFactor)1, -0x34c898e2));", // IID455 + "__ cmovq(Assembler::Condition::below, r27, Address(r10, rcx, (Address::ScaleFactor)3, -0x1ef7abf1));", // IID456 + "__ cmovq(Assembler::Condition::aboveEqual, r14, Address(r13, r29, (Address::ScaleFactor)2, -0x7c4c8369));", // IID457 + "__ cmovq(Assembler::Condition::zero, r15, Address(r23, rcx, (Address::ScaleFactor)2, -0x6bd22ccf));", // IID458 + "__ cmovq(Assembler::Condition::notZero, r24, Address(r15, r10, (Address::ScaleFactor)1, -0x7ffb3d09));", // IID459 + "__ cmovq(Assembler::Condition::belowEqual, r23, Address(r11, +0x276a863b));", // IID460 + "__ cmovq(Assembler::Condition::above, r28, Address(r29, +0x3fb4396e));", // IID461 + "__ cmovq(Assembler::Condition::negative, r26, Address(r27, rcx, (Address::ScaleFactor)3, +0x4ddea61c));", // IID462 + "__ cmovq(Assembler::Condition::positive, r10, Address(r22, r19, (Address::ScaleFactor)1, +0x2a126966));", // IID463 + "__ cmovq(Assembler::Condition::parity, r12, Address(r10, +0x3d7c59f));", // IID464 + "__ cmovq(Assembler::Condition::noParity, r10, Address(r8, r8, (Address::ScaleFactor)3, -0xe61862d));", // IID465 + "__ cmovq(Assembler::Condition::less, r23, Address(r29, -0x777ed96d));", // IID466 + "__ cmovq(Assembler::Condition::greaterEqual, rcx, Address(rbx, r19, (Address::ScaleFactor)1, +0x53c601cb));", // IID467 + "__ cmovq(Assembler::Condition::lessEqual, r14, Address(r17, rbx, (Address::ScaleFactor)0, -0x768bf073));", // IID468 + "__ cmovq(Assembler::Condition::greater, r29, Address(r10, r19, (Address::ScaleFactor)1, +0x30c98d3c));", // IID469 + "__ call(r10);", // IID470 + "__ divq(r16);", // IID471 + "__ idivq(r27);", // IID472 + "__ imulq(r9);", // IID473 + "__ mulq(r13);", // IID474 + "__ negq(r14);", // IID475 + "__ notq(r18);", // IID476 + "__ rolq(r28);", // IID477 + "__ rorq(r28);", // IID478 + "__ sarq(r22);", // IID479 + "__ salq(r8);", // IID480 + "__ shlq(r12);", // IID481 + "__ shrq(rbx);", // IID482 + "__ incrementq(rcx);", // IID483 + "__ decrementq(r23);", // IID484 + "__ pushp(rcx);", // IID485 + "__ popp(r26);", // IID486 + "__ call(Address(r29, r10, (Address::ScaleFactor)0, +0x5655bc9f));", // IID487 + "__ mulq(Address(rdx, r21, (Address::ScaleFactor)3, -0x6798a630));", // IID488 + "__ negq(Address(r31, r24, (Address::ScaleFactor)0, -0x20071802));", // IID489 + "__ sarq(Address(r21, rdx, (Address::ScaleFactor)2, -0x343cb9e5));", // IID490 + "__ salq(Address(r20, r24, (Address::ScaleFactor)3, +0xa667574));", // IID491 + "__ shrq(Address(r27, +0x76b77974));", // IID492 + "__ incrementq(Address(r25, -0x534e8d31));", // IID493 + "__ decrementq(Address(r20, -0x180d3ea1));", // IID494 + "__ imulq(r17, Address(r16, -0x2af2fd58), 4096);", // IID495 + "__ imulq(r28, r25, 16);", // IID496 + "__ shldq(r27, r13, 16);", // IID497 + "__ shrdq(r8, r10, 16);", // IID498 + "__ pop2(r14, r8);", // IID499 + "__ pop2p(r18, rbx);", // IID500 + "__ push2(r23, r19);", // IID501 + "__ push2p(r12, rbx);", // IID502 + "__ movzbq(r9, Address(r14, r23, (Address::ScaleFactor)3, -0x428d2646));", // IID503 + "__ movzwq(r28, Address(r9, rcx, (Address::ScaleFactor)2, -0x72611661));", // IID504 + "__ movsbq(rbx, Address(r24, r21, (Address::ScaleFactor)2, +0x3a6be990));", // IID505 + "__ movswq(r16, Address(r22, r10, (Address::ScaleFactor)0, +0x7ef8bdd));", // IID506 + "__ movzbq(r28, r14);", // IID507 + "__ movzwq(r13, r28);", // IID508 + "__ movsbq(r11, rdx);", // IID509 + "__ movswq(r12, r26);", // IID510 + "__ cmpxchgq(r20, Address(r10, -0xbd2a8da));", // IID511 + "__ eidivq(r15, false);", // IID512 + "__ eidivq(r23, true);", // IID513 + "__ edivq(r14, false);", // IID514 + "__ edivq(r14, true);", // IID515 + "__ eimulq(r15, false);", // IID516 + "__ eimulq(r20, true);", // IID517 + "__ emulq(rcx, false);", // IID518 + "__ emulq(r21, true);", // IID519 + "__ emulq(Address(r16, r10, (Address::ScaleFactor)3, +0x5f66ac1e), false);", // IID520 + "__ emulq(Address(r21, r22, (Address::ScaleFactor)3, -0xbbc807d), true);", // IID521 + "__ eimulq(r22, r26, false);", // IID522 + "__ eimulq(r25, r21, true);", // IID523 + "__ elzcntq(r20, r13, false);", // IID524 + "__ elzcntq(r25, r19, true);", // IID525 + "__ enegq(r21, r30, false);", // IID526 + "__ enegq(r29, r11, true);", // IID527 + "__ enotq(r22, r8);", // IID528 + "__ epopcntq(r12, r19, false);", // IID529 + "__ epopcntq(r29, r23, true);", // IID530 + "__ erolq(r28, r24, false);", // IID531 + "__ erolq(rdx, r20, true);", // IID532 + "__ erorq(rbx, r30, false);", // IID533 + "__ erorq(r10, r15, true);", // IID534 + "__ esalq(r17, r13, false);", // IID535 + "__ esalq(r21, r24, true);", // IID536 + "__ esarq(r31, r12, false);", // IID537 + "__ esarq(rdx, r24, true);", // IID538 + "__ edecq(r21, r24, false);", // IID539 + "__ edecq(r15, r31, true);", // IID540 + "__ eincq(r10, rbx, false);", // IID541 + "__ eincq(r18, r8, true);", // IID542 + "__ eshlq(r10, r26, false);", // IID543 + "__ eshlq(r28, r14, true);", // IID544 + "__ eshrq(r10, r19, false);", // IID545 + "__ eshrq(r28, r21, true);", // IID546 + "__ etzcntq(r21, r22, false);", // IID547 + "__ etzcntq(r16, r23, true);", // IID548 + "__ eimulq(r11, Address(r18, r9, (Address::ScaleFactor)2, -0x132285a1), false);", // IID549 + "__ eimulq(r13, Address(r24, r15, (Address::ScaleFactor)3, +0x48f50ca0), true);", // IID550 + "__ elzcntq(r9, Address(r13, +0x2115cf0e), false);", // IID551 + "__ elzcntq(r27, Address(r30, +0x49cabbb), true);", // IID552 + "__ enegq(r21, Address(r13, r31, (Address::ScaleFactor)2, +0x50a8f4d2), false);", // IID553 + "__ enegq(r22, Address(r18, r20, (Address::ScaleFactor)1, -0x5da0584c), true);", // IID554 + "__ epopcntq(r14, Address(rbx, r22, (Address::ScaleFactor)2, -0x606349d1), false);", // IID555 + "__ epopcntq(r26, Address(r23, r22, (Address::ScaleFactor)3, -0x72c66c23), true);", // IID556 + "__ esalq(r26, Address(r9, +0x334aba09), false);", // IID557 + "__ esalq(r9, Address(r9, r30, (Address::ScaleFactor)3, -0x219a6102), true);", // IID558 + "__ esarq(r25, Address(r20, -0x2131bab1), false);", // IID559 + "__ esarq(r16, Address(r28, r16, (Address::ScaleFactor)1, +0x48c483b9), true);", // IID560 + "__ edecq(r30, Address(r9, r16, (Address::ScaleFactor)0, -0x88ce84f), false);", // IID561 + "__ edecq(r11, Address(r30, r29, (Address::ScaleFactor)2, +0x3eeb8fd0), true);", // IID562 + "__ eincq(r26, Address(r29, r10, (Address::ScaleFactor)3, +0x3ef4822e), false);", // IID563 + "__ eincq(r29, Address(r19, r20, (Address::ScaleFactor)2, -0x3f0f3db9), true);", // IID564 + "__ eshrq(r8, Address(r30, r20, (Address::ScaleFactor)0, +0x15b56a17), false);", // IID565 + "__ eshrq(r26, Address(r11, -0x2de86561), true);", // IID566 + "__ etzcntq(r11, Address(rcx, r30, (Address::ScaleFactor)1, -0x32ffb1c2), false);", // IID567 + "__ etzcntq(r23, Address(r9, r12, (Address::ScaleFactor)1, -0x54823e69), true);", // IID568 + "__ eaddq(r20, Address(r13, rcx, (Address::ScaleFactor)3, -0x46116c0d), r15, false);", // IID569 + "__ eaddq(r13, Address(r9, r23, (Address::ScaleFactor)1, -0x286c7605), r16, true);", // IID570 + "__ eandq(r21, Address(r30, r17, (Address::ScaleFactor)0, +0xf4e30b2), r29, false);", // IID571 + "__ eandq(r30, Address(r17, r31, (Address::ScaleFactor)0, +0x3ab9dec4), r17, true);", // IID572 + "__ eorq(r10, Address(r27, r30, (Address::ScaleFactor)1, -0x197f1266), r28, false);", // IID573 + "__ eorq(r9, Address(r29, r30, (Address::ScaleFactor)0, -0x24ea9b08), r11, true);", // IID574 + "__ esubq(r15, Address(r14, -0x4f44bf90), r16, false);", // IID575 + "__ esubq(rcx, Address(r21, r18, (Address::ScaleFactor)1, -0x11d0ac8f), r28, true);", // IID576 + "__ exorq(r19, Address(r19, r18, (Address::ScaleFactor)0, -0xa5e55ec), r8, false);", // IID577 + "__ exorq(r28, Address(r17, r28, (Address::ScaleFactor)1, -0x6eb42fe0), r16, true);", // IID578 + "__ eaddq(r17, Address(r18, -0x60ab1105), 16777216, false);", // IID579 + "__ eaddq(r25, Address(r19, r25, (Address::ScaleFactor)0, +0x122444d9), 65536, true);", // IID580 + "__ eandq(r30, Address(r9, r28, (Address::ScaleFactor)1, -0x25b00cf3), 4096, false);", // IID581 + "__ eandq(r9, Address(r22, rbx, (Address::ScaleFactor)1, -0x7e465026), 268435456, true);", // IID582 + "__ eimulq(r12, Address(r25, r25, (Address::ScaleFactor)1, -0x432d68cc), 1, false);", // IID583 + "__ eimulq(r15, Address(r17, r31, (Address::ScaleFactor)3, -0x2b97565e), 16, true);", // IID584 + "__ eorq(r28, Address(rdx, r31, (Address::ScaleFactor)0, +0x3f1363b1), 256, false);", // IID585 + "__ eorq(r16, Address(r12, r23, (Address::ScaleFactor)3, -0x1785863c), 16777216, true);", // IID586 + "__ esalq(r8, Address(r14, r24, (Address::ScaleFactor)2, -0x714290a5), 2, false);", // IID587 + "__ esalq(r8, Address(r15, r14, (Address::ScaleFactor)2, +0x21f13243), 16, true);", // IID588 + "__ esarq(r10, Address(r13, r29, (Address::ScaleFactor)0, +0x7d04cb72), 2, false);", // IID589 + "__ esarq(r11, Address(r21, r31, (Address::ScaleFactor)3, -0x2176b4dc), 8, true);", // IID590 + "__ eshrq(rcx, Address(r16, r12, (Address::ScaleFactor)1, +0x260c9a38), 4, false);", // IID591 + "__ eshrq(r22, Address(r26, r9, (Address::ScaleFactor)0, -0x5e56bb62), 8, true);", // IID592 + "__ esubq(r31, Address(rbx, r28, (Address::ScaleFactor)1, +0x2b00bb10), 1, false);", // IID593 + "__ esubq(r21, Address(r31, -0x6c10f4ad), 4096, true);", // IID594 + "__ exorq(r11, Address(r23, r30, (Address::ScaleFactor)1, +0x51a6026b), 65536, false);", // IID595 + "__ exorq(r14, Address(r27, r10, (Address::ScaleFactor)2, -0x34ad9bab), 16, true);", // IID596 + "__ eaddq(r20, r23, 16777216, false);", // IID597 + "__ eaddq(rax, r30, 16777216, false);", // IID598 + "__ eaddq(r9, r21, 4096, true);", // IID599 + "__ eaddq(rax, rbx, 4096, true);", // IID600 + "__ eandq(rdx, r21, 268435456, false);", // IID601 + "__ eandq(rax, r8, 268435456, false);", // IID602 + "__ eandq(r19, r31, 65536, true);", // IID603 + "__ eandq(rax, rbx, 65536, true);", // IID604 + "__ eimulq(r21, r9, 16777216, false);", // IID605 + "__ eimulq(rax, r30, 16777216, false);", // IID606 + "__ eimulq(r30, r18, 65536, true);", // IID607 + "__ eimulq(rax, r19, 65536, true);", // IID608 + "__ eorq(r20, r16, 1048576, false);", // IID609 + "__ eorq(rax, r28, 1048576, false);", // IID610 + "__ eorq(rbx, r24, 4096, true);", // IID611 + "__ eorq(rax, r22, 4096, true);", // IID612 + "__ erclq(r20, r30, 4);", // IID613 + "__ erclq(rax, r22, 4);", // IID614 + "__ erolq(rcx, r28, 2, false);", // IID615 + "__ erolq(rax, r21, 2, false);", // IID616 + "__ erolq(r26, r15, 4, true);", // IID617 + "__ erolq(rax, r19, 4, true);", // IID618 + "__ erorq(r24, r19, 8, false);", // IID619 + "__ erorq(rax, r28, 8, false);", // IID620 + "__ erorq(r25, r18, 4, true);", // IID621 + "__ erorq(rax, r13, 4, true);", // IID622 + "__ esalq(r27, r17, 2, false);", // IID623 + "__ esalq(rax, rdx, 2, false);", // IID624 + "__ esalq(rbx, r28, 16, true);", // IID625 + "__ esalq(rax, r15, 16, true);", // IID626 + "__ esarq(rbx, r12, 4, false);", // IID627 + "__ esarq(rax, rbx, 4, false);", // IID628 + "__ esarq(r17, rdx, 2, true);", // IID629 + "__ esarq(rax, r31, 2, true);", // IID630 + "__ eshlq(r21, rbx, 4, false);", // IID631 + "__ eshlq(rax, r24, 4, false);", // IID632 + "__ eshlq(r27, r13, 16, true);", // IID633 + "__ eshlq(rax, r25, 16, true);", // IID634 + "__ eshrq(rcx, r22, 16, false);", // IID635 + "__ eshrq(rax, r14, 16, false);", // IID636 + "__ eshrq(r11, r30, 4, true);", // IID637 + "__ eshrq(rax, r24, 4, true);", // IID638 + "__ esubq(r20, r19, 256, false);", // IID639 + "__ esubq(rax, r17, 256, false);", // IID640 + "__ esubq(r31, r30, 65536, true);", // IID641 + "__ esubq(rax, r18, 65536, true);", // IID642 + "__ exorq(r18, r11, 4096, false);", // IID643 + "__ exorq(rax, r10, 4096, false);", // IID644 + "__ exorq(r24, r18, 268435456, true);", // IID645 + "__ exorq(rax, rbx, 268435456, true);", // IID646 + "__ eorq_imm32(r26, r21, 4194304, false);", // IID647 + "__ eorq_imm32(rax, r8, 4194304, false);", // IID648 + "__ eorq_imm32(r22, r21, 262144, false);", // IID649 + "__ eorq_imm32(rax, r27, 262144, false);", // IID650 + "__ esubq_imm32(r16, r8, 4194304, false);", // IID651 + "__ esubq_imm32(rax, rdx, 4194304, false);", // IID652 + "__ esubq_imm32(r20, r31, 1048576, true);", // IID653 + "__ esubq_imm32(rax, r21, 1048576, true);", // IID654 + "__ eaddq(r20, r14, Address(rcx, r16, (Address::ScaleFactor)0, +0x7c6654d9), false);", // IID655 + "__ eaddq(r29, rcx, Address(r15, r23, (Address::ScaleFactor)0, +0x45b7f72d), true);", // IID656 + "__ eandq(r19, r17, Address(r13, r22, (Address::ScaleFactor)1, -0x750c1996), false);", // IID657 + "__ eandq(r13, r8, Address(r31, r23, (Address::ScaleFactor)1, -0x2211b6b2), true);", // IID658 + "__ eorq(r11, r28, Address(r13, r11, (Address::ScaleFactor)3, +0x5c0013ab), false);", // IID659 + "__ eorq(rdx, r18, Address(r18, rcx, (Address::ScaleFactor)0, +0x59557e71), true);", // IID660 + "__ eimulq(r27, r11, Address(r22, -0x28469649), false);", // IID661 + "__ eimulq(r10, r9, Address(r24, +0x49691d54), true);", // IID662 + "__ esubq(r24, r12, Address(r19, +0x22d529aa), false);", // IID663 + "__ esubq(r20, r18, Address(r9, r10, (Address::ScaleFactor)2, -0x264a7a48), true);", // IID664 + "__ exorq(rbx, r9, Address(r14, r27, (Address::ScaleFactor)0, +0xf71c02f), false);", // IID665 + "__ exorq(r25, r15, Address(r10, r12, (Address::ScaleFactor)1, +0x732367bd), true);", // IID666 + "__ eaddq(r11, r9, r10, false);", // IID667 + "__ eaddq(r25, r13, r16, true);", // IID668 + "__ eadcxq(r11, r21, r25);", // IID669 + "__ eadoxq(rdx, r20, rbx);", // IID670 + "__ eandq(r25, r21, r26, false);", // IID671 + "__ eandq(r23, r27, r21, true);", // IID672 + "__ eimulq(r10, r10, r12, false);", // IID673 + "__ eimulq(r31, r12, r23, true);", // IID674 + "__ eorq(r16, r29, r14, false);", // IID675 + "__ eorq(r19, r24, r23, true);", // IID676 + "__ esubq(r14, r21, r15, false);", // IID677 + "__ esubq(r25, r9, r29, true);", // IID678 + "__ exorq(rdx, r11, r25, false);", // IID679 + "__ exorq(r19, r10, r16, true);", // IID680 + "__ eshldq(r8, r23, r31, 8, false);", // IID681 + "__ eshldq(r31, rbx, r16, 2, true);", // IID682 + "__ eshrdq(r24, r10, r9, 2, false);", // IID683 + "__ eshrdq(r28, r26, r18, 16, true);", // IID684 + "__ ecmovq (Assembler::Condition::overflow, r25, r20, r16);", // IID685 + "__ ecmovq (Assembler::Condition::noOverflow, r21, rbx, r28);", // IID686 + "__ ecmovq (Assembler::Condition::below, r22, r19, r13);", // IID687 + "__ ecmovq (Assembler::Condition::aboveEqual, r15, rdx, r8);", // IID688 + "__ ecmovq (Assembler::Condition::zero, r22, r14, r12);", // IID689 + "__ ecmovq (Assembler::Condition::notZero, r24, r14, r24);", // IID690 + "__ ecmovq (Assembler::Condition::belowEqual, r13, r21, rbx);", // IID691 + "__ ecmovq (Assembler::Condition::above, rbx, r27, r14);", // IID692 + "__ ecmovq (Assembler::Condition::negative, r24, r27, r17);", // IID693 + "__ ecmovq (Assembler::Condition::positive, r21, r27, r27);", // IID694 + "__ ecmovq (Assembler::Condition::parity, r27, r14, r24);", // IID695 + "__ ecmovq (Assembler::Condition::noParity, r28, r29, r22);", // IID696 + "__ ecmovq (Assembler::Condition::less, r15, r13, r31);", // IID697 + "__ ecmovq (Assembler::Condition::greaterEqual, r21, r15, r30);", // IID698 + "__ ecmovq (Assembler::Condition::lessEqual, r20, r8, r13);", // IID699 + "__ ecmovq (Assembler::Condition::greater, r31, r25, r27);", // IID700 + "__ ecmovq (Assembler::Condition::overflow, r31, r15, Address(r14, r13, (Address::ScaleFactor)1, -0x6e68556));", // IID701 + "__ ecmovq (Assembler::Condition::noOverflow, r12, r28, Address(r30, r15, (Address::ScaleFactor)3, +0x3ba33f9e));", // IID702 + "__ ecmovq (Assembler::Condition::below, r16, r25, Address(r12, r9, (Address::ScaleFactor)0, -0x28e03b33));", // IID703 + "__ ecmovq (Assembler::Condition::aboveEqual, r8, r27, Address(r8, r25, (Address::ScaleFactor)3, -0x1e42bd95));", // IID704 + "__ ecmovq (Assembler::Condition::zero, rcx, r20, Address(r27, rbx, (Address::ScaleFactor)2, +0x46823c58));", // IID705 + "__ ecmovq (Assembler::Condition::notZero, rbx, r12, Address(r21, -0x635b8c8));", // IID706 + "__ ecmovq (Assembler::Condition::belowEqual, r23, rbx, Address(r27, r26, (Address::ScaleFactor)3, +0x922bcc0));", // IID707 + "__ ecmovq (Assembler::Condition::above, r25, r9, Address(r23, +0xd2a14ec));", // IID708 + "__ ecmovq (Assembler::Condition::negative, r11, r19, Address(r11, -0xfb95a9d));", // IID709 + "__ ecmovq (Assembler::Condition::positive, r13, r18, Address(r28, r19, (Address::ScaleFactor)0, +0x716b9b7e));", // IID710 + "__ ecmovq (Assembler::Condition::parity, r21, r16, Address(rcx, r29, (Address::ScaleFactor)0, -0x5af0441e));", // IID711 + "__ ecmovq (Assembler::Condition::noParity, r12, r31, Address(r20, r26, (Address::ScaleFactor)0, +0xe0b7fb1));", // IID712 + "__ ecmovq (Assembler::Condition::less, r15, r24, Address(r30, +0x2d3b7b4f));", // IID713 + "__ ecmovq (Assembler::Condition::greaterEqual, r12, r15, Address(r14, r21, (Address::ScaleFactor)2, -0x1222aee8));", // IID714 + "__ ecmovq (Assembler::Condition::lessEqual, rbx, r31, Address(r23, r20, (Address::ScaleFactor)0, -0x96e4d6a));", // IID715 + "__ ecmovq (Assembler::Condition::greater, rdx, rdx, Address(r10, rdx, (Address::ScaleFactor)3, +0x3875f17c));", // IID716 #endif // _LP64 }; // END Generated code -- do not edit diff --git a/test/hotspot/gtest/x86/x86-asmtest.py b/test/hotspot/gtest/x86/x86-asmtest.py index 318bc50f6ef..51932988fb2 100644 --- a/test/hotspot/gtest/x86/x86-asmtest.py +++ b/test/hotspot/gtest/x86/x86-asmtest.py @@ -1,4 +1,4 @@ -# Copyright (c) 2024, Oracle and/or its affiliates. All rights reserved. +# Copyright (c) 2024, 2025, Oracle and/or its affiliates. All rights reserved. # DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. # # This code is free software; you can redistribute it and/or modify it @@ -57,7 +57,7 @@ shift_rot_ops = {'sarl', 'sarq', 'sall', 'salq', 'shll', 'shlq', 'shrl', 'shrq', registers_mapping = { # skip rax, rsi, rdi, rsp, rbp as they have special encodings - # 'rax': {64: 'rax', 32: 'eax', 16: 'ax', 8: 'al'}, + 'rax': {64: 'rax', 32: 'eax', 16: 'ax', 8: 'al'}, 'rcx': {64: 'rcx', 32: 'ecx', 16: 'cx', 8: 'cl'}, 'rdx': {64: 'rdx', 32: 'edx', 16: 'dx', 8: 'dl'}, 'rbx': {64: 'rbx', 32: 'ebx', 16: 'bx', 8: 'bl'}, @@ -415,7 +415,7 @@ class RegRegRegImmNddInstruction(NFInstruction): self.imm = Immediate().generate(imm) self.generate_operands(self.reg1, self.reg2, self.reg3, self.imm) -test_regs = list(registers_mapping.keys()) +test_regs = [key for key in registers_mapping.keys() if key != 'rax'] immediates32 = [2 ** i for i in range(0, 32, 4)] immediates16 = [2 ** i for i in range(0, 16, 2)] @@ -624,6 +624,14 @@ def generate(RegOp, ops, print_lp64_flag=True, full_set=False): instr = RegOp(*op, reg1=test_reg1, reg2=test_reg2, imm=imm) print_instruction(instr, lp64_flag, print_lp64_flag) + # additional tests with rax as destination + if RegOp in [RegRegImmNddInstruction]: + test_reg1 = 'rax' + test_reg2 = random.choice(test_regs) + lp64_flag = handle_lp64_flag(lp64_flag, print_lp64_flag, test_reg1, test_reg2) + instr = RegOp(*op, reg1=test_reg1, reg2=test_reg2, imm=imm) + print_instruction(instr, lp64_flag, print_lp64_flag) + elif RegOp in [RegMemImmInstruction, RegMemImmNddInstruction]: if full_set: imm_list = get_immediate_list(op_name, width) @@ -1466,4 +1474,4 @@ if __name__ == "__main__": print("// END Generated code -- do not edit") for f in ["x86ops.s", "x86ops.o", "x86ops.bin"]: - os.remove(f) \ No newline at end of file + os.remove(f)