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8382315: RISC-V: TestMultiplyReductionByte.java fails with guarantee(is_uimm5(imm)) failed: uimm is invalid

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Reviewed-by: fyang, gcao
This commit is contained in:
Dingli Zhang 2026-04-20 06:33:17 +00:00
parent 444e6f6366
commit da0a7b1eec
3 changed files with 36 additions and 26 deletions
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42
src/hotspot/cpu/riscv/c2_MacroAssembler_riscv.cpp
View File

@ -3069,12 +3069,12 @@ void C2_MacroAssembler::reduce_mul_integral_v(Register dst, Register src1, Vecto
// If the operation is MUL, then the identity value is one.
vmv_v_i(vtmp1, 1);
vmerge_vvm(vtmp2, vtmp1, src2); // vm == v0
vslidedown_vi(vtmp1, vtmp2, vector_length);
slidedown_v(vtmp1, vtmp2, vector_length);
vsetvli_helper(bt, vector_length);
vmul_vv(vtmp1, vtmp1, vtmp2);
} else {
vslidedown_vi(vtmp1, src2, vector_length);
slidedown_v(vtmp1, src2, vector_length);
vsetvli_helper(bt, vector_length);
vmul_vv(vtmp1, vtmp1, src2);
@ -3082,7 +3082,7 @@ void C2_MacroAssembler::reduce_mul_integral_v(Register dst, Register src1, Vecto
while (vector_length > 1) {
vector_length /= 2;
vslidedown_vi(vtmp2, vtmp1, vector_length);
slidedown_v(vtmp2, vtmp1, vector_length);
vsetvli_helper(bt, vector_length);
vmul_vv(vtmp1, vtmp1, vtmp2);
}
@ -3281,40 +3281,44 @@ VFCVT_SAFE(vfcvt_rtz_x_f_v);
// Extract a scalar element from an vector at position 'idx'.
// The input elements in src are expected to be of integral type.
void C2_MacroAssembler::extract_v(Register dst, VectorRegister src, BasicType bt,
int idx, VectorRegister tmp) {
void C2_MacroAssembler::extract_v(Register dst, VectorRegister src,
BasicType bt, int idx, VectorRegister vtmp) {
assert(is_integral_type(bt), "unsupported element type");
assert(idx >= 0, "idx cannot be negative");
// Only need the first element after vector slidedown
vsetvli_helper(bt, 1);
if (idx == 0) {
vmv_x_s(dst, src);
} else if (idx <= 31) {
vslidedown_vi(tmp, src, idx);
vmv_x_s(dst, tmp);
} else {
mv(t0, idx);
vslidedown_vx(tmp, src, t0);
vmv_x_s(dst, tmp);
slidedown_v(vtmp, src, idx);
vmv_x_s(dst, vtmp);
}
}
// Extract a scalar element from an vector at position 'idx'.
// The input elements in src are expected to be of floating point type.
void C2_MacroAssembler::extract_fp_v(FloatRegister dst, VectorRegister src, BasicType bt,
int idx, VectorRegister tmp) {
void C2_MacroAssembler::extract_fp_v(FloatRegister dst, VectorRegister src,
BasicType bt, int idx, VectorRegister vtmp) {
assert(is_floating_point_type(bt), "unsupported element type");
assert(idx >= 0, "idx cannot be negative");
// Only need the first element after vector slidedown
vsetvli_helper(bt, 1);
if (idx == 0) {
vfmv_f_s(dst, src);
} else if (idx <= 31) {
vslidedown_vi(tmp, src, idx);
vfmv_f_s(dst, tmp);
} else {
mv(t0, idx);
vslidedown_vx(tmp, src, t0);
vfmv_f_s(dst, tmp);
slidedown_v(vtmp, src, idx);
vfmv_f_s(dst, vtmp);
}
}
// Move elements down a vector register group.
// Offset is the start index (offset) for the source.
void C2_MacroAssembler::slidedown_v(VectorRegister dst, VectorRegister src,
uint32_t offset, Register tmp) {
if (is_uimm5(offset)) {
vslidedown_vi(dst, src, offset);
} else {
mv(tmp, offset);
vslidedown_vx(dst, src, tmp);
}
}

12
src/hotspot/cpu/riscv/c2_MacroAssembler_riscv.hpp
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2020, 2025, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2020, 2026, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2020, 2022, Huawei Technologies Co., Ltd. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
@ -296,7 +296,13 @@
void vfcvt_rtz_x_f_v_safe(VectorRegister dst, VectorRegister src);
void extract_v(Register dst, VectorRegister src, BasicType bt, int idx, VectorRegister tmp);
void extract_fp_v(FloatRegister dst, VectorRegister src, BasicType bt, int idx, VectorRegister tmp);
void extract_v(Register dst, VectorRegister src,
BasicType bt, int idx, VectorRegister vtmp);
void extract_fp_v(FloatRegister dst, VectorRegister src,
BasicType bt, int idx, VectorRegister vtmp);
void slidedown_v(VectorRegister dst, VectorRegister src,
uint32_t offset, Register tmp = t0);
#endif // CPU_RISCV_C2_MACROASSEMBLER_RISCV_HPP

8
test/hotspot/jtreg/compiler/vectorapi/TestMultiplyReductionByte.java
View File

@ -57,7 +57,7 @@ public class TestMultiplyReductionByte {
@Test
@IR(counts = {IRNode.MUL_REDUCTION_VI, ">=1"},
applyIfCPUFeatureOr = {"avx", "true", "asimd", "true"},
applyIfCPUFeatureOr = {"avx", "true", "asimd", "true", "rvv", "true"},
applyIf = {"MaxVectorSize", ">=8"})
static byte testMulReduce64() {
return ByteVector.fromArray(ByteVector.SPECIES_64, input, 0)
@ -75,7 +75,7 @@ public class TestMultiplyReductionByte {
@Test
@IR(counts = {IRNode.MUL_REDUCTION_VI, ">=1"},
applyIfCPUFeatureOr = {"avx", "true", "asimd", "true"},
applyIfCPUFeatureOr = {"avx", "true", "asimd", "true", "rvv", "true"},
applyIf = {"MaxVectorSize", ">=16"})
static byte testMulReduce128() {
return ByteVector.fromArray(ByteVector.SPECIES_128, input, 0)
@ -93,7 +93,7 @@ public class TestMultiplyReductionByte {
@Test
@IR(counts = {IRNode.MUL_REDUCTION_VI, ">=1"},
applyIfCPUFeatureOr = {"avx2", "true", "asimd", "true"},
applyIfCPUFeatureOr = {"avx2", "true", "asimd", "true", "rvv", "true"},
applyIf = {"MaxVectorSize", ">=32"})
static byte testMulReduce256() {
return ByteVector.fromArray(ByteVector.SPECIES_256, input, 0)
@ -111,7 +111,7 @@ public class TestMultiplyReductionByte {
@Test
@IR(counts = {IRNode.MUL_REDUCTION_VI, ">=1"},
applyIfCPUFeatureOr = {"avx512f", "true", "asimd", "true"},
applyIfCPUFeatureOr = {"avx512f", "true", "asimd", "true", "rvv", "true"},
applyIf = {"MaxVectorSize", ">=64"})
static byte testMulReduce512() {
return ByteVector.fromArray(ByteVector.SPECIES_512, input, 0)