From dc80ce7aec8e466a29fd4c94ee70c90a7244869f Mon Sep 17 00:00:00 2001 From: ikarostsin Date: Mon, 9 Feb 2026 07:41:20 +0000 Subject: [PATCH] 8374056: RISC-V: Fix argument passing for the RiscvFlushIcache::flush Reviewed-by: fyang, rehn --- src/hotspot/cpu/riscv/icache_riscv.cpp | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/hotspot/cpu/riscv/icache_riscv.cpp b/src/hotspot/cpu/riscv/icache_riscv.cpp index 258bc665770..20de2dbb2ad 100644 --- a/src/hotspot/cpu/riscv/icache_riscv.cpp +++ b/src/hotspot/cpu/riscv/icache_riscv.cpp @@ -39,7 +39,8 @@ static int icache_flush(address addr, int lines, int magic) { // We need to make sure stores happens before the I/D cache synchronization. __asm__ volatile("fence rw, rw" : : : "memory"); - RiscvFlushIcache::flush((uintptr_t)addr, ((uintptr_t)lines) << ICache::log2_line_size); + uintptr_t end = (uintptr_t)addr + ((uintptr_t)lines << ICache::log2_line_size); + RiscvFlushIcache::flush((uintptr_t)addr, end); return magic; }