From e9f7db304559cbc8e2b46ea30496d3c570569f4c Mon Sep 17 00:00:00 2001 From: Kim Barrett Date: Tue, 9 Jan 2024 22:26:17 +0000 Subject: [PATCH] 8322880: Eliminate -Wparentheses warnings in arm32 code Reviewed-by: shade, dholmes --- src/hotspot/cpu/arm/arm.ad | 4 ++-- src/hotspot/cpu/arm/assembler_arm.hpp | 4 ++-- src/hotspot/cpu/arm/c1_LIRAssembler_arm.cpp | 6 +++--- src/hotspot/cpu/arm/frame_arm.inline.hpp | 4 ++-- src/hotspot/cpu/arm/nativeInst_arm_32.cpp | 4 ++-- src/hotspot/cpu/arm/nativeInst_arm_32.hpp | 4 ++-- 6 files changed, 13 insertions(+), 13 deletions(-) diff --git a/src/hotspot/cpu/arm/arm.ad b/src/hotspot/cpu/arm/arm.ad index c4197235987..e31ad91613a 100644 --- a/src/hotspot/cpu/arm/arm.ad +++ b/src/hotspot/cpu/arm/arm.ad @@ -1,5 +1,5 @@ // -// Copyright (c) 2008, 2023, Oracle and/or its affiliates. All rights reserved. +// Copyright (c) 2008, 2024, Oracle and/or its affiliates. All rights reserved. // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. // // This code is free software; you can redistribute it and/or modify it @@ -9193,7 +9193,7 @@ instruct clear_array(iRegX cnt, iRegP base, iRegI temp, iRegX zero, Universe dum ins_encode %{ __ mov($zero$$Register, 0); __ mov($temp$$Register, $cnt$$Register); - Label(loop); + Label loop; __ bind(loop); __ subs($temp$$Register, $temp$$Register, 4); __ str($zero$$Register, Address($base$$Register, $temp$$Register), ge); diff --git a/src/hotspot/cpu/arm/assembler_arm.hpp b/src/hotspot/cpu/arm/assembler_arm.hpp index b1b4199e88d..6a3092f7b3b 100644 --- a/src/hotspot/cpu/arm/assembler_arm.hpp +++ b/src/hotspot/cpu/arm/assembler_arm.hpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2008, 2023, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 2008, 2024, Oracle and/or its affiliates. All rights reserved. * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. * * This code is free software; you can redistribute it and/or modify it @@ -175,7 +175,7 @@ class Address { if (_index == noreg) { assert(-256 < _disp && _disp < 256, "encoding constraint"); return _mode | up(_disp) << 23 | 1 << 22 | _base->encoding() << 16 | - (abs(_disp) & 0xf0) << 4 | abs(_disp) & 0x0f; + (abs(_disp) & 0xf0) << 4 | (abs(_disp) & 0x0f); } else { assert(_index != PC && (_mode == basic_offset || _index != _base), "unpredictable instruction"); assert(_disp == 0 && _shift == lsl && _shift_imm == 0, "encoding constraint"); diff --git a/src/hotspot/cpu/arm/c1_LIRAssembler_arm.cpp b/src/hotspot/cpu/arm/c1_LIRAssembler_arm.cpp index 72993b3211f..999309c0225 100644 --- a/src/hotspot/cpu/arm/c1_LIRAssembler_arm.cpp +++ b/src/hotspot/cpu/arm/c1_LIRAssembler_arm.cpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2008, 2023, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 2008, 2024, Oracle and/or its affiliates. All rights reserved. * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. * * This code is free software; you can redistribute it and/or modify it @@ -2640,8 +2640,8 @@ void LIR_Assembler::rt_call(LIR_Opr result, address dest, const LIR_OprList* arg void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) { - assert(src->is_double_cpu() && dest->is_address() || - src->is_address() && dest->is_double_cpu(), + assert((src->is_double_cpu() && dest->is_address()) || + (src->is_address() && dest->is_double_cpu()), "Simple move_op is called for all other cases"); int null_check_offset; diff --git a/src/hotspot/cpu/arm/frame_arm.inline.hpp b/src/hotspot/cpu/arm/frame_arm.inline.hpp index 9191d03baf0..43cc523658b 100644 --- a/src/hotspot/cpu/arm/frame_arm.inline.hpp +++ b/src/hotspot/cpu/arm/frame_arm.inline.hpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2008, 2023, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 2008, 2024, Oracle and/or its affiliates. All rights reserved. * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. * * This code is free software; you can redistribute it and/or modify it @@ -93,7 +93,7 @@ inline bool frame::equal(frame other) const { && unextended_sp() == other.unextended_sp() && fp() == other.fp() && pc() == other.pc(); - assert(!ret || ret && cb() == other.cb() && _deopt_state == other._deopt_state, "inconsistent construction"); + assert(!ret || (cb() == other.cb() && _deopt_state == other._deopt_state), "inconsistent construction"); return ret; } diff --git a/src/hotspot/cpu/arm/nativeInst_arm_32.cpp b/src/hotspot/cpu/arm/nativeInst_arm_32.cpp index e5e5e89c200..429a0c000f6 100644 --- a/src/hotspot/cpu/arm/nativeInst_arm_32.cpp +++ b/src/hotspot/cpu/arm/nativeInst_arm_32.cpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2008, 2023, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 2008, 2024, Oracle and/or its affiliates. All rights reserved. * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. * * This code is free software; you can redistribute it and/or modify it @@ -162,7 +162,7 @@ void NativeMovConstReg::set_data(intptr_t x, address pc) { unsigned int hi = (unsigned int)(x >> 16); this->set_encoding((this->encoding() & 0xfff0f000) | (lo & 0xf000) << 4 | (lo & 0xfff)); next->set_encoding((next->encoding() & 0xfff0f000) | (hi & 0xf000) << 4 | (hi & 0xfff)); - } else if (oop_addr == nullptr & metadata_addr == nullptr) { + } else if (oop_addr == nullptr && metadata_addr == nullptr) { // A static ldr_literal (without oop or metadata relocation) assert(is_ldr_literal(), "must be"); int offset = ldr_offset(); diff --git a/src/hotspot/cpu/arm/nativeInst_arm_32.hpp b/src/hotspot/cpu/arm/nativeInst_arm_32.hpp index 804292c24b0..a7a51f017d2 100644 --- a/src/hotspot/cpu/arm/nativeInst_arm_32.hpp +++ b/src/hotspot/cpu/arm/nativeInst_arm_32.hpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2008, 2023, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 2008, 2024, Oracle and/or its affiliates. All rights reserved. * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. * * This code is free software; you can redistribute it and/or modify it @@ -396,7 +396,7 @@ class NativeMovConstReg: public NativeInstruction { inline NativeMovConstReg* nativeMovConstReg_at(address address) { NativeInstruction* ni = nativeInstruction_at(address); assert(ni->is_ldr_literal() || ni->is_pc_rel() || - ni->is_movw() && VM_Version::supports_movw(), "must be"); + (ni->is_movw() && VM_Version::supports_movw()), "must be"); return (NativeMovConstReg*)address; }