diff --git a/test/hotspot/jtreg/compiler/vectorapi/TestVectorMulLongToSignedUnsignedInt.java b/test/hotspot/jtreg/compiler/vectorapi/TestVectorMulLongToSignedUnsignedInt.java
index e7745b5e88c..cb58cfca652 100644
--- a/test/hotspot/jtreg/compiler/vectorapi/TestVectorMulLongToSignedUnsignedInt.java
+++ b/test/hotspot/jtreg/compiler/vectorapi/TestVectorMulLongToSignedUnsignedInt.java
@@ -89,7 +89,7 @@ public class TestVectorMulLongToSignedUnsignedInt {
     @Test
     @IR(counts = {IRNode.AND_VL, " >0 ",
                   IRNode.MUL_VL, " >0 "},
-        applyIfCPUFeatureOr = {"avx", "true", "asimd", "true"})
+        applyIfCPUFeatureOr = {"avx", "true", "asimd", "true", "rvv", "true"})
     @IR(failOn = {IRNode.X86_VMULUDQ_REG},
         phase = CompilePhase.MATCHING,
         applyIfCPUFeature = {"avx", "true"})
@@ -119,7 +119,7 @@ public class TestVectorMulLongToSignedUnsignedInt {
     @Test
     @IR(counts = {IRNode.AND_VL, " >0 ",
                   IRNode.MUL_VL, " >0 "},
-        applyIfCPUFeatureOr = {"avx", "true", "asimd", "true"})
+        applyIfCPUFeatureOr = {"avx", "true", "asimd", "true", "rvv", "true"})
     @IR(failOn = {IRNode.X86_VMULUDQ_REG},
         phase = CompilePhase.MATCHING,
         applyIfCPUFeature = {"avx", "true"})
@@ -147,7 +147,7 @@ public class TestVectorMulLongToSignedUnsignedInt {
     @Test
     @IR(counts = {IRNode.AND_VL, " >0 ",
                   IRNode.MUL_VL, " >0 "},
-        applyIfCPUFeatureOr = {"avx", "true", "asimd", "true"})
+        applyIfCPUFeatureOr = {"avx", "true", "asimd", "true", "rvv", "true"})
     @IR(failOn = {IRNode.X86_VMULUDQ_REG},
         phase = CompilePhase.MATCHING,
         applyIfCPUFeature = {"avx", "true"})
@@ -176,7 +176,7 @@ public class TestVectorMulLongToSignedUnsignedInt {
     // Case 5: Mask = 0xFFFF_FFFFL (exactly uint max, boundary valid case).
     @Test
     @IR(counts = {IRNode.MUL_VL, " >0 "},
-        applyIfCPUFeatureOr = {"avx", "true", "asimd", "true"})
+        applyIfCPUFeatureOr = {"avx", "true", "asimd", "true", "rvv", "true"})
     @IR(counts = {IRNode.X86_VMULUDQ_REG, " >0 "},
         phase = CompilePhase.MATCHING,
         applyIfCPUFeature = {"avx", "true"})
@@ -205,7 +205,7 @@ public class TestVectorMulLongToSignedUnsignedInt {
     // Case 6: Small mask (0xFFFFL), clearly fits in uint.
     @Test
     @IR(counts = {IRNode.MUL_VL, " >0 "},
-        applyIfCPUFeatureOr = {"avx", "true", "asimd", "true"})
+        applyIfCPUFeatureOr = {"avx", "true", "asimd", "true", "rvv", "true"})
     @IR(counts = {IRNode.X86_VMULUDQ_REG, " >0 "},
         phase = CompilePhase.MATCHING,
         applyIfCPUFeature = {"avx", "true"})
@@ -235,7 +235,7 @@ public class TestVectorMulLongToSignedUnsignedInt {
     @Test
     @IR(counts = {IRNode.MUL_VL, " >0 ",
                   IRNode.URSHIFT_VL, " >0 "},
-        applyIfCPUFeatureOr = {"avx", "true", "asimd", "true"})
+        applyIfCPUFeatureOr = {"avx", "true", "asimd", "true", "rvv", "true"})
     @IR(counts = {IRNode.X86_VMULUDQ_REG, " >0 "},
         phase = CompilePhase.MATCHING,
         applyIfCPUFeature = {"avx", "true"})
@@ -265,7 +265,7 @@ public class TestVectorMulLongToSignedUnsignedInt {
     @Test
     @IR(counts = {IRNode.AND_VL, " >0 ",
                   IRNode.MUL_VL, " >0 "},
-        applyIfCPUFeatureOr = {"avx", "true", "asimd", "true"})
+        applyIfCPUFeatureOr = {"avx", "true", "asimd", "true", "rvv", "true"})
     @IR(failOn = {IRNode.X86_VMULUDQ_REG},
         phase = CompilePhase.MATCHING,
         applyIfCPUFeature = {"avx", "true"})
@@ -297,7 +297,7 @@ public class TestVectorMulLongToSignedUnsignedInt {
     @IR(counts = {IRNode.URSHIFT_VL, " >0 ",
                   IRNode.AND_VL, " >0 ",
                   IRNode.MUL_VL, " >0 "},
-        applyIfCPUFeatureOr = {"avx", "true", "asimd", "true"})
+        applyIfCPUFeatureOr = {"avx", "true", "asimd", "true", "rvv", "true"})
     @IR(failOn = {IRNode.X86_VMULUDQ_REG},
         phase = CompilePhase.MATCHING,
         applyIfCPUFeature = {"avx", "true"})
@@ -327,7 +327,7 @@ public class TestVectorMulLongToSignedUnsignedInt {
     @Test
     @IR(counts = {IRNode.AND_VL, " >0 ",
                   IRNode.MUL_VL, " >0 "},
-        applyIfCPUFeatureOr = {"avx512f", "true", "sve", "true"})
+        applyIfCPUFeatureOr = {"avx512f", "true", "sve", "true", "rvv", "true"})
     @IR(failOn = {IRNode.X86_VMULUDQ_REG},
         phase = CompilePhase.MATCHING,
         applyIfCPUFeature = {"avx512f", "true"})
@@ -359,7 +359,7 @@ public class TestVectorMulLongToSignedUnsignedInt {
     @Test
     @IR(counts = {IRNode.URSHIFT_VL, " >0 ",
                   IRNode.MUL_VL, " >0 "},
-        applyIfCPUFeatureOr = {"avx512f", "true", "sve", "true"})
+        applyIfCPUFeatureOr = {"avx512f", "true", "sve", "true", "rvv", "true"})
     @IR(failOn = {IRNode.X86_VMULUDQ_REG},
         phase = CompilePhase.MATCHING,
         applyIfCPUFeature = {"avx512f", "true"})
@@ -391,7 +391,7 @@ public class TestVectorMulLongToSignedUnsignedInt {
     @Test
     @IR(counts = {IRNode.RSHIFT_VL, " >0 ",
                   IRNode.MUL_VL, " >0 "},
-        applyIfCPUFeatureOr = {"avx512f", "true", "sve", "true"})
+        applyIfCPUFeatureOr = {"avx512f", "true", "sve", "true", "rvv", "true"})
     @IR(failOn = {IRNode.X86_VMULDQ_REG},
         phase = CompilePhase.MATCHING,
         applyIfCPUFeature = {"avx512f", "true"})
diff --git a/test/hotspot/jtreg/compiler/vectorapi/VectorMultiplyOpt.java b/test/hotspot/jtreg/compiler/vectorapi/VectorMultiplyOpt.java
index 68ac9249ebf..4d8344e729e 100644
--- a/test/hotspot/jtreg/compiler/vectorapi/VectorMultiplyOpt.java
+++ b/test/hotspot/jtreg/compiler/vectorapi/VectorMultiplyOpt.java
@@ -107,7 +107,8 @@ public class VectorMultiplyOpt {
     }
 
     @Test
-    @IR(counts = {IRNode.MUL_VL, " >0 ", IRNode.AND_VL, " >0 "}, applyIfCPUFeature = {"avx", "true"})
+    @IR(counts = {IRNode.MUL_VL, " >0 ", IRNode.AND_VL, " >0 "},
+        applyIfCPUFeatureOr = {"avx", "true", "rvv", "true"})
     @IR(counts = {"vmuludq", " >0 "}, phase = CompilePhase.FINAL_CODE, applyIfCPUFeature = {"avx", "true"})
     @IR(counts = {"vmulL_uint_sve2", " >0 "}, phase = CompilePhase.FINAL_CODE,
         applyIfCPUFeature = {"sve2", "true"})
@@ -135,7 +136,8 @@ public class VectorMultiplyOpt {
     }
 
     @Test
-    @IR(counts = {IRNode.MUL_VL, " >0 ", IRNode.AND_VL, " >0 ", IRNode.URSHIFT_VL, " >0 "}, applyIfCPUFeature = {"avx", "true"})
+    @IR(counts = {IRNode.MUL_VL, " >0 ", IRNode.AND_VL, " >0 ", IRNode.URSHIFT_VL, " >0 "},
+        applyIfCPUFeatureOr = {"avx", "true", "rvv", "true"})
     @IR(counts = {"vmuludq", " >0 "}, phase = CompilePhase.FINAL_CODE, applyIfCPUFeature = {"avx", "true"})
     @IR(counts = {"vmulL_uint_sve2", " >0 "}, phase = CompilePhase.FINAL_CODE,
         applyIfCPUFeature = {"sve2", "true"})
@@ -163,7 +165,8 @@ public class VectorMultiplyOpt {
     }
 
     @Test
-    @IR(counts = {IRNode.MUL_VL, " >0 ", IRNode.URSHIFT_VL, " >0 "}, applyIfCPUFeature = {"avx", "true"})
+    @IR(counts = {IRNode.MUL_VL, " >0 ", IRNode.URSHIFT_VL, " >0 "},
+        applyIfCPUFeatureOr = {"avx", "true", "rvv", "true"})
     @IR(counts = {"vmuludq", " >0 "}, phase = CompilePhase.FINAL_CODE, applyIfCPUFeature = {"avx", "true"})
     @IR(counts = {"vmulL_uint_sve2", " >0 "}, phase = CompilePhase.FINAL_CODE,
         applyIfCPUFeature = {"sve2", "true"})
@@ -191,7 +194,8 @@ public class VectorMultiplyOpt {
     }
 
     @Test
-    @IR(counts = {IRNode.MUL_VL, " >0 ", IRNode.URSHIFT_VL, " >0 "}, applyIfCPUFeature = {"avx", "true"})
+    @IR(counts = {IRNode.MUL_VL, " >0 ", IRNode.URSHIFT_VL, " >0 "},
+        applyIfCPUFeatureOr = {"avx", "true", "rvv", "true"})
     @IR(counts = {"vmuludq", " >0 "}, applyIfCPUFeature = {"avx", "true"}, phase = CompilePhase.FINAL_CODE)
     @IR(counts = {"vmulL_uint_sve2", " >0 "}, phase = CompilePhase.FINAL_CODE,
         applyIfCPUFeature = {"sve2", "true"})
@@ -219,7 +223,8 @@ public class VectorMultiplyOpt {
     }
 
     @Test
-    @IR(counts = {IRNode.MUL_VL, " >0 ", IRNode.VECTOR_CAST_I2L, " >0 "}, applyIfCPUFeature = {"avx", "true"})
+    @IR(counts = {IRNode.MUL_VL, " >0 ", IRNode.VECTOR_CAST_I2L, " >0 "},
+        applyIfCPUFeatureOr = {"avx", "true", "rvv", "true"})
     @IR(counts = {"vmuldq", " >0 "}, applyIfCPUFeature = {"avx", "true"}, phase = CompilePhase.FINAL_CODE)
     @IR(counts = {"vmulL_int_sve2", " >0 "}, phase = CompilePhase.FINAL_CODE,
         applyIfCPUFeature = {"sve2", "true"})
@@ -250,7 +255,8 @@ public class VectorMultiplyOpt {
 
 
     @Test
-    @IR(counts = {IRNode.MUL_VL, " >0 ", IRNode.RSHIFT_VL, " >0 "}, applyIfCPUFeature = {"avx", "true"})
+    @IR(counts = {IRNode.MUL_VL, " >0 ", IRNode.RSHIFT_VL, " >0 "},
+        applyIfCPUFeatureOr = {"avx", "true", "rvv", "true"})
     @IR(counts = {"vmuldq", " >0 "}, applyIfCPUFeature = {"avx", "true"}, phase = CompilePhase.FINAL_CODE)
     @IR(counts = {"vmulL_int_sve2", " >0 "}, phase = CompilePhase.FINAL_CODE,
         applyIfCPUFeature = {"sve2", "true"})
@@ -280,7 +286,8 @@ public class VectorMultiplyOpt {
     // Same-operand multiplication (v * v) where v has zero-extended high bits.
     // On NEON this should map to the dedicated rule that emits a single xtn.
     @Test
-    @IR(counts = {IRNode.MUL_VL, " >0 ", IRNode.AND_VL, " >0 "}, applyIfCPUFeature = {"avx", "true"})
+    @IR(counts = {IRNode.MUL_VL, " >0 ", IRNode.AND_VL, " >0 "},
+        applyIfCPUFeatureOr = {"avx", "true", "rvv", "true"})
     @IR(counts = {"vmuludq", " >0 "}, phase = CompilePhase.FINAL_CODE, applyIfCPUFeature = {"avx", "true"})
     @IR(counts = {"vmulL_uint_sve2", " >0 "}, phase = CompilePhase.FINAL_CODE,
         applyIfCPUFeature = {"sve2", "true"})
@@ -309,7 +316,8 @@ public class VectorMultiplyOpt {
     // Same-operand multiplication (v * v) where v has sign-extended high bits.
     // On NEON this should map to the dedicated rule that emits a single xtn.
     @Test
-    @IR(counts = {IRNode.MUL_VL, " >0 ", IRNode.VECTOR_CAST_I2L, " >0 "}, applyIfCPUFeature = {"avx", "true"})
+    @IR(counts = {IRNode.MUL_VL, " >0 ", IRNode.VECTOR_CAST_I2L, " >0 "},
+        applyIfCPUFeatureOr = {"avx", "true", "rvv", "true"})
     @IR(counts = {"vmuldq", " >0 "}, applyIfCPUFeature = {"avx", "true"}, phase = CompilePhase.FINAL_CODE)
     @IR(counts = {"vmulL_int_sve2", " >0 "}, phase = CompilePhase.FINAL_CODE,
         applyIfCPUFeature = {"sve2", "true"})