diff --git a/src/hotspot/cpu/aarch64/assembler_aarch64.hpp b/src/hotspot/cpu/aarch64/assembler_aarch64.hpp
index 70eb8b57e52..036dc053291 100644
--- a/src/hotspot/cpu/aarch64/assembler_aarch64.hpp
+++ b/src/hotspot/cpu/aarch64/assembler_aarch64.hpp
@@ -3158,9 +3158,9 @@ private:
     int q = (Tb == T4H || Tb == T2S) ? 0 : 1;
     int h = (size == 0b01) ? ((lane >> 2) & 1) : ((lane >> 1) & 1);
     int l = (size == 0b01) ? ((lane >> 1) & 1) : (lane & 1);
-    int m = lane & 1;
-    assert((size == 0b10 ? lane < 4 : lane < 7));
-    f(0, 31), f(q, 30), f(1, 29), f(0b01111, 28, 24), f(size, 23, 22), f(l, 21), f(m, 20);
+    assert(size == 0b10 ? lane < 4 : lane < 8, "umullv assumes lane < 4 when using half-words and lane < 8 otherwise");
+    assert(Ts == H ? Vm->encoding() < 16 : Vm->encoding() < 32, "umullv requires Vm to be in range V0..V15 when Ts is H");
+    f(0, 31), f(q, 30), f(0b101111, 29, 24), f(size, 23, 22), f(l, 21); //f(m, 20);
     rf(Vm, 16), f(0b1010, 15, 12), f(h, 11), f(0, 10), rf(Vn, 5), rf(Vd, 0);
   }
 
@@ -3178,17 +3178,15 @@ public:
   //Vector by element variant of UMULL
   void umullv(FloatRegister Vd, SIMD_Arrangement Ta, FloatRegister Vn,
                SIMD_Arrangement Tb, FloatRegister Vm, SIMD_RegVariant Ts, int lane) {
-    assert(Tb == T8B || Tb == T4H || Tb == T2S, "umullv assumes T8B, T4H, or T2S as the Tb size specifier");
-    assert(Ts == H || Ts == S, "umullv assumes H or S as the RegVariant for Ts");
-    assert(Ts == H ? Tb == T4H : Tb == T2S, "umullv assumes Tb is T4H when Ts is H");
+    assert(Ta == T4S || Ta == T2D, "umullv destination register must have arrangement T4S or T2D");
+    assert(Ta == T4S ? (Tb == T4H && Ts == H) : (Tb == T2S && Ts == S), "umullv register arrangements must adhere to spec");
     _umullv(Vd, Ta, Vn, Tb, Vm, Ts, lane);
   }
 
   void umull2v(FloatRegister Vd, SIMD_Arrangement Ta, FloatRegister Vn,
                SIMD_Arrangement Tb, FloatRegister Vm, SIMD_RegVariant Ts, int lane) {
-    assert(Tb == T16B || Tb == T8H || Tb == T4S, "umull2v assumes T16B, T8H, or T4S as the size specifier");
-    assert(Ts == H || Ts == S, "umull2v assumes H or S as the RegVariant for Ts");
-    assert(Ts == H ? Tb == T8H : Tb == T4S, "umull2v assumes Tb is T8H when Ts is H");
+    assert(Ta == T4S || Ta == T2D, "umullv destination register must have arrangement T4S or T2D");
+    assert(Ta == T4S ? (Tb == T8H && Ts == H) : (Tb == T4S && Ts == S), "umullv register arrangements must adhere to spec");
     _umullv(Vd, Ta, Vn, Tb, Vm, Ts, lane);
   }
 
diff --git a/src/hotspot/cpu/aarch64/stubGenerator_aarch64.cpp b/src/hotspot/cpu/aarch64/stubGenerator_aarch64.cpp
index e93d528b5cb..19a1256d3b3 100644
--- a/src/hotspot/cpu/aarch64/stubGenerator_aarch64.cpp
+++ b/src/hotspot/cpu/aarch64/stubGenerator_aarch64.cpp
@@ -7312,7 +7312,7 @@ class StubGenerator: public StubCodeGenerator {
 
       // low_0 += c_i
       // n = low_0 & limb_mask
-      __ eor(c_01, __ T2D, c_01, c_01);
+      __ eor(c_01, __ T16B, c_01, c_01);
       __ ld1(c_01, __ D, 0, c_ptr);
       __ addv(low_01, __ T2D, low_01, c_01);
       __ andr(n, __ T16B, low_01, limb_mask);