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8259822: [PPC64] Support the prefixed instruction format added in POWER10
Reviewed-by: cashford, mdoerr
This commit is contained in:
Kazunori Ogata
Martin Doerr
parent
a45733f840
commit
f7a6c63ad3
@ -1,6 +1,6 @@
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/*
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* Copyright (c) 2002, 2020, Oracle and/or its affiliates. All rights reserved.
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* Copyright (c) 2012, 2020 SAP SE. All rights reserved.
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* Copyright (c) 2002, 2021, Oracle and/or its affiliates. All rights reserved.
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* Copyright (c) 2012, 2021 SAP SE. All rights reserved.
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* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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*
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* This code is free software; you can redistribute it and/or modify it
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@ -221,6 +221,12 @@ class Assembler : public AbstractAssembler {
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SPR_0_4_SHIFT = 16u, // SPR_0_4 field in bits 16 -- 20
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RS_SHIFT = 21u, // RS field in bits 21 -- 25
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OPCODE_SHIFT = 26u, // opcode in bits 26 -- 31
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// Shift counts in prefix word
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PRE_TYPE_SHIFT = 24u, // Prefix type in bits 24 -- 25
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PRE_ST1_SHIFT = 23u, // ST1 field in bits 23 -- 23
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PRE_R_SHIFT = 20u, // R-bit in bits 20 -- 20
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PRE_ST4_SHIFT = 20u, // ST4 field in bits 23 -- 20
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};
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enum opcdxos_masks {
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@ -797,6 +803,28 @@ class Assembler : public AbstractAssembler {
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};
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enum opcdeos_mask {
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// Mask for prefix primary opcode field
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PREFIX_OPCODE_MASK = (63u << OPCODE_SHIFT),
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// Mask for prefix opcode and type fields
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PREFIX_OPCODE_TYPE_MASK = (63u << OPCODE_SHIFT) | (3u << PRE_TYPE_SHIFT),
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// Masks for type 00/10 and type 01/11, including opcode, type, and st fieds
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PREFIX_OPCODE_TYPEx0_MASK = PREFIX_OPCODE_TYPE_MASK | ( 1u << PRE_ST1_SHIFT),
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PREFIX_OPCODE_TYPEx1_MASK = PREFIX_OPCODE_TYPE_MASK | (15u << PRE_ST4_SHIFT),
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// Masks for each instructions
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PADDI_PREFIX_OPCODE_MASK = PREFIX_OPCODE_TYPEx0_MASK,
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PADDI_SUFFIX_OPCODE_MASK = ADDI_OPCODE_MASK,
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};
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enum opcdeos {
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PREFIX_PRIMARY_OPCODE = (1u << OPCODE_SHIFT),
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// Prefixed addi/li
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PADDI_PREFIX_OPCODE = PREFIX_PRIMARY_OPCODE | (2u << PRE_TYPE_SHIFT),
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PADDI_SUFFIX_OPCODE = ADDI_OPCODE,
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};
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// Trap instructions TO bits
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enum trap_to_bits {
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// single bits
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@ -1082,6 +1110,20 @@ class Assembler : public AbstractAssembler {
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static int inv_bo_field(int x) { return inv_opp_u_field(x, 10, 6); }
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static int inv_bi_field(int x) { return inv_opp_u_field(x, 15, 11); }
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// For extended opcodes (prefixed instructions) introduced with Power 10
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static long inv_r_eo( int x) { return inv_opp_u_field(x, 11, 11); }
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static long inv_type( int x) { return inv_opp_u_field(x, 7, 6); }
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static long inv_st_x0( int x) { return inv_opp_u_field(x, 8, 8); }
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static long inv_st_x1( int x) { return inv_opp_u_field(x, 11, 8); }
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// - 8LS:D/MLS:D Formats
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static long inv_d0_eo( long x) { return inv_opp_u_field(x, 31, 14); }
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// - 8RR:XX4/8RR:D Formats
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static long inv_imm0_eo(int x) { return inv_opp_u_field(x, 31, 16); }
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static long inv_uimm_eo(int x) { return inv_opp_u_field(x, 31, 29); }
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static long inv_imm_eo( int x) { return inv_opp_u_field(x, 31, 24); }
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#define opp_u_field(x, hi_bit, lo_bit) u_field(x, 31-(lo_bit), 31-(hi_bit))
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#define opp_s_field(x, hi_bit, lo_bit) s_field(x, 31-(lo_bit), 31-(hi_bit))
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@ -1203,6 +1245,24 @@ class Assembler : public AbstractAssembler {
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static int vcmp_rc( int x) { return opp_u_field(x, 21, 21); } // for vcmp* instructions
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static int xxsplt_uim(int x) { return opp_u_field(x, 15, 14); } // for xxsplt* instructions
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// For extended opcodes (prefixed instructions) introduced with Power 10
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static long r_eo( int x) { return opp_u_field(x, 11, 11); }
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static long type( int x) { return opp_u_field(x, 7, 6); }
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static long st_x0( int x) { return opp_u_field(x, 8, 8); }
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static long st_x1( int x) { return opp_u_field(x, 11, 8); }
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// - 8LS:D/MLS:D Formats
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static long d0_eo( long x) { return opp_u_field((x >> 16) & 0x3FFFF, 31, 14); }
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static long d1_eo( long x) { return opp_u_field(x & 0xFFFF, 31, 16); }
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static long s0_eo( long x) { return d0_eo(x); }
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static long s1_eo( long x) { return d1_eo(x); }
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// - 8RR:XX4/8RR:D Formats
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static long imm0_eo( int x) { return opp_u_field(x >> 16, 31, 16); }
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static long imm1_eo( int x) { return opp_u_field(x & 0xFFFF, 31, 16); }
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static long uimm_eo( int x) { return opp_u_field(x, 31, 29); }
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static long imm_eo( int x) { return opp_u_field(x, 31, 24); }
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//static int xo1( int x) { return opp_u_field(x, 29, 21); }// is contained in our opcodes
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//static int xo2( int x) { return opp_u_field(x, 30, 21); }// is contained in our opcodes
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//static int xo3( int x) { return opp_u_field(x, 30, 22); }// is contained in our opcodes
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@ -1302,9 +1362,15 @@ class Assembler : public AbstractAssembler {
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// PPC 1, section 3.3.8, Fixed-Point Arithmetic Instructions
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inline void addi( Register d, Register a, int si16);
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inline void addis(Register d, Register a, int si16);
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// Prefixed add immediate, introduced by POWER10
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inline void paddi(Register d, Register a, long si34, bool r);
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inline void pli( Register d, long si34);
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private:
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inline void addi_r0ok( Register d, Register a, int si16);
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inline void addis_r0ok(Register d, Register a, int si16);
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inline void paddi_r0ok(Register d, Register a, long si34, bool r);
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public:
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inline void addic_( Register d, Register a, int si16);
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inline void subfic( Register d, Register a, int si16);
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@ -131,6 +131,17 @@ inline void Assembler::divw_( Register d, Register a, Register b) { emit_int32(
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inline void Assembler::divwu( Register d, Register a, Register b) { emit_int32(DIVWU_OPCODE | rt(d) | ra(a) | rb(b) | oe(0) | rc(0)); }
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inline void Assembler::divwu_( Register d, Register a, Register b) { emit_int32(DIVWU_OPCODE | rt(d) | ra(a) | rb(b) | oe(0) | rc(1)); }
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// Prefixed instructions, introduced by POWER10
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inline void Assembler::paddi(Register d, Register a, long si34, bool r = false) {
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assert(a != R0 || r, "r0 not allowed, unless R is set (CIA relative)");
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paddi_r0ok( d, a, si34, r);
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}
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inline void Assembler::paddi_r0ok(Register d, Register a, long si34, bool r = false) {
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emit_int32(PADDI_PREFIX_OPCODE | r_eo(r) | d0_eo(si34));
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emit_int32(PADDI_SUFFIX_OPCODE | rt(d) | ra(a) | d1_eo(si34));
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}
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// Fixed-Point Arithmetic Instructions with Overflow detection
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inline void Assembler::addo( Register d, Register a, Register b) { emit_int32(ADD_OPCODE | rt(d) | ra(a) | rb(b) | oe(1) | rc(0)); }
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inline void Assembler::addo_( Register d, Register a, Register b) { emit_int32(ADD_OPCODE | rt(d) | ra(a) | rb(b) | oe(1) | rc(1)); }
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@ -169,6 +180,9 @@ inline void Assembler::lis( Register d, int si16) { Assembler::addi
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inline void Assembler::addir(Register d, int si16, Register a) { Assembler::addi(d, a, si16); }
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inline void Assembler::subi( Register d, Register a, int si16) { Assembler::addi(d, a, -si16); }
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// Prefixed instructions, introduced by POWER10
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inline void Assembler::pli(Register d, long si34) { Assembler::paddi_r0ok( d, R0, si34, false); }
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// PPC 1, section 3.3.9, Fixed-Point Compare Instructions
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inline void Assembler::cmpi( ConditionRegister f, int l, Register a, int si16) { emit_int32( CMPI_OPCODE | bf(f) | l10(l) | ra(a) | simm(si16,16)); }
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inline void Assembler::cmp( ConditionRegister f, int l, Register a, Register b) { emit_int32( CMP_OPCODE | bf(f) | l10(l) | ra(a) | rb(b)); }
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@ -1155,7 +1155,41 @@ static int cc_to_biint(int cc, int flags_reg) {
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// is the number of bytes (not instructions) which will be inserted before
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// the instruction. The padding must match the size of a NOP instruction.
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// Currently not used on this platform.
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// Add nop if a prefixed (two-word) instruction is going to cross a 64-byte boundary.
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// (See Section 1.6 of Power ISA Version 3.1)
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static int compute_prefix_padding(int current_offset) {
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assert(PowerArchitecturePPC64 >= 10 && (CodeEntryAlignment & 63) == 0,
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"Code buffer must be aligned to a multiple of 64 bytes");
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if (is_aligned(current_offset + BytesPerInstWord, 64)) {
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return BytesPerInstWord;
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}
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return 0;
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}
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int loadConI32Node::compute_padding(int current_offset) const {
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return compute_prefix_padding(current_offset);
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}
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int loadConL34Node::compute_padding(int current_offset) const {
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return compute_prefix_padding(current_offset);
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}
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int addI_reg_imm32Node::compute_padding(int current_offset) const {
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return compute_prefix_padding(current_offset);
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}
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int addL_reg_imm34Node::compute_padding(int current_offset) const {
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return compute_prefix_padding(current_offset);
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}
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int addP_reg_imm34Node::compute_padding(int current_offset) const {
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return compute_prefix_padding(current_offset);
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}
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int cmprb_Whitespace_reg_reg_prefixedNode::compute_padding(int current_offset) const {
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return compute_prefix_padding(current_offset);
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}
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//=============================================================================
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@ -1893,7 +1927,7 @@ uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
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#ifndef PRODUCT
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void MachNopNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
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st->print("NOP \t// %d nops to pad for loops.", _count);
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st->print("NOP \t// %d nops to pad for loops or prefixed instructions.", _count);
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}
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#endif
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@ -4016,6 +4050,15 @@ operand immIhi16() %{
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interface(CONST_INTER);
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%}
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// Integer Immediate: 32-bit immediate for prefixed addi and load/store.
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operand immI32() %{
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predicate(PowerArchitecturePPC64 >= 10);
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op_cost(0);
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match(ConI);
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format %{ %}
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interface(CONST_INTER);
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%}
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operand immInegpow2() %{
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predicate(is_power_of_2(-(juint)(n->get_int())));
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match(ConI);
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@ -4257,6 +4300,15 @@ operand immL32() %{
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interface(CONST_INTER);
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%}
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// Long Immediate: 34-bit, immediate field in prefixed addi and load/store.
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operand immL34() %{
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predicate(PowerArchitecturePPC64 >= 10 && Assembler::is_simm(n->get_long(), 34));
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match(ConL);
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op_cost(0);
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format %{ %}
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interface(CONST_INTER);
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%}
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// Long Immediate: 64-bit, where highest 16 bits are not 0x0000.
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operand immLhighest16() %{
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predicate((n->get_long() & 0xffff000000000000L) != 0L && (n->get_long() & 0x0000ffffffffffffL) == 0L);
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@ -5791,6 +5843,23 @@ instruct loadConI32_lo16(iRegIdst dst, iRegIsrc src1, immI16 src2) %{
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ins_pipe(pipe_class_default);
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%}
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instruct loadConI32(iRegIdst dst, immI32 src) %{
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match(Set dst src);
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// This macro is valid only in Power 10 and up, but adding the following predicate here
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// caused a build error, so we comment it out for now.
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// predicate(PowerArchitecturePPC64 >= 10);
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ins_cost(DEFAULT_COST+1);
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format %{ "PLI $dst, $src" %}
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size(8);
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ins_encode %{
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assert( ((intptr_t)(__ pc()) & 0x3c) != 0x3c, "Bad alignment for prefixed instruction at " INTPTR_FORMAT, (intptr_t)(__ pc()));
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__ pli($dst$$Register, $src$$constant);
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%}
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ins_pipe(pipe_class_default);
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ins_alignment(2);
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%}
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instruct loadConI_Ex(iRegIdst dst, immI src) %{
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match(Set dst src);
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ins_cost(DEFAULT_COST*2);
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@ -5862,6 +5931,24 @@ instruct loadConL32_Ex(iRegLdst dst, immL32 src) %{
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%}
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%}
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// Load 34-bit long constant using prefixed addi. No constant pool entries required.
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instruct loadConL34(iRegLdst dst, immL34 src) %{
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match(Set dst src);
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// This macro is valid only in Power 10 and up, but adding the following predicate here
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// caused a build error, so we comment it out for now.
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// predicate(PowerArchitecturePPC64 >= 10);
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ins_cost(DEFAULT_COST+1);
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format %{ "PLI $dst, $src \t// long" %}
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size(8);
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ins_encode %{
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assert( ((intptr_t)(__ pc()) & 0x3c) != 0x3c, "Bad alignment for prefixed instruction at " INTPTR_FORMAT, (intptr_t)(__ pc()));
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__ pli($dst$$Register, $src$$constant);
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%}
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ins_pipe(pipe_class_default);
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ins_alignment(2);
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%}
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// Load long constant 0x????000000000000.
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instruct loadConLhighest16_Ex(iRegLdst dst, immLhighest16 src) %{
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match(Set dst src);
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@ -8474,6 +8561,21 @@ instruct addI_reg_immhi16(iRegIdst dst, iRegIsrc src1, immIhi16 src2) %{
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ins_pipe(pipe_class_default);
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%}
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// Immediate Addition using prefixed addi
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instruct addI_reg_imm32(iRegIdst dst, iRegIsrc src1, immI32 src2) %{
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match(Set dst (AddI src1 src2));
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predicate(PowerArchitecturePPC64 >= 10);
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ins_cost(DEFAULT_COST+1);
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format %{ "PADDI $dst, $src1, $src2" %}
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size(8);
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ins_encode %{
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assert( ((intptr_t)(__ pc()) & 0x3c) != 0x3c, "Bad alignment for prefixed instruction at " INTPTR_FORMAT, (intptr_t)(__ pc()));
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__ paddi($dst$$Register, $src1$$Register, $src2$$constant);
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%}
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ins_pipe(pipe_class_default);
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ins_alignment(2);
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%}
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// Long Addition
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instruct addL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
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match(Set dst (AddL src1 src2));
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@ -8548,6 +8650,23 @@ instruct addL_reg_immhi16(iRegLdst dst, iRegLsrc src1, immL32hi16 src2) %{
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ins_pipe(pipe_class_default);
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%}
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// Long Immediate Addition using prefixed addi
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// No constant pool entries required.
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instruct addL_reg_imm34(iRegLdst dst, iRegLsrc src1, immL34 src2) %{
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match(Set dst (AddL src1 src2));
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predicate(PowerArchitecturePPC64 >= 10);
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ins_cost(DEFAULT_COST+1);
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format %{ "PADDI $dst, $src1, $src2" %}
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size(8);
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ins_encode %{
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assert( ((intptr_t)(__ pc()) & 0x3c) != 0x3c, "Bad alignment for prefixed instruction at " INTPTR_FORMAT, (intptr_t)(__ pc()));
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__ paddi($dst$$Register, $src1$$Register, $src2$$constant);
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%}
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ins_pipe(pipe_class_default);
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ins_alignment(2);
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%}
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// Pointer Register Addition
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instruct addP_reg_reg(iRegPdst dst, iRegP_N2P src1, iRegLsrc src2) %{
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match(Set dst (AddP src1 src2));
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@ -8585,6 +8704,23 @@ instruct addP_reg_immhi16(iRegPdst dst, iRegP_N2P src1, immL32hi16 src2) %{
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ins_pipe(pipe_class_default);
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%}
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// Pointer Immediate Addition using prefixed addi
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// No constant pool entries required.
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instruct addP_reg_imm34(iRegPdst dst, iRegP_N2P src1, immL34 src2) %{
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match(Set dst (AddP src1 src2));
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predicate(PowerArchitecturePPC64 >= 10);
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ins_cost(DEFAULT_COST+1);
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format %{ "PADDI $dst, $src1, $src2" %}
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size(8);
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ins_encode %{
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assert( ((intptr_t)(__ pc()) & 0x3c) != 0x3c, "Bad alignment for prefixed instruction at " INTPTR_FORMAT, (intptr_t)(__ pc()));
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__ paddi($dst$$Register, $src1$$Register, $src2$$constant);
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%}
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ins_pipe(pipe_class_default);
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ins_alignment(2);
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%}
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//---------------------
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// Subtraction Instructions
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@ -11887,6 +12023,7 @@ instruct cmprb_UpperCase_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2, fla
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instruct cmprb_Whitespace_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2, flagsReg crx) %{
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match(Set dst (Whitespace src1));
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predicate(PowerArchitecturePPC64 <= 9);
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effect(TEMP src2, TEMP crx);
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ins_cost(4 * DEFAULT_COST);
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@ -11906,6 +12043,29 @@ instruct cmprb_Whitespace_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2, fl
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ins_pipe(pipe_class_default);
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%}
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// Power 10 version, using prefixed addi to load 32-bit constant
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instruct cmprb_Whitespace_reg_reg_prefixed(iRegIdst dst, iRegIsrc src1, iRegIsrc src2, flagsReg crx) %{
|
||||
match(Set dst (Whitespace src1));
|
||||
predicate(PowerArchitecturePPC64 >= 10);
|
||||
effect(TEMP src2, TEMP crx);
|
||||
ins_cost(3 * DEFAULT_COST);
|
||||
|
||||
format %{ "PLI $src2, 0x201C0D09\n\t"
|
||||
"CMPRB $crx, 1, $src1, $src2\n\t"
|
||||
"SETB $dst, $crx" %}
|
||||
size(16);
|
||||
ins_encode %{
|
||||
// 0x09 to 0x0D, 0x1C to 0x20
|
||||
assert( ((intptr_t)(__ pc()) & 0x3c) != 0x3c, "Bad alignment for prefixed instruction at " INTPTR_FORMAT, (intptr_t)(__ pc()));
|
||||
__ pli($src2$$Register, 0x201C0D09);
|
||||
// compare src with ranges 0x09 to 0x0D and 0x1C to 0x20
|
||||
__ cmprb($crx$$CondRegister, 1, $src1$$Register, $src2$$Register);
|
||||
__ setb($dst$$Register, $crx$$CondRegister);
|
||||
%}
|
||||
ins_pipe(pipe_class_default);
|
||||
ins_alignment(2);
|
||||
%}
|
||||
|
||||
//----------Branches---------------------------------------------------------
|
||||
// Jump
|
||||
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user