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https://github.com/openjdk/jdk.git
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8352585: Add special case handling for Float16.max/min x86 backend
Reviewed-by: epeter, sviswanathan
This commit is contained in:
Jatin Bhateja
parent
9c5ed23eac
commit
f7a94feedd
@ -13810,6 +13810,16 @@ void Assembler::vcmpps(XMMRegister dst, XMMRegister nds, XMMRegister src, int co
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emit_int24((unsigned char)0xC2, (0xC0 | encode), (unsigned char)comparison);
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}
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void Assembler::evcmpsh(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src, ComparisonPredicateFP comparison) {
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assert(VM_Version::supports_avx512_fp16(), "");
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InstructionAttr attributes(Assembler::AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
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attributes.set_is_evex_instruction();
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attributes.set_embedded_opmask_register_specifier(mask);
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attributes.reset_is_clear_context();
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int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_3A, &attributes);
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emit_int24((unsigned char)0xC2, (0xC0 | encode), comparison);
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}
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void Assembler::evcmpps(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src,
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ComparisonPredicateFP comparison, int vector_len) {
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assert(VM_Version::supports_evex(), "");
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@ -3195,6 +3195,9 @@ private:
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void evcmpps(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src,
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ComparisonPredicateFP comparison, int vector_len);
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void evcmpsh(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src,
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ComparisonPredicateFP comparison);
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// Vector integer compares
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void vpcmpgtd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
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void evpcmpd(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src,
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@ -6680,8 +6680,6 @@ void C2_MacroAssembler::efp16sh(int opcode, XMMRegister dst, XMMRegister src1, X
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case Op_SubHF: vsubsh(dst, src1, src2); break;
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case Op_MulHF: vmulsh(dst, src1, src2); break;
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case Op_DivHF: vdivsh(dst, src1, src2); break;
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case Op_MaxHF: vmaxsh(dst, src1, src2); break;
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case Op_MinHF: vminsh(dst, src1, src2); break;
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default: assert(false, "%s", NodeClassNames[opcode]); break;
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}
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}
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@ -7091,3 +7089,48 @@ void C2_MacroAssembler::vector_saturating_op(int ideal_opc, BasicType elem_bt, X
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vector_saturating_op(ideal_opc, elem_bt, dst, src1, src2, vlen_enc);
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}
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}
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void C2_MacroAssembler::scalar_max_min_fp16(int opcode, XMMRegister dst, XMMRegister src1, XMMRegister src2,
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KRegister ktmp, XMMRegister xtmp1, XMMRegister xtmp2, int vlen_enc) {
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if (opcode == Op_MaxHF) {
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// Move sign bits of src2 to mask register.
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evpmovw2m(ktmp, src2, vlen_enc);
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// xtmp1 = src2 < 0 ? src2 : src1
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evpblendmw(xtmp1, ktmp, src1, src2, true, vlen_enc);
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// xtmp2 = src2 < 0 ? ? src1 : src2
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evpblendmw(xtmp2, ktmp, src2, src1, true, vlen_enc);
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// Idea behind above swapping is to make seconds source operand a +ve value.
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// As per instruction semantic, if the values being compared are both 0.0s (of either sign), the value in
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// the second source operand is returned. If only one value is a NaN (SNaN or QNaN) for this instruction,
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// the second source operand, either a NaN or a valid floating-point value, is returned
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// dst = max(xtmp1, xtmp2)
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vmaxsh(dst, xtmp1, xtmp2);
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// isNaN = is_unordered_quiet(xtmp1)
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evcmpsh(ktmp, k0, xtmp1, xtmp1, Assembler::UNORD_Q);
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// Final result is same as first source if its a NaN value,
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// in case second operand holds a NaN value then as per above semantics
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// result is same as second operand.
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Assembler::evmovdquw(dst, ktmp, xtmp1, true, vlen_enc);
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} else {
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assert(opcode == Op_MinHF, "");
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// Move sign bits of src1 to mask register.
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evpmovw2m(ktmp, src1, vlen_enc);
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// xtmp1 = src1 < 0 ? src2 : src1
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evpblendmw(xtmp1, ktmp, src1, src2, true, vlen_enc);
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// xtmp2 = src1 < 0 ? src1 : src2
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evpblendmw(xtmp2, ktmp, src2, src1, true, vlen_enc);
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// Idea behind above swapping is to make seconds source operand a -ve value.
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// As per instruction semantics, if the values being compared are both 0.0s (of either sign), the value in
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// the second source operand is returned.
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// If only one value is a NaN (SNaN or QNaN) for this instruction, the second source operand, either a NaN
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// or a valid floating-point value, is written to the result.
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// dst = min(xtmp1, xtmp2)
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vminsh(dst, xtmp1, xtmp2);
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// isNaN = is_unordered_quiet(xtmp1)
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evcmpsh(ktmp, k0, xtmp1, xtmp1, Assembler::UNORD_Q);
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// Final result is same as first source if its a NaN value,
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// in case second operand holds a NaN value then as per above semantics
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// result is same as second operand.
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Assembler::evmovdquw(dst, ktmp, xtmp1, true, vlen_enc);
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}
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}
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@ -584,4 +584,6 @@ public:
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void select_from_two_vectors_evex(BasicType elem_bt, XMMRegister dst, XMMRegister src1, XMMRegister src2, int vlen_enc);
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void scalar_max_min_fp16(int opcode, XMMRegister dst, XMMRegister src1, XMMRegister src2,
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KRegister ktmp, XMMRegister xtmp1, XMMRegister xtmp2, int vlen_enc);
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#endif // CPU_X86_C2_MACROASSEMBLER_X86_HPP
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@ -1461,11 +1461,14 @@ bool Matcher::match_rule_supported(int opcode) {
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return false;
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}
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break;
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case Op_MaxHF:
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case Op_MinHF:
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if (!VM_Version::supports_avx512vlbw()) {
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return false;
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} // fallthrough
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case Op_AddHF:
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case Op_DivHF:
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case Op_FmaHF:
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case Op_MaxHF:
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case Op_MinHF:
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case Op_MulHF:
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case Op_ReinterpretS2HF:
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case Op_ReinterpretHF2S:
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@ -10935,8 +10938,6 @@ instruct scalar_binOps_HF_reg(regF dst, regF src1, regF src2)
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%{
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match(Set dst (AddHF src1 src2));
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match(Set dst (DivHF src1 src2));
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match(Set dst (MaxHF src1 src2));
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match(Set dst (MinHF src1 src2));
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match(Set dst (MulHF src1 src2));
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match(Set dst (SubHF src1 src2));
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format %{ "scalar_binop_fp16 $dst, $src1, $src2" %}
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@ -10947,6 +10948,20 @@ instruct scalar_binOps_HF_reg(regF dst, regF src1, regF src2)
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ins_pipe(pipe_slow);
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%}
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instruct scalar_minmax_HF_reg(regF dst, regF src1, regF src2, kReg ktmp, regF xtmp1, regF xtmp2)
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%{
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match(Set dst (MaxHF src1 src2));
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match(Set dst (MinHF src1 src2));
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effect(TEMP_DEF dst, TEMP ktmp, TEMP xtmp1, TEMP xtmp2);
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format %{ "scalar_min_max_fp16 $dst, $src1, $src2\t using $ktmp, $xtmp1 and $xtmp2 as TEMP" %}
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ins_encode %{
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int opcode = this->ideal_Opcode();
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__ scalar_max_min_fp16(opcode, $dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, $ktmp$$KRegister,
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$xtmp1$$XMMRegister, $xtmp2$$XMMRegister, Assembler::AVX_128bit);
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%}
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ins_pipe( pipe_slow );
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%}
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instruct scalar_fma_HF_reg(regF dst, regF src1, regF src2)
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%{
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match(Set dst (FmaHF src2 (Binary dst src1)));
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@ -0,0 +1,175 @@
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/*
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* Copyright (c) 2025, Oracle and/or its affiliates. All rights reserved.
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* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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*
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* This code is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 only, as
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* published by the Free Software Foundation.
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*
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* This code is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* version 2 for more details (a copy is included in the LICENSE file that
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* accompanied this code).
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*
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* You should have received a copy of the GNU General Public License version
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* 2 along with this work; if not, write to the Free Software Foundation,
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* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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*
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* Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
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* or visit www.oracle.com if you need additional information or have any
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* questions.
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*/
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package compiler.intrinsics.float16;
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import compiler.lib.ir_framework.*;
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import jdk.incubator.vector.*;
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import java.util.Random;
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import jdk.test.lib.*;
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/**
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* @test
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* @bug 8352585
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* @library /test/lib /
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* @summary Add special case handling for Float16.max/min x86 backend
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* @modules jdk.incubator.vector
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* @run driver compiler.intrinsics.float16.TestFloat16MaxMinSpecialValues
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*/
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public class TestFloat16MaxMinSpecialValues {
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public static Float16 POS_ZERO = Float16.valueOf(0.0f);
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public static Float16 NEG_ZERO = Float16.valueOf(-0.0f);
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public static Float16 SRC = Float16.valueOf(Float.MAX_VALUE);
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public static Random rd = Utils.getRandomInstance();
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public static Float16 genNaN() {
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// IEEE 754 Half Precision QNaN Format
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// S EEEEE MMMMMMMMMM
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// X 11111 1XXXXXXXXX
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short sign = (short)(rd.nextBoolean() ? 1 << 15 : 0);
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short significand = (short)rd.nextInt(512);
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return Float16.shortBitsToFloat16((short)(sign | 0x7E00 | significand));
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}
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public static boolean assertionCheck(Float16 actual, Float16 expected) {
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return !actual.equals(expected);
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}
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public Float16 RES;
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public static void main(String [] args) {
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TestFramework.runWithFlags("--add-modules=jdk.incubator.vector");
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}
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@Test
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@IR(counts = {IRNode.MAX_HF, " >0 "}, applyIfCPUFeatureAnd = {"avx512_fp16", "true", "avx512bw", "true", "avx512vl", "true"})
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public Float16 testMaxNaNOperands(Float16 src1, Float16 src2) {
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return Float16.max(src1, src2);
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}
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@Run(test = "testMaxNaNOperands")
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public void launchMaxNaNOperands() {
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Float16 NAN = null;
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for (int i = 0; i < 100; i++) {
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NAN = genNaN();
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RES = testMaxNaNOperands(SRC, NAN);
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if (assertionCheck(RES, NAN)) {
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throw new AssertionError("input1 = " + SRC.floatValue() + " input2 = NaN , expected = NaN, actual = " + RES.floatValue());
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}
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NAN = genNaN();
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RES = testMaxNaNOperands(NAN, SRC);
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if (assertionCheck(RES, NAN)) {
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throw new AssertionError("input1 = NaN, input2 = " + SRC.floatValue() + ", expected = NaN, actual = " + RES.floatValue());
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}
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NAN = genNaN();
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RES = testMaxNaNOperands(NAN, NAN);
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if (assertionCheck(RES, NAN)) {
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throw new AssertionError("input1 = NaN, input2 = NaN, expected = NaN, actual = " + RES.floatValue());
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}
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}
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}
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@Test
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@IR(counts = {IRNode.MIN_HF, " >0 "}, applyIfCPUFeatureAnd = {"avx512_fp16", "true", "avx512bw", "true", "avx512vl", "true"})
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public Float16 testMinNaNOperands(Float16 src1, Float16 src2) {
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return Float16.min(src1, src2);
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}
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@Run(test = "testMinNaNOperands")
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public void launchMinNaNOperands() {
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Float16 NAN = null;
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for (int i = 0; i < 100; i++) {
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NAN = genNaN();
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RES = testMinNaNOperands(SRC, NAN);
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if (assertionCheck(RES, NAN)) {
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throw new AssertionError("input1 = " + SRC.floatValue() + " input2 = NaN, expected = NaN, actual = " + RES.floatValue());
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}
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NAN = genNaN();
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RES = testMinNaNOperands(NAN, SRC);
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if (assertionCheck(RES, NAN)) {
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throw new AssertionError("input1 = NaN, input2 = " + SRC.floatValue() + ", expected = NaN, actual = " + RES.floatValue());
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}
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NAN = genNaN();
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RES = testMinNaNOperands(NAN, NAN);
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if (assertionCheck(RES, NAN)) {
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throw new AssertionError("input1 = NaN, input2 = NaN, expected = NaN, actual = " + RES.floatValue());
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}
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}
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}
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@Test
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@IR(counts = {IRNode.MAX_HF, " >0 "}, applyIfCPUFeatureAnd = {"avx512_fp16", "true", "avx512bw", "true", "avx512vl", "true"})
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public Float16 testMaxZeroOperands(Float16 src1, Float16 src2) {
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return Float16.max(src1, src2);
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}
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@Run(test = "testMaxZeroOperands")
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public void launchMaxZeroOperands() {
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RES = testMaxZeroOperands(POS_ZERO, NEG_ZERO);
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if (assertionCheck(RES, POS_ZERO)) {
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throw new AssertionError("input1 = +0.0, input2 = -0.0, expected = +0.0, actual = " + RES.floatValue());
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}
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RES = testMaxZeroOperands(NEG_ZERO, POS_ZERO);
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if (assertionCheck(RES, POS_ZERO)) {
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throw new AssertionError("input1 = -0.0, input2 = +0.0, expected = +0.0, actual = " + RES.floatValue());
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}
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RES = testMaxZeroOperands(POS_ZERO, POS_ZERO);
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if (assertionCheck(RES, POS_ZERO)) {
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throw new AssertionError("input1 = +0.0, input2 = +0.0, expected = +0.0, actual = " + RES.floatValue());
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}
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RES = testMaxZeroOperands(NEG_ZERO, NEG_ZERO);
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if (assertionCheck(RES, NEG_ZERO)) {
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throw new AssertionError("input1 = -0.0, input2 = -0.0, expected = -0.0, actual = " + RES.floatValue());
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}
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}
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@Test
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@IR(counts = {IRNode.MIN_HF, " >0 "}, applyIfCPUFeatureAnd = {"avx512_fp16", "true", "avx512bw", "true", "avx512vl", "true"})
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public Float16 testMinZeroOperands(Float16 src1, Float16 src2) {
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return Float16.min(src1, src2);
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}
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@Run(test = "testMinZeroOperands")
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public void launchMinZeroOperands() {
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RES = testMinZeroOperands(POS_ZERO, NEG_ZERO);
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if (assertionCheck(RES, NEG_ZERO)) {
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throw new AssertionError("input1 = +0.0, input2 = -0.0, expected = -0.0, actual = " + RES.floatValue());
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}
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RES = testMinZeroOperands(NEG_ZERO, POS_ZERO);
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if (assertionCheck(RES, NEG_ZERO)) {
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throw new AssertionError("input1 = -0.0, input2 = +0.0, expected = -0.0, actual = " + RES.floatValue());
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}
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RES = testMinZeroOperands(POS_ZERO, POS_ZERO);
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if (assertionCheck(RES, POS_ZERO)) {
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throw new AssertionError("input1 = +0.0, input2 = +0.0, expected = +0.0, actual = " + RES.floatValue());
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}
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RES = testMinZeroOperands(NEG_ZERO, NEG_ZERO);
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if (assertionCheck(RES, NEG_ZERO)) {
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throw new AssertionError("input1 = -0.0, input2 = -0.0, expected = -0.0, actual = " + RES.floatValue());
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}
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}
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}
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