From fc3d3d9b303652275599e315b2d7e534d92080ea Mon Sep 17 00:00:00 2001 From: Srinivas Vamsi Parasa Date: Sat, 31 May 2025 23:07:55 +0000 Subject: [PATCH] 8351994: Enable Extended EVEX to REX2/REX demotion when src and dst are the same Reviewed-by: sviswanathan, jbhateja, epeter --- src/hotspot/cpu/x86/assembler_x86.cpp | 595 +- src/hotspot/cpu/x86/assembler_x86.hpp | 39 +- src/hotspot/cpu/x86/vm_version_x86.cpp | 12 +- src/hotspot/cpu/x86/vm_version_x86.hpp | 3 +- src/hotspot/cpu/x86/x86_64.ad | 135 - test/hotspot/gtest/x86/asmtest.out.h | 5022 ++++++++++------- test/hotspot/gtest/x86/test_assembler_x86.cpp | 2 +- test/hotspot/gtest/x86/x86-asmtest.py | 186 +- 8 files changed, 3382 insertions(+), 2612 deletions(-) diff --git a/src/hotspot/cpu/x86/assembler_x86.cpp b/src/hotspot/cpu/x86/assembler_x86.cpp index 84c08dda848..3fb64c8f644 100644 --- a/src/hotspot/cpu/x86/assembler_x86.cpp +++ b/src/hotspot/cpu/x86/assembler_x86.cpp @@ -280,15 +280,14 @@ void Assembler::emit_arith_b(int op1, int op2, Register dst, int imm8) { emit_int24(op1, (op2 | encode(dst)), imm8); } - -void Assembler::emit_arith(int op1, int op2, Register dst, int32_t imm32) { +void Assembler::emit_arith(int op1, int op2, Register dst, int32_t imm32, bool optimize_rax_dst) { assert(isByte(op1) && isByte(op2), "wrong opcode"); assert(op1 == 0x81, "Unexpected opcode"); if (is8bit(imm32)) { emit_int24(op1 | 0x02, // set sign bit op2 | encode(dst), imm32 & 0xFF); - } else if (dst == rax) { + } else if (optimize_rax_dst && dst == rax) { switch (op2) { case 0xD0: emit_int8(0x15); break; // adc case 0xC0: emit_int8(0x05); break; // add @@ -307,21 +306,6 @@ void Assembler::emit_arith(int op1, int op2, Register dst, int32_t imm32) { } } -void Assembler::emit_arith_ndd(int op1, int op2, Register dst, int32_t imm32) { - assert(isByte(op1) && isByte(op2), "wrong opcode"); - assert(op1 == 0x81, "Unexpected opcode"); - // This code cache friendly optimization saves 3 bytes per encoding, which offsets the EVEX encoding penalty. - if (is8bit(imm32)) { - emit_int24(op1 | 0x02, // set sign bit - op2 | encode(dst), - imm32 & 0xFF); - } - else { - emit_int16(op1, (op2 | encode(dst))); - emit_int32(imm32); - } -} - // Force generation of a 4 byte immediate value even if it fits into 8bit void Assembler::emit_arith_imm32(int op1, int op2, Register dst, int32_t imm32) { assert(isByte(op1) && isByte(op2), "wrong opcode"); @@ -1364,7 +1348,7 @@ void Assembler::eaddl(Register dst, Address src, int32_t imm32, bool no_flags) { InstructionMark im(this); InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); attributes.set_address_attributes(/* tuple_type */ EVEX_NOSCALE, /* input_size_in_bits */ EVEX_32bit); - evex_prefix_ndd(src, dst->encoding(), 0, VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags); + eevex_prefix_ndd(src, dst->encoding(), 0, VEX_SIMD_NONE, VEX_OPCODE_0F_3C /* MAP4 */, &attributes, no_flags); emit_arith_operand(0x81, rax, src, imm32); } @@ -1416,7 +1400,7 @@ void Assembler::eaddl(Register dst, Address src1, Register src2, bool no_flags) InstructionMark im(this); InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); attributes.set_address_attributes(/* tuple_type */ EVEX_NOSCALE, /* input_size_in_bits */ EVEX_32bit); - evex_prefix_ndd(src1, dst->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags); + eevex_prefix_ndd(src1, dst->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C /* MAP4 */, &attributes, no_flags); emit_int8(0x01); emit_operand(src2, src1, 0); } @@ -1427,9 +1411,7 @@ void Assembler::addl(Register dst, int32_t imm32) { } void Assembler::eaddl(Register dst, Register src, int32_t imm32, bool no_flags) { - InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); - (void) evex_prefix_and_encode_ndd(0, dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags); - emit_arith_ndd(0x81, 0xC0, src, imm32); + emit_eevex_prefix_or_demote_arith_ndd(dst, src, imm32, VEX_SIMD_NONE, VEX_OPCODE_0F_3C /* MAP4 */, EVEX_32bit, 0x81, 0xC0, no_flags); } void Assembler::addl(Register dst, Address src) { @@ -1441,11 +1423,7 @@ void Assembler::addl(Register dst, Address src) { void Assembler::eaddl(Register dst, Register src1, Address src2, bool no_flags) { InstructionMark im(this); - InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); - attributes.set_address_attributes(/* tuple_type */ EVEX_NOSCALE, /* input_size_in_bits */ EVEX_32bit); - evex_prefix_ndd(src2, dst->encoding(), src1->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags); - emit_int8(0x03); - emit_operand(src1, src2, 0); + emit_eevex_or_demote(dst, src1, src2, VEX_SIMD_NONE, VEX_OPCODE_0F_3C /* MAP4 */, EVEX_32bit, 0x03, no_flags); } void Assembler::addl(Register dst, Register src) { @@ -1457,7 +1435,7 @@ void Assembler::eaddl(Register dst, Register src1, Register src2, bool no_flags) InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); // NDD shares its encoding bits with NDS bits for regular EVEX instruction. // Therefore, DST is passed as the second argument to minimize changes in the leaf level routine. - (void)evex_prefix_and_encode_ndd(src1->encoding(), dst->encoding(), src2->encoding(), VEX_SIMD_NONE, /* MAP4 */VEX_OPCODE_0F_3C, &attributes, no_flags); + (void)emit_eevex_prefix_or_demote_ndd(src1->encoding(), dst->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C /* MAP4 */, &attributes, no_flags); emit_arith(0x03, 0xC0, src1, src2); } @@ -1647,7 +1625,7 @@ void Assembler::eandl(Register dst, Address src, int32_t imm32, bool no_flags) { InstructionMark im(this); InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); attributes.set_address_attributes(/* tuple_type */ EVEX_NOSCALE, /* input_size_in_bits */ EVEX_32bit); - evex_prefix_ndd(src, dst->encoding(), 0, VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags); + eevex_prefix_ndd(src, dst->encoding(), 0, VEX_SIMD_NONE, VEX_OPCODE_0F_3C /* MAP4 */, &attributes, no_flags); emit_arith_operand(0x81, rsp, src, imm32); } @@ -1657,9 +1635,7 @@ void Assembler::andl(Register dst, int32_t imm32) { } void Assembler::eandl(Register dst, Register src, int32_t imm32, bool no_flags) { - InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); - (void) evex_prefix_and_encode_ndd(0, dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags); - emit_arith_ndd(0x81, 0xE0, src, imm32); + emit_eevex_prefix_or_demote_arith_ndd(dst, src, imm32, VEX_SIMD_NONE, VEX_OPCODE_0F_3C /* MAP4 */, EVEX_32bit, 0x81, 0xE0, no_flags); } void Assembler::andl(Address dst, Register src) { @@ -1678,11 +1654,7 @@ void Assembler::andl(Register dst, Address src) { void Assembler::eandl(Register dst, Register src1, Address src2, bool no_flags) { InstructionMark im(this); - InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); - attributes.set_address_attributes(/* tuple_type */ EVEX_NOSCALE, /* input_size_in_bits */ EVEX_32bit); - evex_prefix_ndd(src2, dst->encoding(), src1->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags); - emit_int8(0x23); - emit_operand(src1, src2, 0); + emit_eevex_or_demote(dst, src1, src2, VEX_SIMD_NONE, VEX_OPCODE_0F_3C /* MAP4 */, EVEX_32bit, 0x23, no_flags); } void Assembler::andl(Register dst, Register src) { @@ -1694,7 +1666,7 @@ void Assembler::eandl(Register dst, Register src1, Register src2, bool no_flags) InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); // NDD shares its encoding bits with NDS bits for regular EVEX instruction. // Therefore, DST is passed as the second argument to minimize changes in the leaf level routine. - (void) evex_prefix_and_encode_ndd(src1->encoding(), dst->encoding(), src2->encoding(), VEX_SIMD_NONE, /* MAP4 */VEX_OPCODE_0F_3C, &attributes, no_flags); + (void) emit_eevex_prefix_or_demote_ndd(src1->encoding(), dst->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C /* MAP4 */, &attributes, no_flags); emit_arith(0x23, 0xC0, src1, src2); } @@ -1841,9 +1813,7 @@ void Assembler::cmovl(Condition cc, Register dst, Register src) { } void Assembler::ecmovl(Condition cc, Register dst, Register src1, Register src2) { - InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); - int encode = evex_prefix_and_encode_ndd(src1->encoding(), dst->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes); - emit_int16((0x40 | cc), (0xC0 | encode)); + emit_eevex_or_demote(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C /* MAP4 */, EVEX_32bit, 0x40 | cc, false /* no_flags */, true /* is_map1 */, true /* swap */); } void Assembler::cmovl(Condition cc, Register dst, Address src) { @@ -1855,11 +1825,7 @@ void Assembler::cmovl(Condition cc, Register dst, Address src) { void Assembler::ecmovl(Condition cc, Register dst, Register src1, Address src2) { InstructionMark im(this); - InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); - attributes.set_address_attributes(/* tuple_type */ EVEX_NOSCALE, /* input_size_in_bits */ EVEX_32bit); - evex_prefix_ndd(src2, dst->encoding(), src1->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes); - emit_int8((0x40 | cc)); - emit_operand(src1, src2, 0); + emit_eevex_or_demote(dst, src1, src2, VEX_SIMD_NONE, VEX_OPCODE_0F_3C /* MAP4 */, EVEX_32bit, (0x40 | cc) , false /* no_flags */, true /* is_map1 */); } void Assembler::cmpb(Address dst, Register reg) { @@ -2029,7 +1995,7 @@ void Assembler::crc32(Register crc, Register v, int8_t sizeInBytes) { assert(VM_Version::supports_sse4_2(), ""); if (needs_eevex(crc, v)) { InstructionAttr attributes(AVX_128bit, /* rex_w */ sizeInBytes == 8, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); - int encode = vex_prefix_and_encode(crc->encoding(), 0, v->encoding(), sizeInBytes == 2 ? VEX_SIMD_66 : VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, true); + int encode = vex_prefix_and_encode(crc->encoding(), 0, v->encoding(), sizeInBytes == 2 ? VEX_SIMD_66 : VEX_SIMD_NONE, VEX_OPCODE_0F_3C /* MAP4 */, &attributes, true); emit_int16(sizeInBytes == 1 ? (unsigned char)0xF0 : (unsigned char)0xF1, (0xC0 | encode)); } else { int8_t w = 0x01; @@ -2076,7 +2042,7 @@ void Assembler::crc32(Register crc, Address adr, int8_t sizeInBytes) { if (needs_eevex(crc, adr.base(), adr.index())) { InstructionAttr attributes(AVX_128bit, /* vex_w */ sizeInBytes == 8, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); attributes.set_address_attributes(/* tuple_type */ EVEX_NOSCALE, /* input_size_in_bits */ EVEX_64bit); - vex_prefix(adr, 0, crc->encoding(), sizeInBytes == 2 ? VEX_SIMD_66 : VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes); + vex_prefix(adr, 0, crc->encoding(), sizeInBytes == 2 ? VEX_SIMD_66 : VEX_SIMD_NONE, VEX_OPCODE_0F_3C /* MAP4 */, &attributes); emit_int8(sizeInBytes == 1 ? (unsigned char)0xF0 : (unsigned char)0xF1); emit_operand(crc, adr, 0); } else { @@ -2473,7 +2439,7 @@ void Assembler::edecl(Register dst, Address src, bool no_flags) { InstructionMark im(this); InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); attributes.set_address_attributes(/* tuple_type */ EVEX_NOSCALE, /* input_size_in_bits */ EVEX_32bit); - evex_prefix_ndd(src, dst->encoding(), 0, VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags); + eevex_prefix_ndd(src, dst->encoding(), 0, VEX_SIMD_NONE, VEX_OPCODE_0F_3C /* MAP4 */, &attributes, no_flags); emit_int8((unsigned char)0xFF); emit_operand(rcx, src, 0); } @@ -2521,7 +2487,7 @@ void Assembler::idivl(Register src) { void Assembler::eidivl(Register src, bool no_flags) { // Signed InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); - int encode = evex_prefix_and_encode_nf(0, 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags); + int encode = eevex_prefix_and_encode_nf(0, 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C /* MAP4 */, &attributes, no_flags); emit_int16((unsigned char)0xF7, (0xF8 | encode)); } @@ -2532,7 +2498,7 @@ void Assembler::divl(Register src) { // Unsigned void Assembler::edivl(Register src, bool no_flags) { // Unsigned InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); - int encode = evex_prefix_and_encode_nf(0, 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags); + int encode = eevex_prefix_and_encode_nf(0, 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C /* MAP4 */, &attributes, no_flags); emit_int16((unsigned char)0xF7, (0xF0 | encode)); } @@ -2543,7 +2509,7 @@ void Assembler::imull(Register src) { void Assembler::eimull(Register src, bool no_flags) { InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); - int encode = evex_prefix_and_encode_nf(0, 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags); + int encode = eevex_prefix_and_encode_nf(0, 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C /* MAP4 */, &attributes, no_flags); emit_int16((unsigned char)0xF7, (0xE8 | encode)); } @@ -2553,9 +2519,7 @@ void Assembler::imull(Register dst, Register src) { } void Assembler::eimull(Register dst, Register src1, Register src2, bool no_flags) { - InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); - int encode = evex_prefix_and_encode_ndd(src1->encoding(), dst->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags); - emit_int16((unsigned char)0xAF, (0xC0 | encode)); + emit_eevex_or_demote(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C /* MAP4 */, EVEX_32bit, 0xAF, no_flags, true /* is_map1 */, true /* swap */); } void Assembler::imull(Register dst, Address src, int32_t value) { @@ -2576,7 +2540,7 @@ void Assembler::eimull(Register dst, Address src, int32_t value, bool no_flags) InstructionMark im(this); InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); attributes.set_address_attributes(/* tuple_type */ EVEX_NOSCALE, /* input_size_in_bits */ EVEX_32bit); - evex_prefix_nf(src, 0, dst->encoding(), VEX_SIMD_NONE, /* MAP4 */VEX_OPCODE_0F_3C, &attributes, no_flags); + eevex_prefix_nf(src, 0, dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C /* MAP4 */, &attributes, no_flags); if (is8bit(value)) { emit_int8((unsigned char)0x6B); emit_operand(dst, src, 1); @@ -2600,7 +2564,7 @@ void Assembler::imull(Register dst, Register src, int value) { void Assembler::eimull(Register dst, Register src, int value, bool no_flags) { InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); - int encode = evex_prefix_and_encode_nf(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags); + int encode = eevex_prefix_and_encode_nf(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C /* MAP4 */, &attributes, no_flags); if (is8bit(value)) { emit_int24(0x6B, (0xC0 | encode), value & 0xFF); } else { @@ -2618,11 +2582,7 @@ void Assembler::imull(Register dst, Address src) { void Assembler::eimull(Register dst, Register src1, Address src2, bool no_flags) { InstructionMark im(this); - InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); - attributes.set_address_attributes(/* tuple_type */ EVEX_NOSCALE, /* input_size_in_bits */ EVEX_32bit); - evex_prefix_ndd(src2, dst->encoding(), src1->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags); - emit_int8((unsigned char)0xAF); - emit_operand(src1, src2, 0); + emit_eevex_or_demote(dst, src1, src2, VEX_SIMD_NONE, VEX_OPCODE_0F_3C /* MAP4 */, EVEX_32bit, (unsigned char)0xAF, no_flags, true /* is_map1 */); } void Assembler::incl(Address dst) { @@ -2638,7 +2598,7 @@ void Assembler::eincl(Register dst, Address src, bool no_flags) { InstructionMark im(this); InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); attributes.set_address_attributes(/* tuple_type */ EVEX_NOSCALE, /* input_size_in_bits */ EVEX_32bit); - evex_prefix_ndd(src, dst->encoding(), 0, VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags); + eevex_prefix_ndd(src, dst->encoding(), 0, VEX_SIMD_NONE, VEX_OPCODE_0F_3C /* MAP4 */, &attributes, no_flags); emit_int8((unsigned char)0xFF); emit_operand(rax, src, 0); } @@ -2830,7 +2790,7 @@ void Assembler::lzcntl(Register dst, Register src) { void Assembler::elzcntl(Register dst, Register src, bool no_flags) { assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR"); InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); - int encode = evex_prefix_and_encode_nf(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags); + int encode = eevex_prefix_and_encode_nf(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C /* MAP4 */, &attributes, no_flags); emit_int16((unsigned char)0xF5, (0xC0 | encode)); } @@ -2848,7 +2808,7 @@ void Assembler::elzcntl(Register dst, Address src, bool no_flags) { InstructionMark im(this); InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); attributes.set_address_attributes(/* tuple_type */ EVEX_NOSCALE, /* input_size_in_bits */ EVEX_32bit); - evex_prefix_nf(src, 0, dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags); + eevex_prefix_nf(src, 0, dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C /* MAP4 */, &attributes, no_flags); emit_int8((unsigned char)0xF5); emit_operand(dst, src, 0); } @@ -4066,7 +4026,7 @@ void Assembler::emull(Address src, bool no_flags) { InstructionMark im(this); InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); attributes.set_address_attributes(/* tuple_type */ EVEX_NOSCALE, /* input_size_in_bits */ EVEX_32bit); - evex_prefix_nf(src, 0, 0, VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags); + eevex_prefix_nf(src, 0, 0, VEX_SIMD_NONE, VEX_OPCODE_0F_3C /* MAP4 */, &attributes, no_flags); emit_int8((unsigned char)0xF7); emit_operand(rsp, src, 0); } @@ -4078,7 +4038,7 @@ void Assembler::mull(Register src) { void Assembler::emull(Register src, bool no_flags) { InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); - int encode = evex_prefix_and_encode_nf(0, 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags); + int encode = eevex_prefix_and_encode_nf(0, 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C /* MAP4 */, &attributes, no_flags); emit_int16((unsigned char)0xF7, (0xE0 | encode)); } @@ -4121,7 +4081,7 @@ void Assembler::negl(Register dst) { void Assembler::enegl(Register dst, Register src, bool no_flags) { InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); - int encode = evex_prefix_and_encode_ndd(0, dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags); + int encode = emit_eevex_prefix_or_demote_ndd(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C /* MAP4 */, &attributes, no_flags); emit_int16((unsigned char)0xF7, (0xD8 | encode)); } @@ -4136,7 +4096,7 @@ void Assembler::enegl(Register dst, Address src, bool no_flags) { InstructionMark im(this); InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); attributes.set_address_attributes(/* tuple_type */ EVEX_NOSCALE, /* input_size_in_bits */ EVEX_32bit); - evex_prefix_ndd(src, dst->encoding(), 0, VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags); + eevex_prefix_ndd(src, dst->encoding(), 0, VEX_SIMD_NONE, VEX_OPCODE_0F_3C /* MAP4 */, &attributes, no_flags); emit_int8((unsigned char)0xF7); emit_operand(as_Register(3), src, 0); } @@ -4454,7 +4414,7 @@ void Assembler::notl(Register dst) { void Assembler::enotl(Register dst, Register src) { InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); - int encode = evex_prefix_and_encode_ndd(0, dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes); + int encode = emit_eevex_prefix_or_demote_ndd(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C /* MAP4 */, &attributes); emit_int16((unsigned char)0xF7, (0xD0 | encode)); } @@ -4462,7 +4422,7 @@ void Assembler::eorw(Register dst, Register src1, Register src2, bool no_flags) InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); // NDD shares its encoding bits with NDS bits for regular EVEX instruction. // Therefore, DST is passed as the second argument to minimize changes in the leaf level routine. - (void) evex_prefix_and_encode_ndd(src1->encoding(), dst->encoding(), src2->encoding(), VEX_SIMD_66, /* MAP4 */VEX_OPCODE_0F_3C, &attributes, no_flags); + (void) emit_eevex_prefix_or_demote_ndd(src1->encoding(), dst->encoding(), src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3C /* MAP4 */, &attributes, no_flags); emit_arith(0x0B, 0xC0, src1, src2); } @@ -4476,7 +4436,7 @@ void Assembler::eorl(Register dst, Address src, int32_t imm32, bool no_flags) { InstructionMark im(this); InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); attributes.set_address_attributes(/* tuple_type */ EVEX_NOSCALE, /* input_size_in_bits */ EVEX_32bit); - evex_prefix_ndd(src, dst->encoding(), 0, VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags); + eevex_prefix_ndd(src, dst->encoding(), 0, VEX_SIMD_NONE, VEX_OPCODE_0F_3C /* MAP4 */, &attributes, no_flags); emit_arith_operand(0x81, rcx, src, imm32); } @@ -4486,9 +4446,7 @@ void Assembler::orl(Register dst, int32_t imm32) { } void Assembler::eorl(Register dst, Register src, int32_t imm32, bool no_flags) { - InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); - evex_prefix_and_encode_ndd(0, dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags); - emit_arith_ndd(0x81, 0xC8, src, imm32); + emit_eevex_prefix_or_demote_arith_ndd(dst, src, imm32, VEX_SIMD_NONE, VEX_OPCODE_0F_3C /* MAP4 */, EVEX_32bit, 0x81, 0xC8, no_flags); } void Assembler::orl(Register dst, Address src) { @@ -4500,11 +4458,7 @@ void Assembler::orl(Register dst, Address src) { void Assembler::eorl(Register dst, Register src1, Address src2, bool no_flags) { InstructionMark im(this); - InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); - attributes.set_address_attributes(/* tuple_type */ EVEX_NOSCALE, /* input_size_in_bits */ EVEX_64bit); - evex_prefix_ndd(src2, dst->encoding(), src1->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags); - emit_int8(0x0B); - emit_operand(src1, src2, 0); + emit_eevex_or_demote(dst, src1, src2, VEX_SIMD_NONE, VEX_OPCODE_0F_3C /* MAP4 */, EVEX_32bit, 0x0B, no_flags); } void Assembler::orl(Register dst, Register src) { @@ -4516,7 +4470,7 @@ void Assembler::eorl(Register dst, Register src1, Register src2, bool no_flags) InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); // NDD shares its encoding bits with NDS bits for regular EVEX instruction. // Therefore, DST is passed as the second argument to minimize changes in the leaf level routine. - (void) evex_prefix_and_encode_ndd(src1->encoding(), dst->encoding(), src2->encoding(), VEX_SIMD_NONE, /* MAP4 */VEX_OPCODE_0F_3C, &attributes, no_flags); + (void) emit_eevex_prefix_or_demote_ndd(src1->encoding(), dst->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C /* MAP4 */, &attributes, no_flags); emit_arith(0x0B, 0xC0, src1, src2); } @@ -4531,7 +4485,7 @@ void Assembler::eorl(Register dst, Address src1, Register src2, bool no_flags) { InstructionMark im(this); InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); attributes.set_address_attributes(/* tuple_type */ EVEX_NOSCALE, /* input_size_in_bits */ EVEX_32bit); - evex_prefix_ndd(src1, dst->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags); + eevex_prefix_ndd(src1, dst->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C /* MAP4 */, &attributes, no_flags); emit_int8(0x09); emit_operand(src2, src1, 0); } @@ -4548,7 +4502,7 @@ void Assembler::eorb(Register dst, Address src, int imm8, bool no_flags) { InstructionMark im(this); InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); attributes.set_address_attributes(/* tuple_type */ EVEX_NOSCALE, /* input_size_in_bits */ EVEX_8bit); - evex_prefix_ndd(src, dst->encoding(), 0, VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags); + eevex_prefix_ndd(src, dst->encoding(), 0, VEX_SIMD_NONE, VEX_OPCODE_0F_3C /* MAP4 */, &attributes, no_flags); emit_int8((unsigned char)0x80); emit_operand(rcx, src, 1); emit_int8(imm8); @@ -4565,7 +4519,7 @@ void Assembler::eorb(Register dst, Address src1, Register src2, bool no_flags) { InstructionMark im(this); InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); attributes.set_address_attributes(/* tuple_type */ EVEX_NOSCALE, /* input_size_in_bits */ EVEX_8bit); - evex_prefix_ndd(src1, dst->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags); + eevex_prefix_ndd(src1, dst->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C /* MAP4 */, &attributes, no_flags); emit_int8(0x08); emit_operand(src2, src1, 0); } @@ -5693,7 +5647,7 @@ void Assembler::epopcntl(Register dst, Address src, bool no_flags) { InstructionMark im(this); InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); attributes.set_address_attributes(/* tuple_type */ EVEX_NOSCALE, /* input_size_in_bits */ EVEX_32bit); - evex_prefix_nf(src, 0, dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags); + eevex_prefix_nf(src, 0, dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C /* MAP4 */, &attributes, no_flags); emit_int8((unsigned char)0x88); emit_operand(dst, src, 0); } @@ -5708,7 +5662,7 @@ void Assembler::popcntl(Register dst, Register src) { void Assembler::epopcntl(Register dst, Register src, bool no_flags) { assert(VM_Version::supports_popcnt(), "must support"); InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); - int encode = evex_prefix_and_encode_nf(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags); + int encode = eevex_prefix_and_encode_nf(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C /* MAP4 */, &attributes, no_flags); emit_int16((unsigned char)0x88, (0xC0 | encode)); } @@ -6259,7 +6213,7 @@ void Assembler::rcll(Register dst, int imm8) { void Assembler::ercll(Register dst, Register src, int imm8) { assert(isShiftCount(imm8), "illegal shift count"); InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); - int encode = evex_prefix_and_encode_ndd(0, dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes); + int encode = emit_eevex_prefix_or_demote_ndd(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C /* MAP4 */, &attributes); if (imm8 == 1) { emit_int16((unsigned char)0xD1, (0xD0 | encode)); } else { @@ -6342,7 +6296,7 @@ void Assembler::roll(Register dst, int imm8) { void Assembler::eroll(Register dst, Register src, int imm8, bool no_flags) { assert(isShiftCount(imm8), "illegal shift count"); InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); - int encode = evex_prefix_and_encode_ndd(0, dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags); + int encode = emit_eevex_prefix_or_demote_ndd(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C /* MAP4 */, &attributes, no_flags); if (imm8 == 1) { emit_int16((unsigned char)0xD1, (0xC0 | encode)); } else { @@ -6357,7 +6311,7 @@ void Assembler::roll(Register dst) { void Assembler::eroll(Register dst, Register src, bool no_flags) { InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); - int encode = evex_prefix_and_encode_ndd(0, dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags); + int encode = emit_eevex_prefix_or_demote_ndd(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C /* MAP4 */, &attributes, no_flags); emit_int16((unsigned char)0xD3, (0xC0 | encode)); } @@ -6374,7 +6328,7 @@ void Assembler::rorl(Register dst, int imm8) { void Assembler::erorl(Register dst, Register src, int imm8, bool no_flags) { assert(isShiftCount(imm8), "illegal shift count"); InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); - int encode = evex_prefix_and_encode_ndd(0, dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags); + int encode = emit_eevex_prefix_or_demote_ndd(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C /* MAP4 */, &attributes, no_flags); if (imm8 == 1) { emit_int16((unsigned char)0xD1, (0xC8 | encode)); } else { @@ -6389,7 +6343,7 @@ void Assembler::rorl(Register dst) { void Assembler::erorl(Register dst, Register src, bool no_flags) { InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); - int encode = evex_prefix_and_encode_ndd(0, dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags); + int encode = emit_eevex_prefix_or_demote_ndd(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C /* MAP4 */, &attributes, no_flags); emit_int16((unsigned char)0xD3, (0xC8 | encode)); } @@ -6400,7 +6354,7 @@ void Assembler::rorq(Register dst) { void Assembler::erorq(Register dst, Register src, bool no_flags) { InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); - int encode = evex_prefix_and_encode_ndd(0, dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags); + int encode = emit_eevex_prefix_or_demote_ndd(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C /* MAP4 */, &attributes, no_flags, true /* use_prefixq */); emit_int16((unsigned char)0xD3, (0xC8 | encode)); } @@ -6417,7 +6371,7 @@ void Assembler::rorq(Register dst, int imm8) { void Assembler::erorq(Register dst, Register src, int imm8, bool no_flags) { assert(isShiftCount(imm8), "illegal shift count"); InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); - int encode = evex_prefix_and_encode_ndd(0, dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags); + int encode = emit_eevex_prefix_or_demote_ndd(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C /* MAP4 */, &attributes, no_flags, true /* use_prefixq */); if (imm8 == 1) { emit_int16((unsigned char)0xD1, (0xC8 | encode)); } else { @@ -6432,7 +6386,7 @@ void Assembler::rolq(Register dst) { void Assembler::erolq(Register dst, Register src, bool no_flags) { InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); - int encode = evex_prefix_and_encode_ndd(0, dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags); + int encode = emit_eevex_prefix_or_demote_ndd(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C /* MAP4 */, &attributes, no_flags, true /* use_prefixq */); emit_int16((unsigned char)0xD3, (0xC0 | encode)); } @@ -6449,7 +6403,7 @@ void Assembler::rolq(Register dst, int imm8) { void Assembler::erolq(Register dst, Register src, int imm8, bool no_flags) { assert(isShiftCount(imm8), "illegal shift count"); InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); - int encode = evex_prefix_and_encode_ndd(0, dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags); + int encode = emit_eevex_prefix_or_demote_ndd(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C /* MAP4 */, &attributes, no_flags, true /* use_prefixq */); if (imm8 == 1) { emit_int16((unsigned char)0xD1, (0xC0 | encode)); } else { @@ -6477,7 +6431,7 @@ void Assembler::esall(Register dst, Address src, int imm8, bool no_flags) { assert(isShiftCount(imm8), "illegal shift count"); InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); attributes.set_address_attributes(/* tuple_type */ EVEX_NOSCALE, /* input_size_in_bits */ EVEX_32bit); - evex_prefix_ndd(src, dst->encoding(), 0, VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags); + eevex_prefix_ndd(src, dst->encoding(), 0, VEX_SIMD_NONE, VEX_OPCODE_0F_3C /* MAP4 */, &attributes, no_flags); if (imm8 == 1) { emit_int8((unsigned char)0xD1); emit_operand(as_Register(4), src, 0); @@ -6500,7 +6454,7 @@ void Assembler::esall(Register dst, Address src, bool no_flags) { InstructionMark im(this); InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); attributes.set_address_attributes(/* tuple_type */ EVEX_NOSCALE, /* input_size_in_bits */ EVEX_32bit); - evex_prefix_ndd(src, dst->encoding(), 0, VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags); + eevex_prefix_ndd(src, dst->encoding(), 0, VEX_SIMD_NONE, VEX_OPCODE_0F_3C /* MAP4 */, &attributes, no_flags); emit_int8((unsigned char)0xD3); emit_operand(as_Register(4), src, 0); } @@ -6518,7 +6472,7 @@ void Assembler::sall(Register dst, int imm8) { void Assembler::esall(Register dst, Register src, int imm8, bool no_flags) { assert(isShiftCount(imm8), "illegal shift count"); InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); - int encode = evex_prefix_and_encode_ndd(0, dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags); + int encode = emit_eevex_prefix_or_demote_ndd(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C /* MAP4 */, &attributes, no_flags); if (imm8 == 1) { emit_int16((unsigned char)0xD1, (0xE0 | encode)); } else { @@ -6533,7 +6487,7 @@ void Assembler::sall(Register dst) { void Assembler::esall(Register dst, Register src, bool no_flags) { InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); - int encode = evex_prefix_and_encode_ndd(0, dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags); + int encode = emit_eevex_prefix_or_demote_ndd(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C /* MAP4 */, &attributes, no_flags); emit_int16((unsigned char)0xD3, (0xE0 | encode)); } @@ -6557,7 +6511,7 @@ void Assembler::esarl(Register dst, Address src, int imm8, bool no_flags) { InstructionMark im(this); InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); attributes.set_address_attributes(/* tuple_type */ EVEX_NOSCALE, /* input_size_in_bits */ EVEX_32bit); - evex_prefix_ndd(src, dst->encoding(), 0, VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags); + eevex_prefix_ndd(src, dst->encoding(), 0, VEX_SIMD_NONE, VEX_OPCODE_0F_3C /* MAP4 */, &attributes, no_flags); if (imm8 == 1) { emit_int8((unsigned char)0xD1); emit_operand(as_Register(7), src, 0); @@ -6580,7 +6534,7 @@ void Assembler::esarl(Register dst, Address src, bool no_flags) { InstructionMark im(this); InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); attributes.set_address_attributes(/* tuple_type */ EVEX_NOSCALE, /* input_size_in_bits */ EVEX_32bit); - evex_prefix_ndd(src, dst->encoding(), 0, VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags); + eevex_prefix_ndd(src, dst->encoding(), 0, VEX_SIMD_NONE, VEX_OPCODE_0F_3C /* MAP4 */, &attributes, no_flags); emit_int8((unsigned char)0xD3); emit_operand(as_Register(7), src, 0); } @@ -6598,7 +6552,7 @@ void Assembler::sarl(Register dst, int imm8) { void Assembler::esarl(Register dst, Register src, int imm8, bool no_flags) { assert(isShiftCount(imm8), "illegal shift count"); InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); - int encode = evex_prefix_and_encode_ndd(0, dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags); + int encode = emit_eevex_prefix_or_demote_ndd(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C /* MAP4 */, &attributes, no_flags); if (imm8 == 1) { emit_int16((unsigned char)0xD1, (0xF8 | encode)); } else { @@ -6613,7 +6567,7 @@ void Assembler::sarl(Register dst) { void Assembler::esarl(Register dst, Register src, bool no_flags) { InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); - int encode = evex_prefix_and_encode_ndd(0, dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags); + int encode = emit_eevex_prefix_or_demote_ndd(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C /* MAP4 */, &attributes, no_flags); emit_int16((unsigned char)0xD3, (0xF8 | encode)); } @@ -6754,7 +6708,7 @@ void Assembler::shll(Register dst, int imm8) { void Assembler::eshll(Register dst, Register src, int imm8, bool no_flags) { assert(isShiftCount(imm8), "illegal shift count"); InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); - int encode = evex_prefix_and_encode_ndd(0, dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags); + int encode = emit_eevex_prefix_or_demote_ndd(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C /* MAP4 */, &attributes, no_flags); if (imm8 == 1 ) { emit_int16((unsigned char)0xD1, (0xE0 | encode)); } else { @@ -6769,7 +6723,7 @@ void Assembler::shll(Register dst) { void Assembler::eshll(Register dst, Register src, bool no_flags) { InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); - int encode = evex_prefix_and_encode_ndd(0, dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags); + int encode = emit_eevex_prefix_or_demote_ndd(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C /* MAP4 */, &attributes, no_flags); emit_int16((unsigned char)0xD3, (0xE0 | encode)); } @@ -6787,7 +6741,7 @@ void Assembler::shrl(Register dst, int imm8) { void Assembler::eshrl(Register dst, Register src, int imm8, bool no_flags) { assert(isShiftCount(imm8), "illegal shift count"); InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); - int encode = evex_prefix_and_encode_ndd(0, dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags); + int encode = emit_eevex_prefix_or_demote_ndd(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C /* MAP4 */, &attributes, no_flags); if (imm8 == 1) { emit_int16((unsigned char)0xD1, (0xE8 | encode)); } @@ -6803,7 +6757,7 @@ void Assembler::shrl(Register dst) { void Assembler::eshrl(Register dst, Register src, bool no_flags) { InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); - int encode = evex_prefix_and_encode_ndd(0, dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags); + int encode = emit_eevex_prefix_or_demote_ndd(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C /* MAP4 */, &attributes, no_flags); emit_int16((unsigned char)0xD3, (0xE8 | encode)); } @@ -6818,7 +6772,7 @@ void Assembler::eshrl(Register dst, Address src, bool no_flags) { InstructionMark im(this); InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); attributes.set_address_attributes(/* tuple_type */ EVEX_NOSCALE, /* input_size_in_bits */ EVEX_32bit); - evex_prefix_ndd(src, dst->encoding(), 0, VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags); + eevex_prefix_ndd(src, dst->encoding(), 0, VEX_SIMD_NONE, VEX_OPCODE_0F_3C /* MAP4 */, &attributes, no_flags); emit_int8((unsigned char)0xD3); emit_operand(as_Register(5), src, 0); } @@ -6843,7 +6797,7 @@ void Assembler::eshrl(Register dst, Address src, int imm8, bool no_flags) { assert(isShiftCount(imm8), "illegal shift count"); InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); attributes.set_address_attributes(/* tuple_type */ EVEX_NOSCALE, /* input_size_in_bits */ EVEX_32bit); - evex_prefix_ndd(src, dst->encoding(), 0, VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags); + eevex_prefix_ndd(src, dst->encoding(), 0, VEX_SIMD_NONE, VEX_OPCODE_0F_3C /* MAP4 */, &attributes, no_flags); if (imm8 == 1) { emit_int8((unsigned char)0xD1); emit_operand(as_Register(5), src, 0); @@ -6861,11 +6815,7 @@ void Assembler::shldl(Register dst, Register src) { } void Assembler::eshldl(Register dst, Register src1, Register src2, bool no_flags) { - InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); - // NDD shares its encoding bits with NDS bits for regular EVEX instruction. - // Therefore, DST is passed as the second argument to minimize changes in the leaf level routine. - int encode = evex_prefix_and_encode_ndd(src2->encoding(), dst->encoding(), src1->encoding(), VEX_SIMD_NONE, /* MAP4 */VEX_OPCODE_0F_3C, &attributes, no_flags); - emit_int16(0xA5, (0xC0 | encode)); + emit_eevex_or_demote(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C /* MAP4 */, EVEX_32bit, 0xA5, no_flags, true /* is_map1 */); } void Assembler::shldl(Register dst, Register src, int8_t imm8) { @@ -6874,11 +6824,7 @@ void Assembler::shldl(Register dst, Register src, int8_t imm8) { } void Assembler::eshldl(Register dst, Register src1, Register src2, int8_t imm8, bool no_flags) { - InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); - // NDD shares its encoding bits with NDS bits for regular EVEX instruction. - // Therefore, DST is passed as the second argument to minimize changes in the leaf level routine. - int encode = evex_prefix_and_encode_ndd(src2->encoding(), dst->encoding(), src1->encoding(), VEX_SIMD_NONE, /* MAP4 */VEX_OPCODE_0F_3C, &attributes, no_flags); - emit_int24(0x24, (0xC0 | encode), imm8); + emit_eevex_or_demote(dst->encoding(), src1->encoding(), src2->encoding(), imm8, VEX_SIMD_NONE, VEX_OPCODE_0F_3C /* MAP4 */, EVEX_32bit, 0x24, no_flags, true /* is_map1 */); } void Assembler::shrdl(Register dst, Register src) { @@ -6887,11 +6833,7 @@ void Assembler::shrdl(Register dst, Register src) { } void Assembler::eshrdl(Register dst, Register src1, Register src2, bool no_flags) { - InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); - // NDD shares its encoding bits with NDS bits for regular EVEX instruction. - // Therefore, DST is passed as the second argument to minimize changes in the leaf level routine. - int encode = evex_prefix_and_encode_ndd(src2->encoding(), dst->encoding(), src1->encoding(), VEX_SIMD_NONE, /* MAP4 */VEX_OPCODE_0F_3C, &attributes, no_flags); - emit_int16(0xAD, (0xC0 | encode)); + emit_eevex_or_demote(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C /* MAP4 */, EVEX_32bit, 0xAD, no_flags, true /* is_map1 */); } void Assembler::shrdl(Register dst, Register src, int8_t imm8) { @@ -6900,11 +6842,7 @@ void Assembler::shrdl(Register dst, Register src, int8_t imm8) { } void Assembler::eshrdl(Register dst, Register src1, Register src2, int8_t imm8, bool no_flags) { - InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); - // NDD shares its encoding bits with NDS bits for regular EVEX instruction. - // Therefore, DST is passed as the second argument to minimize changes in the leaf level routine. - int encode = evex_prefix_and_encode_ndd(src2->encoding(), dst->encoding(), src1->encoding(), VEX_SIMD_NONE, /* MAP4 */VEX_OPCODE_0F_3C, &attributes, no_flags); - emit_int24(0x2C, (0xC0 | encode), imm8); + emit_eevex_or_demote(dst->encoding(), src1->encoding(), src2->encoding(), imm8, VEX_SIMD_NONE, VEX_OPCODE_0F_3C /* MAP4 */, EVEX_32bit, 0x2C, no_flags, true /* is_map1 */); } void Assembler::shldq(Register dst, Register src, int8_t imm8) { @@ -6913,11 +6851,7 @@ void Assembler::shldq(Register dst, Register src, int8_t imm8) { } void Assembler::eshldq(Register dst, Register src1, Register src2, int8_t imm8, bool no_flags) { - InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); - // NDD shares its encoding bits with NDS bits for regular EVEX instruction. - // Therefore, DST is passed as the second argument to minimize changes in the leaf level routine. - int encode = evex_prefix_and_encode_ndd(src2->encoding(), dst->encoding(), src1->encoding(), VEX_SIMD_NONE, /* MAP4 */VEX_OPCODE_0F_3C, &attributes, no_flags); - emit_int24(0x24, (0xC0 | encode), imm8); + emit_eevex_or_demote(dst->encoding(), src1->encoding(), src2->encoding(), imm8, VEX_SIMD_NONE, VEX_OPCODE_0F_3C /* MAP4 */, EVEX_64bit, 0x24, no_flags, true /* is_map1 */); } void Assembler::shrdq(Register dst, Register src, int8_t imm8) { @@ -6926,11 +6860,7 @@ void Assembler::shrdq(Register dst, Register src, int8_t imm8) { } void Assembler::eshrdq(Register dst, Register src1, Register src2, int8_t imm8, bool no_flags) { - InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); - // NDD shares its encoding bits with NDS bits for regular EVEX instruction. - // Therefore, DST is passed as the second argument to minimize changes in the leaf level routine. - int encode = evex_prefix_and_encode_ndd(src2->encoding(), dst->encoding(), src1->encoding(), VEX_SIMD_NONE, /* MAP4 */VEX_OPCODE_0F_3C, &attributes, no_flags); - emit_int24(0x2C, (0xC0 | encode), imm8); + emit_eevex_or_demote(dst->encoding(), src1->encoding(), src2->encoding(), imm8, VEX_SIMD_NONE, VEX_OPCODE_0F_3C /* MAP4 */, EVEX_64bit, 0x2C, no_flags, true /* is_map1 */); } // copies a single word from [esi] to [edi] @@ -7020,7 +6950,7 @@ void Assembler::esubl(Register dst, Address src, int32_t imm32, bool no_flags) { InstructionMark im(this); InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); attributes.set_address_attributes(/* tuple_type */ EVEX_NOSCALE, /* input_size_in_bits */ EVEX_32bit); - evex_prefix_ndd(src, dst->encoding(), 0, VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags); + eevex_prefix_ndd(src, dst->encoding(), 0, VEX_SIMD_NONE, VEX_OPCODE_0F_3C /* MAP4 */, &attributes, no_flags); emit_arith_operand(0x81, rbp, src, imm32); } @@ -7035,7 +6965,7 @@ void Assembler::esubl(Register dst, Address src1, Register src2, bool no_flags) InstructionMark im(this); InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); attributes.set_address_attributes(/* tuple_type */ EVEX_NOSCALE, /* input_size_in_bits */ EVEX_32bit); - evex_prefix_ndd(src1, dst->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags); + eevex_prefix_ndd(src1, dst->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C /* MAP4 */, &attributes, no_flags); emit_int8(0x29); emit_operand(src2, src1, 0); } @@ -7046,9 +6976,7 @@ void Assembler::subl(Register dst, int32_t imm32) { } void Assembler::esubl(Register dst, Register src, int32_t imm32, bool no_flags) { - InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); - (void) evex_prefix_and_encode_ndd(0, dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags); - emit_arith_ndd(0x81, 0xE8, src, imm32); + emit_eevex_prefix_or_demote_arith_ndd(dst, src, imm32, VEX_SIMD_NONE, VEX_OPCODE_0F_3C /* MAP4 */, EVEX_32bit, 0x81, 0xE8, no_flags); } // Force generation of a 4 byte immediate value even if it fits into 8bit @@ -7059,7 +6987,7 @@ void Assembler::subl_imm32(Register dst, int32_t imm32) { void Assembler::esubl_imm32(Register dst, Register src, int32_t imm32, bool no_flags) { InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); - (void) evex_prefix_and_encode_ndd(0, dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags); + (void) emit_eevex_prefix_or_demote_ndd(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C /* MAP4 */, &attributes, no_flags); emit_arith_imm32(0x81, 0xE8, src, imm32); } @@ -7072,11 +7000,7 @@ void Assembler::subl(Register dst, Address src) { void Assembler::esubl(Register dst, Register src1, Address src2, bool no_flags) { InstructionMark im(this); - InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); - attributes.set_address_attributes(/* tuple_type */ EVEX_NOSCALE, /* input_size_in_bits */ EVEX_32bit); - evex_prefix_ndd(src2, dst->encoding(), src1->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags); - emit_int8(0x2B); - emit_operand(src1, src2, 0); + emit_eevex_or_demote(dst, src1, src2, VEX_SIMD_NONE, VEX_OPCODE_0F_3C /* MAP4 */, EVEX_32bit, 0x2B, no_flags); } void Assembler::subl(Register dst, Register src) { @@ -7088,7 +7012,7 @@ void Assembler::esubl(Register dst, Register src1, Register src2, bool no_flags) InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); // NDD shares its encoding bits with NDS bits for regular EVEX instruction. // Therefore, DST is passed as the second argument to minimize changes in the leaf level routine. - (void) evex_prefix_and_encode_ndd(src1->encoding(), dst->encoding(), src2->encoding(), VEX_SIMD_NONE, /* MAP4 */VEX_OPCODE_0F_3C, &attributes, no_flags); + (void) emit_eevex_prefix_or_demote_ndd(src1->encoding(), dst->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C /* MAP4 */, &attributes, no_flags); emit_arith(0x2B, 0xC0, src1, src2); } @@ -7193,7 +7117,7 @@ void Assembler::tzcntl(Register dst, Register src) { void Assembler::etzcntl(Register dst, Register src, bool no_flags) { assert(VM_Version::supports_bmi1(), "tzcnt instruction not supported"); InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); - int encode = evex_prefix_and_encode_nf(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags); + int encode = eevex_prefix_and_encode_nf(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C /* MAP4 */, &attributes, no_flags); emit_int16((unsigned char)0xF4, (0xC0 | encode)); } @@ -7211,7 +7135,7 @@ void Assembler::etzcntl(Register dst, Address src, bool no_flags) { InstructionMark im(this); InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); attributes.set_address_attributes(/* tuple_type */ EVEX_NOSCALE, /* input_size_in_bits */ EVEX_32bit); - evex_prefix_nf(src, 0, dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags); + eevex_prefix_nf(src, 0, dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C /* MAP4 */, &attributes, no_flags); emit_int8((unsigned char)0xF4); emit_operand(dst, src, 0); } @@ -7226,7 +7150,7 @@ void Assembler::tzcntq(Register dst, Register src) { void Assembler::etzcntq(Register dst, Register src, bool no_flags) { assert(VM_Version::supports_bmi1(), "tzcnt instruction not supported"); InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); - int encode = evex_prefix_and_encode_nf(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags); + int encode = eevex_prefix_and_encode_nf(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C /* MAP4 */, &attributes, no_flags); emit_int16((unsigned char)0xF4, (0xC0 | encode)); } @@ -7244,7 +7168,7 @@ void Assembler::etzcntq(Register dst, Address src, bool no_flags) { InstructionMark im(this); InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); attributes.set_address_attributes(/* tuple_type */ EVEX_NOSCALE, /* input_size_in_bits */ EVEX_64bit); - evex_prefix_nf(src, 0, dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags); + eevex_prefix_nf(src, 0, dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C /* MAP4 */, &attributes, no_flags); emit_int8((unsigned char)0xF4); emit_operand(dst, src, 0); } @@ -7368,7 +7292,7 @@ void Assembler::exorl(Register dst, Address src, int32_t imm32, bool no_flags) { InstructionMark im(this); InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); attributes.set_address_attributes(/* tuple_type */ EVEX_NOSCALE, /* input_size_in_bits */ EVEX_32bit); - evex_prefix_ndd(src, dst->encoding(), 0, VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags); + eevex_prefix_ndd(src, dst->encoding(), 0, VEX_SIMD_NONE, VEX_OPCODE_0F_3C /* MAP4 */, &attributes, no_flags); emit_arith_operand(0x81, as_Register(6), src, imm32); } @@ -7378,9 +7302,7 @@ void Assembler::xorl(Register dst, int32_t imm32) { } void Assembler::exorl(Register dst, Register src, int32_t imm32, bool no_flags) { - InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); - evex_prefix_and_encode_ndd(0, dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags); - emit_arith_ndd(0x81, 0xF0, src, imm32); + emit_eevex_prefix_or_demote_arith_ndd(dst, src, imm32, VEX_SIMD_NONE, VEX_OPCODE_0F_3C /* MAP4 */, EVEX_32bit, 0x81, 0xF0, no_flags); } void Assembler::xorl(Register dst, Address src) { @@ -7392,11 +7314,7 @@ void Assembler::xorl(Register dst, Address src) { void Assembler::exorl(Register dst, Register src1, Address src2, bool no_flags) { InstructionMark im(this); - InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); - attributes.set_address_attributes(/* tuple_type */ EVEX_NOSCALE, /* input_size_in_bits */ EVEX_32bit); - evex_prefix_ndd(src2, dst->encoding(), src1->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags); - emit_int8(0x33); - emit_operand(src1, src2, 0); + emit_eevex_or_demote(dst, src1, src2, VEX_SIMD_NONE, VEX_OPCODE_0F_3C /* MAP4 */, EVEX_32bit, 0x33, no_flags); } void Assembler::xorl(Register dst, Register src) { @@ -7408,7 +7326,7 @@ void Assembler::exorl(Register dst, Register src1, Register src2, bool no_flags) InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); // NDD shares its encoding bits with NDS bits for regular EVEX instruction. // Therefore, DST is passed as the second argument to minimize changes in the leaf level routine. - (void) evex_prefix_and_encode_ndd(src1->encoding(), dst->encoding(), src2->encoding(), VEX_SIMD_NONE, /* MAP4 */VEX_OPCODE_0F_3C, &attributes, no_flags); + (void) emit_eevex_prefix_or_demote_ndd(src1->encoding(), dst->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C /* MAP4 */, &attributes, no_flags); emit_arith(0x33, 0xC0, src1, src2); } @@ -7423,7 +7341,7 @@ void Assembler::exorl(Register dst, Address src1, Register src2, bool no_flags) InstructionMark im(this); InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); attributes.set_address_attributes(/* tuple_type */ EVEX_NOSCALE, /* input_size_in_bits */ EVEX_32bit); - evex_prefix_ndd(src1, dst->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags); + eevex_prefix_ndd(src1, dst->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C /* MAP4 */, &attributes, no_flags); emit_int8(0x31); emit_operand(src2, src1, 0); } @@ -7437,11 +7355,7 @@ void Assembler::xorb(Register dst, Address src) { void Assembler::exorb(Register dst, Register src1, Address src2, bool no_flags) { InstructionMark im(this); - InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); - attributes.set_address_attributes(/* tuple_type */ EVEX_NOSCALE, /* input_size_in_bits */ EVEX_8bit); - evex_prefix_ndd(src2, dst->encoding(), src1->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags); - emit_int8(0x32); - emit_operand(src1, src2, 0); + emit_eevex_or_demote(dst, src1, src2, VEX_SIMD_NONE, VEX_OPCODE_0F_3C /* MAP4 */, EVEX_8bit, 0x32, no_flags); } void Assembler::xorb(Address dst, Register src) { @@ -7455,7 +7369,7 @@ void Assembler::exorb(Register dst, Address src1, Register src2, bool no_flags) InstructionMark im(this); InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); attributes.set_address_attributes(/* tuple_type */ EVEX_NOSCALE, /* input_size_in_bits */ EVEX_8bit); - evex_prefix_ndd(src1, dst->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags); + eevex_prefix_ndd(src1, dst->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C /* MAP4 */, &attributes, no_flags); emit_int8(0x30); emit_operand(src2, src1, 0); } @@ -7470,13 +7384,7 @@ void Assembler::xorw(Register dst, Address src) { void Assembler::exorw(Register dst, Register src1, Address src2, bool no_flags) { InstructionMark im(this); - InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); - attributes.set_address_attributes(/* tuple_type */ EVEX_NOSCALE, /* input_size_in_bits */ EVEX_16bit); - // NDD shares its encoding bits with NDS bits for regular EVEX instruction. - // Therefore, DST is passed as the second argument to minimize changes in the leaf level routine. - evex_prefix_ndd(src2, dst->encoding(), src1->encoding(), VEX_SIMD_66, /* MAP4 */VEX_OPCODE_0F_3C, &attributes, no_flags); - emit_int8(0x33); - emit_operand(src1, src2, 0); + emit_eevex_or_demote(dst, src1, src2, VEX_SIMD_66, VEX_OPCODE_0F_3C /* MAP4 */, EVEX_16bit, 0x33, no_flags); } // AVX 3-operands scalar float-point arithmetic instructions @@ -12977,12 +12885,35 @@ void Assembler::vex_prefix(Address adr, int nds_enc, int xreg_enc, VexSimdPrefix } } -void Assembler::evex_prefix_ndd(Address adr, int ndd_enc, int xreg_enc, VexSimdPrefix pre, VexOpcode opc, InstructionAttr *attributes, bool no_flags) { +void Assembler::eevex_prefix_ndd(Address adr, int ndd_enc, int xreg_enc, VexSimdPrefix pre, VexOpcode opc, InstructionAttr *attributes, bool no_flags) { attributes->set_is_evex_instruction(); vex_prefix(adr, ndd_enc, xreg_enc, pre, opc, attributes, /* nds_is_ndd */ true, no_flags); } -void Assembler::evex_prefix_nf(Address adr, int ndd_enc, int xreg_enc, VexSimdPrefix pre, VexOpcode opc, InstructionAttr *attributes, bool no_flags) { +void Assembler::emit_eevex_or_demote(Register dst, Register src1, Address src2, VexSimdPrefix pre, VexOpcode opc, + int size, int opcode_byte, bool no_flags, bool is_map1) { + if (is_demotable(no_flags, dst->encoding(), src1->encoding())) { + if (size == EVEX_64bit) { + emit_prefix_and_int8(get_prefixq(src2, dst, is_map1), opcode_byte); + } else { + // For 32-bit, 16-bit and 8-bit + if (size == EVEX_16bit) { + emit_int8(0x66); + } + prefix(src2, dst, false, is_map1); + emit_int8(opcode_byte); + } + } else { + bool vex_w = (size == EVEX_64bit) ? true : false; + InstructionAttr attributes(AVX_128bit, vex_w, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); + attributes.set_address_attributes(/* tuple_type */ EVEX_NOSCALE, size); + eevex_prefix_ndd(src2, dst->encoding(), src1->encoding(), pre, opc, &attributes, no_flags); + emit_int8(opcode_byte); + } + emit_operand(src1, src2, 0); +} + +void Assembler::eevex_prefix_nf(Address adr, int ndd_enc, int xreg_enc, VexSimdPrefix pre, VexOpcode opc, InstructionAttr *attributes, bool no_flags) { attributes->set_is_evex_instruction(); vex_prefix(adr, ndd_enc, xreg_enc, pre, opc, attributes, /* nds_is_ndd */ false, no_flags); } @@ -13044,18 +12975,98 @@ int Assembler::vex_prefix_and_encode(int dst_enc, int nds_enc, int src_enc, VexS return (((dst_enc & 7) << 3) | (src_enc & 7)); } -int Assembler::evex_prefix_and_encode_ndd(int dst_enc, int nds_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc, - InstructionAttr *attributes, bool no_flags) { +void Assembler::emit_eevex_or_demote(int dst_enc, int nds_enc, int src_enc, int8_t imm8, VexSimdPrefix pre, VexOpcode opc, + int size, int opcode_byte, bool no_flags, bool is_map1) { + bool is_prefixq = (size == EVEX_64bit) ? true : false; + if (is_demotable(no_flags, dst_enc, nds_enc)) { + int encode = is_prefixq ? prefixq_and_encode(src_enc, dst_enc, is_map1) : prefix_and_encode(src_enc, dst_enc, is_map1); + emit_opcode_prefix_and_encoding((unsigned char)(opcode_byte | 0x80), 0xC0, encode, imm8); + } else { + InstructionAttr attributes(AVX_128bit, is_prefixq, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); + attributes.set_address_attributes(/* tuple_type */ EVEX_NOSCALE, size); + int encode = emit_eevex_prefix_or_demote_ndd(src_enc, dst_enc, nds_enc, pre, opc, &attributes, no_flags); + emit_int24(opcode_byte, (0xC0 | encode), imm8); + } +} + +void Assembler::emit_eevex_or_demote(int dst_enc, int nds_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc, + int size, int opcode_byte, bool no_flags, bool is_map1, bool swap) { + int encode; + bool is_prefixq = (size == EVEX_64bit) ? true : false; + if (is_demotable(no_flags, dst_enc, nds_enc)) { + if (size == EVEX_16bit) { + emit_int8(0x66); + } + + if (swap) { + encode = is_prefixq ? prefixq_and_encode(dst_enc, src_enc, is_map1) : prefix_and_encode(dst_enc, src_enc, is_map1); + } else { + encode = is_prefixq ? prefixq_and_encode(src_enc, dst_enc, is_map1) : prefix_and_encode(src_enc, dst_enc, is_map1); + } + emit_opcode_prefix_and_encoding((unsigned char)opcode_byte, 0xC0, encode); + } else { + InstructionAttr attributes(AVX_128bit, is_prefixq, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); + attributes.set_is_evex_instruction(); + if (swap) { + encode = vex_prefix_and_encode(nds_enc, dst_enc, src_enc, pre, opc, &attributes, /* src_is_gpr */ true, /* nds_is_ndd */ true, no_flags); + } else { + encode = vex_prefix_and_encode(src_enc, dst_enc, nds_enc, pre, opc, &attributes, /* src_is_gpr */ true, /* nds_is_ndd */ true, no_flags); + } + emit_int16(opcode_byte, (0xC0 | encode)); + } +} + +int Assembler::emit_eevex_prefix_or_demote_ndd(int dst_enc, int nds_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc, + InstructionAttr *attributes, bool no_flags, bool use_prefixq) { + if (is_demotable(no_flags, dst_enc, nds_enc)) { + if (pre == VEX_SIMD_66) { + emit_int8(0x66); + } + return use_prefixq ? prefixq_and_encode(dst_enc, src_enc) : prefix_and_encode(dst_enc, src_enc); + } attributes->set_is_evex_instruction(); return vex_prefix_and_encode(dst_enc, nds_enc, src_enc, pre, opc, attributes, /* src_is_gpr */ true, /* nds_is_ndd */ true, no_flags); } -int Assembler::evex_prefix_and_encode_nf(int dst_enc, int nds_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc, - InstructionAttr *attributes, bool no_flags) { +int Assembler::emit_eevex_prefix_or_demote_ndd(int dst_enc, int nds_enc, VexSimdPrefix pre, VexOpcode opc, + InstructionAttr *attributes, bool no_flags, bool use_prefixq) { + //Demote RegReg and RegRegImm instructions + if (is_demotable(no_flags, dst_enc, nds_enc)) { + return use_prefixq ? prefixq_and_encode(dst_enc) : prefix_and_encode(dst_enc); + } + attributes->set_is_evex_instruction(); + return vex_prefix_and_encode(0, dst_enc, nds_enc, pre, opc, attributes, /* src_is_gpr */ true, /* nds_is_ndd */ true, no_flags); +} + +int Assembler::emit_eevex_prefix_ndd(int dst_enc, VexSimdPrefix pre, VexOpcode opc, InstructionAttr *attributes, bool no_flags) { + attributes->set_is_evex_instruction(); + return vex_prefix_and_encode(0, 0, dst_enc, pre, opc, attributes, /* src_is_gpr */ true, /* nds_is_ndd */ true, no_flags); +} + +int Assembler::eevex_prefix_and_encode_nf(int dst_enc, int nds_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc, + InstructionAttr *attributes, bool no_flags) { attributes->set_is_evex_instruction(); return vex_prefix_and_encode(dst_enc, nds_enc, src_enc, pre, opc, attributes, /* src_is_gpr */ true, /* nds_is_ndd */ false, no_flags); } +void Assembler::emit_eevex_prefix_or_demote_arith_ndd(Register dst, Register nds, int32_t imm32, VexSimdPrefix pre, VexOpcode opc, + int size, int op1, int op2, bool no_flags) { + int dst_enc = dst->encoding(); + int nds_enc = nds->encoding(); + bool demote = is_demotable(no_flags, dst_enc, nds_enc); + if (demote) { + (size == EVEX_64bit) ? (void) prefixq_and_encode(dst_enc) : (void) prefix_and_encode(dst_enc); + } else { + bool vex_w = (size == EVEX_64bit) ? true : false; + InstructionAttr attributes(AVX_128bit, vex_w, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); + //attributes.set_address_attributes(/* tuple_type */ EVEX_NOSCALE, size); + attributes.set_is_evex_instruction(); + vex_prefix_and_encode(0, dst_enc, nds_enc, pre, opc, &attributes, /* src_is_gpr */ true, /* nds_is_ndd */ true, no_flags); + + } + emit_arith(op1, op2, nds, imm32, demote); +} + void Assembler::simd_prefix(XMMRegister xreg, XMMRegister nds, Address adr, VexSimdPrefix pre, VexOpcode opc, InstructionAttr *attributes) { if (UseAVX > 0) { @@ -13081,6 +13092,10 @@ int Assembler::simd_prefix_and_encode(XMMRegister dst, XMMRegister nds, XMMRegis } } +bool Assembler::is_demotable(bool no_flags, int dst_enc, int nds_enc) { + return (!no_flags && dst_enc == nds_enc); +} + void Assembler::vmaxss(XMMRegister dst, XMMRegister nds, XMMRegister src) { assert(VM_Version::supports_avx(), ""); InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); @@ -14515,7 +14530,7 @@ void Assembler::eaddq(Register dst, Address src, int32_t imm32, bool no_flags) { InstructionMark im(this); InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); attributes.set_address_attributes(/* tuple_type */ EVEX_NOSCALE, /* input_size_in_bits */ EVEX_64bit); - evex_prefix_ndd(src, dst->encoding(), 0, VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags); + eevex_prefix_ndd(src, dst->encoding(), 0, VEX_SIMD_NONE, VEX_OPCODE_0F_3C /* MAP4 */, &attributes, no_flags); emit_arith_operand(0x81, rax, src, imm32); } @@ -14529,7 +14544,7 @@ void Assembler::eaddq(Register dst, Address src1, Register src2, bool no_flags) InstructionMark im(this); InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); attributes.set_address_attributes(/* tuple_type */ EVEX_NOSCALE, /* input_size_in_bits */ EVEX_64bit); - evex_prefix_ndd(src1, dst->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags); + eevex_prefix_ndd(src1, dst->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C /* MAP4 */, &attributes, no_flags); emit_int8(0x01); emit_operand(src2, src1, 0); } @@ -14540,9 +14555,7 @@ void Assembler::addq(Register dst, int32_t imm32) { } void Assembler::eaddq(Register dst, Register src, int32_t imm32, bool no_flags) { - InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); - (void) evex_prefix_and_encode_ndd(0, dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags); - emit_arith_ndd(0x81, 0xC0, src, imm32); + emit_eevex_prefix_or_demote_arith_ndd(dst, src, imm32, VEX_SIMD_NONE, VEX_OPCODE_0F_3C /* MAP4 */, EVEX_64bit, 0x81, 0xC0, no_flags); } void Assembler::addq(Register dst, Address src) { @@ -14553,11 +14566,7 @@ void Assembler::addq(Register dst, Address src) { void Assembler::eaddq(Register dst, Register src1, Address src2, bool no_flags) { InstructionMark im(this); - InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); - attributes.set_address_attributes(/* tuple_type */ EVEX_NOSCALE, /* input_size_in_bits */ EVEX_64bit); - evex_prefix_ndd(src2, dst->encoding(), src1->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags); - emit_int8(0x03); - emit_operand(src1, src2, 0); + emit_eevex_or_demote(dst, src1, src2, VEX_SIMD_NONE, VEX_OPCODE_0F_3C /* MAP4 */, EVEX_64bit, 0x03, no_flags); } void Assembler::addq(Register dst, Register src) { @@ -14569,7 +14578,7 @@ void Assembler::eaddq(Register dst, Register src1, Register src2, bool no_flags) InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); // NDD shares its encoding bits with NDS bits for regular EVEX instruction. // Therefore, DST is passed as the second argument to minimize changes in the leaf level routine. - (void) evex_prefix_and_encode_ndd(src1->encoding(), dst->encoding(), src2->encoding(), VEX_SIMD_NONE, /* MAP4 */VEX_OPCODE_0F_3C, &attributes, no_flags); + (void) emit_eevex_prefix_or_demote_ndd(src1->encoding(), dst->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C /* MAP4 */, &attributes, no_flags, true /* use_prefixq */); emit_arith(0x03, 0xC0, src1, src2); } @@ -14577,7 +14586,7 @@ void Assembler::adcxq(Register dst, Register src) { //assert(VM_Version::supports_adx(), "adx instructions not supported"); if (needs_rex2(dst, src)) { InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); - int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3C, &attributes, true); + int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3C /* MAP4 */, &attributes, true); emit_int16((unsigned char)0x66, (0xC0 | encode)); } else { emit_int8(0x66); @@ -14590,16 +14599,19 @@ void Assembler::adcxq(Register dst, Register src) { } void Assembler::eadcxq(Register dst, Register src1, Register src2) { - InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); - int encode = evex_prefix_and_encode_ndd(src1->encoding(), dst->encoding(), src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3C, &attributes); - emit_int16((unsigned char)0x66, (0xC0 | encode)); + if (is_demotable(false, dst->encoding(), src1->encoding())) { + return adcxq(dst, src2); + } + InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); + int encode = emit_eevex_prefix_or_demote_ndd(src1->encoding(), dst->encoding(), src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3C /* MAP4 */, &attributes, false /* no_flags */, true /* use_prefixq */); + emit_int16((unsigned char)0x66, (0xC0 | encode)); } void Assembler::adoxq(Register dst, Register src) { //assert(VM_Version::supports_adx(), "adx instructions not supported"); if (needs_rex2(dst, src)) { InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); - int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_3C, &attributes, true); + int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_3C /* MAP4 */, &attributes, true); emit_int16((unsigned char)0x66, (0xC0 | encode)); } else { emit_int8((unsigned char)0xF3); @@ -14612,9 +14624,12 @@ void Assembler::adoxq(Register dst, Register src) { } void Assembler::eadoxq(Register dst, Register src1, Register src2) { - InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); - int encode = evex_prefix_and_encode_ndd(src1->encoding(), dst->encoding(), src2->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_3C, &attributes); - emit_int16((unsigned char)0x66, (0xC0 | encode)); + if (is_demotable(false, dst->encoding(), src1->encoding())) { + return adoxq(dst, src2); + } + InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); + int encode = emit_eevex_prefix_or_demote_ndd(src1->encoding(), dst->encoding(), src2->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_3C /* MAP4 */, &attributes, false /* no_flags */, true /* use_prefixq */); + emit_int16((unsigned char)0x66, (0xC0 | encode)); } void Assembler::andq(Address dst, int32_t imm32) { @@ -14627,7 +14642,7 @@ void Assembler::eandq(Register dst, Address src, int32_t imm32, bool no_flags) { InstructionMark im(this); InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); attributes.set_address_attributes(/* tuple_type */ EVEX_NOSCALE, /* input_size_in_bits */ EVEX_64bit); - evex_prefix_ndd(src, dst->encoding(), 0, VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags); + eevex_prefix_ndd(src, dst->encoding(), 0, VEX_SIMD_NONE, VEX_OPCODE_0F_3C /* MAP4 */, &attributes, no_flags); emit_arith_operand(0x81, as_Register(4), src, imm32); } @@ -14637,9 +14652,7 @@ void Assembler::andq(Register dst, int32_t imm32) { } void Assembler::eandq(Register dst, Register src, int32_t imm32, bool no_flags) { - InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); - evex_prefix_and_encode_ndd(0, dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags); - emit_arith_ndd(0x81, 0xE0, src, imm32); + emit_eevex_prefix_or_demote_arith_ndd(dst, src, imm32, VEX_SIMD_NONE, VEX_OPCODE_0F_3C /* MAP4 */, EVEX_64bit, 0x81, 0xE0, no_flags); } void Assembler::andq(Register dst, Address src) { @@ -14650,11 +14663,7 @@ void Assembler::andq(Register dst, Address src) { void Assembler::eandq(Register dst, Register src1, Address src2, bool no_flags) { InstructionMark im(this); - InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); - attributes.set_address_attributes(/* tuple_type */ EVEX_NOSCALE, /* input_size_in_bits */ EVEX_64bit); - evex_prefix_ndd(src2, dst->encoding(), src1->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags); - emit_int8(0x23); - emit_operand(src1, src2, 0); + emit_eevex_or_demote(dst, src1, src2, VEX_SIMD_NONE, VEX_OPCODE_0F_3C /* MAP4 */, EVEX_64bit, 0x23, no_flags); } void Assembler::andq(Register dst, Register src) { @@ -14666,7 +14675,7 @@ void Assembler::eandq(Register dst, Register src1, Register src2, bool no_flags) InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); // NDD shares its encoding bits with NDS bits for regular EVEX instruction. // Therefore, DST is passed as the second argument to minimize changes in the leaf level routine. - (void) evex_prefix_and_encode_ndd(src1->encoding(), dst->encoding(), src2->encoding(), VEX_SIMD_NONE, /* MAP4 */VEX_OPCODE_0F_3C, &attributes, no_flags); + (void) emit_eevex_prefix_or_demote_ndd(src1->encoding(), dst->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C /* MAP4 */, &attributes, no_flags, true /* use_prefixq */); emit_arith(0x23, 0xC0, src1, src2); } @@ -14680,7 +14689,7 @@ void Assembler::eandq(Register dst, Address src1, Register src2, bool no_flags) InstructionMark im(this); InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); attributes.set_address_attributes(/* tuple_type */ EVEX_NOSCALE, /* input_size_in_bits */ EVEX_64bit); - evex_prefix_ndd(src1, dst->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags); + eevex_prefix_ndd(src1, dst->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C /* MAP4 */, &attributes, no_flags); emit_int8(0x21); emit_operand(src2, src1, 0); } @@ -14819,9 +14828,7 @@ void Assembler::cmovq(Condition cc, Register dst, Register src) { } void Assembler::ecmovq(Condition cc, Register dst, Register src1, Register src2) { - InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); - int encode = evex_prefix_and_encode_ndd(src1->encoding(), dst->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes); - emit_int16((0x40 | cc), (0xC0 | encode)); + emit_eevex_or_demote(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C /* MAP4 */, EVEX_64bit, 0x40 | cc, false /* no_flags */, true /* is_map1 */, true /* swap */); } void Assembler::cmovq(Condition cc, Register dst, Address src) { @@ -14833,11 +14840,7 @@ void Assembler::cmovq(Condition cc, Register dst, Address src) { void Assembler::ecmovq(Condition cc, Register dst, Register src1, Address src2) { InstructionMark im(this); - InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); - attributes.set_address_attributes(/* tuple_type */ EVEX_NOSCALE, /* input_size_in_bits */ EVEX_64bit); - evex_prefix_ndd(src2, dst->encoding(), src1->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes); - emit_int8((0x40 | cc)); - emit_operand(src1, src2, 0); + emit_eevex_or_demote(dst, src1, src2, VEX_SIMD_NONE, VEX_OPCODE_0F_3C /* MAP4 */, EVEX_64bit, (0x40 | cc) , false /* no_flags */, true /* is_map1 */); } void Assembler::cmpq(Address dst, int32_t imm32) { @@ -14936,7 +14939,7 @@ void Assembler::decl(Register dst) { void Assembler::edecl(Register dst, Register src, bool no_flags) { InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); - int encode = evex_prefix_and_encode_ndd(0, dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags); + int encode = emit_eevex_prefix_or_demote_ndd(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C /* MAP4 */, &attributes, no_flags); emit_int16((unsigned char)0xFF, (0xC8 | encode)); } @@ -14949,7 +14952,7 @@ void Assembler::decq(Register dst) { void Assembler::edecq(Register dst, Register src, bool no_flags) { InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); - int encode = evex_prefix_and_encode_ndd(0, dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags); + int encode = emit_eevex_prefix_or_demote_ndd(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C /* MAP4 */, &attributes, no_flags, true /* use_prefixq */); emit_int16((unsigned char)0xFF, (0xC8 | encode)); } @@ -14964,7 +14967,7 @@ void Assembler::edecq(Register dst, Address src, bool no_flags) { InstructionMark im(this); InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); attributes.set_address_attributes(/* tuple_type */ EVEX_NOSCALE, /* input_size_in_bits */ EVEX_64bit); - evex_prefix_ndd(src, dst->encoding(), 0, VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags); + eevex_prefix_ndd(src, dst->encoding(), 0, VEX_SIMD_NONE, VEX_OPCODE_0F_3C /* MAP4 */, &attributes, no_flags); emit_int8((unsigned char)0xFF); emit_operand(rcx, src, 0); } @@ -15004,7 +15007,7 @@ void Assembler::idivq(Register src) { void Assembler::eidivq(Register src, bool no_flags) { InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); - int encode = evex_prefix_and_encode_nf(0, 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags); + int encode = eevex_prefix_and_encode_nf(0, 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C /* MAP4 */, &attributes, no_flags); emit_int16((unsigned char)0xF7, (0xF8 | encode)); } @@ -15015,7 +15018,7 @@ void Assembler::divq(Register src) { void Assembler::edivq(Register src, bool no_flags) { InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); - int encode = evex_prefix_and_encode_nf(0, 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags); + int encode = eevex_prefix_and_encode_nf(0, 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C /* MAP4 */, &attributes, no_flags); emit_int16((unsigned char)0xF7, (0xF0 | encode)); } @@ -15025,15 +15028,16 @@ void Assembler::imulq(Register dst, Register src) { } void Assembler::eimulq(Register dst, Register src, bool no_flags) { + if (is_demotable(no_flags, dst->encoding(), src->encoding())) { + return imulq(dst); + } InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); - int encode = evex_prefix_and_encode_nf(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags); + int encode = eevex_prefix_and_encode_nf(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C /* MAP4 */, &attributes, no_flags); emit_int16((unsigned char)0xAF, (0xC0 | encode)); } void Assembler::eimulq(Register dst, Register src1, Register src2, bool no_flags) { - InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); - int encode = evex_prefix_and_encode_ndd(src1->encoding(), dst->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags); - emit_int16((unsigned char)0xAF, (0xC0 | encode)); + emit_eevex_or_demote(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C /* MAP4 */, EVEX_64bit, 0xAF, no_flags, true /* is_map1 */, true /* swap */); } void Assembler::imulq(Register src) { @@ -15043,7 +15047,7 @@ void Assembler::imulq(Register src) { void Assembler::eimulq(Register src, bool no_flags) { InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); - int encode = evex_prefix_and_encode_nf(0, 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags); + int encode = eevex_prefix_and_encode_nf(0, 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C /* MAP4 */, &attributes, no_flags); emit_int16((unsigned char)0xF7, (0xE8 | encode)); } @@ -15065,7 +15069,7 @@ void Assembler::eimulq(Register dst, Address src, int32_t value, bool no_flags) InstructionMark im(this); InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); attributes.set_address_attributes(/* tuple_type */ EVEX_NOSCALE, /* input_size_in_bits */ EVEX_32bit); - evex_prefix_nf(src, 0, dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags); + eevex_prefix_nf(src, 0, dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C /* MAP4 */, &attributes, no_flags); if (is8bit(value)) { emit_int8((unsigned char)0x6B); emit_operand(dst, src, 1); @@ -15089,7 +15093,7 @@ void Assembler::imulq(Register dst, Register src, int value) { void Assembler::eimulq(Register dst, Register src, int value, bool no_flags) { InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); - int encode = evex_prefix_and_encode_nf(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, /* MAP4 */VEX_OPCODE_0F_3C, &attributes, no_flags); + int encode = eevex_prefix_and_encode_nf(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C /* MAP4 */, &attributes, no_flags); if (is8bit(value)) { emit_int24(0x6B, (0xC0 | encode), (value & 0xFF)); } else { @@ -15109,7 +15113,7 @@ void Assembler::eimulq(Register dst, Address src, bool no_flags) { InstructionMark im(this); InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); attributes.set_address_attributes(/* tuple_type */ EVEX_NOSCALE, /* input_size_in_bits */ EVEX_64bit); - evex_prefix_nf(src, 0, dst->encoding(), VEX_SIMD_NONE, /* MAP4 */VEX_OPCODE_0F_3C, &attributes, no_flags); + eevex_prefix_nf(src, 0, dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C /* MAP4 */, &attributes, no_flags); emit_int8((unsigned char)0xAF); emit_operand(dst, src, 0); @@ -15117,11 +15121,7 @@ void Assembler::eimulq(Register dst, Address src, bool no_flags) { void Assembler::eimulq(Register dst, Register src1, Address src2, bool no_flags) { InstructionMark im(this); - InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); - attributes.set_address_attributes(/* tuple_type */ EVEX_NOSCALE, /* input_size_in_bits */ EVEX_32bit); - evex_prefix_ndd(src2, dst->encoding(), src1->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags); - emit_int8((unsigned char)0xAF); - emit_operand(src1, src2, 0); + emit_eevex_or_demote(dst, src1, src2, VEX_SIMD_NONE, VEX_OPCODE_0F_3C /* MAP4 */, EVEX_64bit, (unsigned char)0xAF, no_flags, true /* is_map1 */); } void Assembler::incl(Register dst) { @@ -15135,8 +15135,7 @@ void Assembler::eincl(Register dst, Register src, bool no_flags) { // Don't use it directly. Use MacroAssembler::incrementl() instead. // Use two-byte form (one-byte from is a REX prefix in 64-bit mode) InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); - // int encode = evex_prefix_and_encode_ndd(0, dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags); - int encode = evex_prefix_and_encode_ndd(0, dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags); + int encode = emit_eevex_prefix_or_demote_ndd(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C /* MAP4 */, &attributes, no_flags); emit_int16((unsigned char)0xFF, (0xC0 | encode)); } @@ -15151,7 +15150,7 @@ void Assembler::eincq(Register dst, Register src, bool no_flags) { // Don't use it directly. Use MacroAssembler::incrementq() instead. // Use two-byte form (one-byte from is a REX prefix in 64-bit mode) InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); - int encode = evex_prefix_and_encode_ndd(0, dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags); + int encode = emit_eevex_prefix_or_demote_ndd(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C /* MAP4 */, &attributes, no_flags, true /* use_prefixq */); emit_int16((unsigned char)0xFF, (0xC0 | encode)); } @@ -15167,7 +15166,7 @@ void Assembler::eincq(Register dst, Address src, bool no_flags) { InstructionMark im(this); InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); attributes.set_address_attributes(/* tuple_type */ EVEX_NOSCALE, /* input_size_in_bits */ EVEX_64bit); - evex_prefix_ndd(src, dst->encoding(), 0, VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags); + eevex_prefix_ndd(src, dst->encoding(), 0, VEX_SIMD_NONE, VEX_OPCODE_0F_3C /* MAP4 */, &attributes, no_flags); emit_int8((unsigned char) 0xFF); emit_operand(rax, src, 0); } @@ -15243,7 +15242,7 @@ void Assembler::lzcntq(Register dst, Register src) { void Assembler::elzcntq(Register dst, Register src, bool no_flags) { assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR"); InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); - int encode = evex_prefix_and_encode_nf(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags); + int encode = eevex_prefix_and_encode_nf(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C /* MAP4 */, &attributes, no_flags); emit_int16((unsigned char)0xF5, (0xC0 | encode)); } @@ -15261,7 +15260,7 @@ void Assembler::elzcntq(Register dst, Address src, bool no_flags) { InstructionMark im(this); InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); attributes.set_address_attributes(/* tuple_type */ EVEX_NOSCALE, /* input_size_in_bits */ EVEX_64bit); - evex_prefix_nf(src, 0, dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags); + eevex_prefix_nf(src, 0, dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C /* MAP4 */, &attributes, no_flags); emit_int8((unsigned char)0xF5); emit_operand(dst, src, 0); } @@ -15388,7 +15387,7 @@ void Assembler::emulq(Address src, bool no_flags) { InstructionMark im(this); InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); attributes.set_address_attributes(/* tuple_type */ EVEX_NOSCALE, /* input_size_in_bits */ EVEX_64bit); - evex_prefix_nf(src, 0, 0, VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags); + eevex_prefix_nf(src, 0, 0, VEX_SIMD_NONE, VEX_OPCODE_0F_3C /* MAP4 */, &attributes, no_flags); emit_int8(0xF7); emit_operand(rsp, src, 0); } @@ -15400,7 +15399,7 @@ void Assembler::mulq(Register src) { void Assembler::emulq(Register src, bool no_flags) { InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); - int encode = evex_prefix_and_encode_nf(0, 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags); + int encode = eevex_prefix_and_encode_nf(0, 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C /* MAP4 */, &attributes, no_flags); emit_int16((unsigned char)0xF7, (0xE0 | encode)); } @@ -15418,7 +15417,7 @@ void Assembler::negq(Register dst) { void Assembler::enegq(Register dst, Register src, bool no_flags) { InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); - int encode = evex_prefix_and_encode_ndd(0, dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags); + int encode = emit_eevex_prefix_or_demote_ndd(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C /* MAP4 */, &attributes, no_flags, true /* use_prefixq */); emit_int16((unsigned char)0xF7, (0xD8 | encode)); } @@ -15432,7 +15431,7 @@ void Assembler::enegq(Register dst, Address src, bool no_flags) { InstructionMark im(this); InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); attributes.set_address_attributes(/* tuple_type */ EVEX_NOSCALE, /* input_size_in_bits */ EVEX_64bit); - evex_prefix_ndd(src, dst->encoding(), 0, VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags); + eevex_prefix_ndd(src, dst->encoding(), 0, VEX_SIMD_NONE, VEX_OPCODE_0F_3C /* MAP4 */, &attributes, no_flags); emit_int8((unsigned char)0xF7); emit_operand(as_Register(3), src, 0); } @@ -15444,7 +15443,7 @@ void Assembler::notq(Register dst) { void Assembler::enotq(Register dst, Register src) { InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); - int encode = evex_prefix_and_encode_ndd(0, dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes); + int encode = emit_eevex_prefix_or_demote_ndd(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C /* MAP4 */, &attributes, false /* no_flags */, true /* use_prefixq */); emit_int16((unsigned char)0xF7, (0xD0 | encode)); } @@ -15488,7 +15487,7 @@ void Assembler::eorq(Register dst, Address src, int32_t imm32, bool no_flags) { InstructionMark im(this); InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); attributes.set_address_attributes(/* tuple_type */ EVEX_NOSCALE, /* input_size_in_bits */ EVEX_64bit); - evex_prefix_ndd(src, dst->encoding(), 0, VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags); + eevex_prefix_ndd(src, dst->encoding(), 0, VEX_SIMD_NONE, VEX_OPCODE_0F_3C /* MAP4 */, &attributes, no_flags); emit_arith_operand(0x81, as_Register(1), src, imm32); } @@ -15502,7 +15501,7 @@ void Assembler::eorq(Register dst, Address src1, Register src2, bool no_flags) { InstructionMark im(this); InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); attributes.set_address_attributes(/* tuple_type */ EVEX_NOSCALE, /* input_size_in_bits */ EVEX_64bit); - evex_prefix_ndd(src1, dst->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags); + eevex_prefix_ndd(src1, dst->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C /* MAP4 */, &attributes, no_flags); emit_int8(0x09); emit_operand(src2, src1, 0); } @@ -15513,9 +15512,7 @@ void Assembler::orq(Register dst, int32_t imm32) { } void Assembler::eorq(Register dst, Register src, int32_t imm32, bool no_flags) { - InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); - evex_prefix_and_encode_ndd(0, dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags); - emit_arith_ndd(0x81, 0xC8, src, imm32); + emit_eevex_prefix_or_demote_arith_ndd(dst, src, imm32, VEX_SIMD_NONE, VEX_OPCODE_0F_3C /* MAP4 */, EVEX_64bit, 0x81, 0xC8, no_flags); } void Assembler::orq_imm32(Register dst, int32_t imm32) { @@ -15525,7 +15522,7 @@ void Assembler::orq_imm32(Register dst, int32_t imm32) { void Assembler::eorq_imm32(Register dst, Register src, int32_t imm32, bool no_flags) { InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); - (void) evex_prefix_and_encode_ndd(0, dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags); + (void) emit_eevex_prefix_or_demote_ndd(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C /* MAP4 */, &attributes, no_flags, true /* use_prefixq */); emit_arith_imm32(0x81, 0xC8, src, imm32); } @@ -15537,11 +15534,7 @@ void Assembler::orq(Register dst, Address src) { void Assembler::eorq(Register dst, Register src1, Address src2, bool no_flags) { InstructionMark im(this); - InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); - attributes.set_address_attributes(/* tuple_type */ EVEX_NOSCALE, /* input_size_in_bits */ EVEX_64bit); - evex_prefix_ndd(src2, dst->encoding(), src1->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags); - emit_int8(0x0B); - emit_operand(src1, src2, 0); + emit_eevex_or_demote(dst, src1, src2, VEX_SIMD_NONE, VEX_OPCODE_0F_3C /* MAP4 */, EVEX_64bit, 0x0B, no_flags); } void Assembler::orq(Register dst, Register src) { @@ -15553,7 +15546,7 @@ void Assembler::eorq(Register dst, Register src1, Register src2, bool no_flags) InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); // NDD shares its encoding bits with NDS bits for regular EVEX instruction. // Therefore, DST is passed as the second argument to minimize changes in the leaf level routine. - (void) evex_prefix_and_encode_ndd(src1->encoding(), dst->encoding(), src2->encoding(), VEX_SIMD_NONE, /* MAP4 */VEX_OPCODE_0F_3C, &attributes, no_flags); + (void) emit_eevex_prefix_or_demote_ndd(src1->encoding(), dst->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C /* MAP4 */, &attributes, no_flags, true /* use_prefixq */); emit_arith(0x0B, 0xC0, src1, src2); } @@ -15570,7 +15563,7 @@ void Assembler::epopcntq(Register dst, Address src, bool no_flags) { InstructionMark im(this); InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); attributes.set_address_attributes(/* tuple_type */ EVEX_NOSCALE, /* input_size_in_bits */ EVEX_64bit); - evex_prefix_nf(src, 0, dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags); + eevex_prefix_nf(src, 0, dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C /* MAP4 */, &attributes, no_flags); emit_int8((unsigned char) 0x88); emit_operand(dst, src, 0); } @@ -15585,7 +15578,7 @@ void Assembler::popcntq(Register dst, Register src) { void Assembler::epopcntq(Register dst, Register src, bool no_flags) { assert(VM_Version::supports_popcnt(), "must support"); InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); - int encode = evex_prefix_and_encode_nf(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags); + int encode = eevex_prefix_and_encode_nf(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C /* MAP4 */, &attributes, no_flags); emit_int16((unsigned char)0x88, (0xC0 | encode)); } @@ -15810,7 +15803,7 @@ void Assembler::rclq(Register dst, int imm8) { void Assembler::erclq(Register dst, Register src, int imm8) { assert(isShiftCount(imm8 >> 1), "illegal shift count"); InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); - int encode = evex_prefix_and_encode_ndd(0, dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes); + int encode = emit_eevex_prefix_or_demote_ndd(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C /* MAP4 */, &attributes, false /* no_flags */, true /* use_prefixq */); if (imm8 == 1) { emit_int16((unsigned char)0xD1, (0xD0 | encode)); } else { @@ -15831,7 +15824,7 @@ void Assembler::rcrq(Register dst, int imm8) { void Assembler::ercrq(Register dst, Register src, int imm8) { assert(isShiftCount(imm8 >> 1), "illegal shift count"); InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); - int encode = evex_prefix_and_encode_ndd(0, dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes); + int encode = emit_eevex_prefix_or_demote_ndd(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C /* MAP4 */, &attributes, false /* no_flags */, true /* use_prefixq */); if (imm8 == 1) { emit_int16((unsigned char)0xD1, (0xD8 | encode)); } else { @@ -15894,7 +15887,7 @@ void Assembler::esalq(Register dst, Address src, int imm8, bool no_flags) { assert(isShiftCount(imm8 >> 1), "illegal shift count"); InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); attributes.set_address_attributes(/* tuple_type */ EVEX_NOSCALE, /* input_size_in_bits */ EVEX_64bit); - evex_prefix_ndd(src, dst->encoding(), 0, VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags); + eevex_prefix_ndd(src, dst->encoding(), 0, VEX_SIMD_NONE, VEX_OPCODE_0F_3C /* MAP4 */, &attributes, no_flags); if (imm8 == 1) { emit_int8((unsigned char)0xD1); emit_operand(as_Register(4), src, 0); @@ -15916,7 +15909,7 @@ void Assembler::esalq(Register dst, Address src, bool no_flags) { InstructionMark im(this); InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); attributes.set_address_attributes(/* tuple_type */ EVEX_NOSCALE, /* input_size_in_bits */ EVEX_64bit); - evex_prefix_ndd(src, dst->encoding(), 0, VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags); + eevex_prefix_ndd(src, dst->encoding(), 0, VEX_SIMD_NONE, VEX_OPCODE_0F_3C /* MAP4 */, &attributes, no_flags); emit_int8((unsigned char)0xD3); emit_operand(as_Register(4), src, 0); } @@ -15934,7 +15927,7 @@ void Assembler::salq(Register dst, int imm8) { void Assembler::esalq(Register dst, Register src, int imm8, bool no_flags) { assert(isShiftCount(imm8 >> 1), "illegal shift count"); InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); - int encode = evex_prefix_and_encode_ndd(0, dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags); + int encode = emit_eevex_prefix_or_demote_ndd(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C /* MAP4 */, &attributes, no_flags, true /* use_prefixq */); if (imm8 == 1) { emit_int16((unsigned char)0xD1, (0xE0 | encode)); } else { @@ -15949,7 +15942,7 @@ void Assembler::salq(Register dst) { void Assembler::esalq(Register dst, Register src, bool no_flags) { InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); - int encode = evex_prefix_and_encode_ndd(0, dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags); + int encode = emit_eevex_prefix_or_demote_ndd(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C /* MAP4 */, &attributes, no_flags, true /* use_prefixq */); emit_int16((unsigned char)0xD3, (0xE0 | encode)); } @@ -15972,7 +15965,7 @@ void Assembler::esarq(Register dst, Address src, int imm8, bool no_flags) { InstructionMark im(this); InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); attributes.set_address_attributes(/* tuple_type */ EVEX_NOSCALE, /* input_size_in_bits */ EVEX_64bit); - evex_prefix_ndd(src, dst->encoding(), 0, VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags); + eevex_prefix_ndd(src, dst->encoding(), 0, VEX_SIMD_NONE, VEX_OPCODE_0F_3C /* MAP4 */, &attributes, no_flags); if (imm8 == 1) { emit_int8((unsigned char)0xD1); emit_operand(as_Register(7), src, 0); @@ -15994,7 +15987,7 @@ void Assembler::esarq(Register dst, Address src, bool no_flags) { InstructionMark im(this); InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); attributes.set_address_attributes(/* tuple_type */ EVEX_NOSCALE, /* input_size_in_bits */ EVEX_64bit); - evex_prefix_ndd(src, dst->encoding(), 0, VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags); + eevex_prefix_ndd(src, dst->encoding(), 0, VEX_SIMD_NONE, VEX_OPCODE_0F_3C /* MAP4 */, &attributes, no_flags); emit_int8((unsigned char)0xD3); emit_operand(as_Register(7), src, 0); } @@ -16011,7 +16004,7 @@ void Assembler::sarq(Register dst, int imm8) { void Assembler::esarq(Register dst, Register src, int imm8, bool no_flags) { InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); - int encode = evex_prefix_and_encode_ndd(0, dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags); + int encode = emit_eevex_prefix_or_demote_ndd(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C /* MAP4 */, &attributes, no_flags, true /* use_prefixq */); if (imm8 == 1) { emit_int16((unsigned char)0xD1, (0xF8 | encode)); } else { @@ -16026,7 +16019,7 @@ void Assembler::sarq(Register dst) { void Assembler::esarq(Register dst, Register src, bool no_flags) { InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); - int encode = evex_prefix_and_encode_ndd(0, dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags); + int encode = emit_eevex_prefix_or_demote_ndd(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C /* MAP4 */, &attributes, no_flags, true /* use_prefixq */); emit_int16((unsigned char)0xD3, (0xF8 | encode)); } @@ -16065,7 +16058,7 @@ void Assembler::shlq(Register dst, int imm8) { void Assembler::eshlq(Register dst, Register src, int imm8, bool no_flags) { assert(isShiftCount(imm8 >> 1), "illegal shift count"); InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); - int encode = evex_prefix_and_encode_ndd(0, dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags); + int encode = emit_eevex_prefix_or_demote_ndd(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C /* MAP4 */, &attributes, no_flags, true /* use_prefixq */); if (imm8 == 1 ) { emit_int16((unsigned char)0xD1, (0xE0 | encode)); } else { @@ -16080,7 +16073,7 @@ void Assembler::shlq(Register dst) { void Assembler::eshlq(Register dst, Register src, bool no_flags) { InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); - int encode = evex_prefix_and_encode_ndd(0, dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags); + int encode = emit_eevex_prefix_or_demote_ndd(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C /* MAP4 */, &attributes, no_flags, true /* use_prefixq */); emit_int16((unsigned char)0xD3, (0xE0 | encode)); } @@ -16098,7 +16091,7 @@ void Assembler::shrq(Register dst, int imm8) { void Assembler::eshrq(Register dst, Register src, int imm8, bool no_flags) { assert(isShiftCount(imm8 >> 1), "illegal shift count"); InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); - int encode = evex_prefix_and_encode_ndd(0, dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags); + int encode = emit_eevex_prefix_or_demote_ndd(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C /* MAP4 */, &attributes, no_flags, true /* use_prefixq */); if (imm8 == 1) { emit_int16((unsigned char)0xD1, (0xE8 | encode)); } @@ -16114,7 +16107,7 @@ void Assembler::shrq(Register dst) { void Assembler::eshrq(Register dst, Register src, bool no_flags) { InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); - int encode = evex_prefix_and_encode_ndd(0, dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags); + int encode = emit_eevex_prefix_or_demote_ndd(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C /* MAP4 */, &attributes, no_flags, true /* use_prefixq */); emit_int16((unsigned char)0xD3, (0xE8 | encode)); } @@ -16128,7 +16121,7 @@ void Assembler::eshrq(Register dst, Address src, bool no_flags) { InstructionMark im(this); InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); attributes.set_address_attributes(/* tuple_type */ EVEX_NOSCALE, /* input_size_in_bits */ EVEX_64bit); - evex_prefix_ndd(src, dst->encoding(), 0, VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags); + eevex_prefix_ndd(src, dst->encoding(), 0, VEX_SIMD_NONE, VEX_OPCODE_0F_3C /* MAP4 */, &attributes, no_flags); emit_int8((unsigned char)0xD3); emit_operand(as_Register(5), src, 0); } @@ -16152,7 +16145,7 @@ void Assembler::eshrq(Register dst, Address src, int imm8, bool no_flags) { assert(isShiftCount(imm8 >> 1), "illegal shift count"); InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); attributes.set_address_attributes(/* tuple_type */ EVEX_NOSCALE, /* input_size_in_bits */ EVEX_64bit); - evex_prefix_ndd(src, dst->encoding(), 0, VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags); + eevex_prefix_ndd(src, dst->encoding(), 0, VEX_SIMD_NONE, VEX_OPCODE_0F_3C /* MAP4 */, &attributes, no_flags); if (imm8 == 1) { emit_int8((unsigned char)0xD1); emit_operand(as_Register(5), src, 0); @@ -16174,7 +16167,7 @@ void Assembler::esubq(Register dst, Address src, int32_t imm32, bool no_flags) { InstructionMark im(this); InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); attributes.set_address_attributes(/* tuple_type */ EVEX_NOSCALE, /* input_size_in_bits */ EVEX_64bit); - evex_prefix_ndd(src, dst->encoding(), 0, VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags); + eevex_prefix_ndd(src, dst->encoding(), 0, VEX_SIMD_NONE, VEX_OPCODE_0F_3C /* MAP4 */, &attributes, no_flags); emit_arith_operand(0x81, rbp, src, imm32); } @@ -16188,7 +16181,7 @@ void Assembler::esubq(Register dst, Address src1, Register src2, bool no_flags) InstructionMark im(this); InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); attributes.set_address_attributes(/* tuple_type */ EVEX_NOSCALE, /* input_size_in_bits */ EVEX_64bit); - evex_prefix_ndd(src1, dst->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags); + eevex_prefix_ndd(src1, dst->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C /* MAP4 */, &attributes, no_flags); emit_int8(0x29); emit_operand(src2, src1, 0); } @@ -16199,9 +16192,7 @@ void Assembler::subq(Register dst, int32_t imm32) { } void Assembler::esubq(Register dst, Register src, int32_t imm32, bool no_flags) { - InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); - (void) evex_prefix_and_encode_ndd(0, dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags); - emit_arith_ndd(0x81, 0xE8, src, imm32); + emit_eevex_prefix_or_demote_arith_ndd(dst, src, imm32, VEX_SIMD_NONE, VEX_OPCODE_0F_3C /* MAP4 */, EVEX_64bit, 0x81, 0xE8, no_flags); } // Force generation of a 4 byte immediate value even if it fits into 8bit @@ -16212,7 +16203,7 @@ void Assembler::subq_imm32(Register dst, int32_t imm32) { void Assembler::esubq_imm32(Register dst, Register src, int32_t imm32, bool no_flags) { InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); - (void) evex_prefix_and_encode_ndd(0, dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags); + (void) emit_eevex_prefix_or_demote_ndd(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C /* MAP4 */, &attributes, no_flags, true /* use_prefixq */); emit_arith_imm32(0x81, 0xE8, src, imm32); } @@ -16224,11 +16215,7 @@ void Assembler::subq(Register dst, Address src) { void Assembler::esubq(Register dst, Register src1, Address src2, bool no_flags) { InstructionMark im(this); - InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); - attributes.set_address_attributes(/* tuple_type */ EVEX_NOSCALE, /* input_size_in_bits */ EVEX_64bit); - evex_prefix_ndd(src2, dst->encoding(), src1->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags); - emit_int8(0x2B); - emit_operand(src1, src2, 0); + emit_eevex_or_demote(dst, src1, src2, VEX_SIMD_NONE, VEX_OPCODE_0F_3C /* MAP4 */, EVEX_64bit, 0x2B, no_flags); } void Assembler::subq(Register dst, Register src) { @@ -16240,7 +16227,7 @@ void Assembler::esubq(Register dst, Register src1, Register src2, bool no_flags) InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); // NDD shares its encoding bits with NDS bits for regular EVEX instruction. // Therefore, DST is passed as the second argument to minimize changes in the leaf level routine. - (void) evex_prefix_and_encode_ndd(src1->encoding(), dst->encoding(), src2->encoding(), VEX_SIMD_NONE, /* MAP4 */VEX_OPCODE_0F_3C, &attributes, no_flags); + (void) emit_eevex_prefix_or_demote_ndd(src1->encoding(), dst->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C /* MAP4 */, &attributes, no_flags, true /* use_prefixq */); emit_arith(0x2B, 0xC0, src1, src2); } @@ -16305,7 +16292,7 @@ void Assembler::exorq(Register dst, Register src1, Register src2, bool no_flags) InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); // NDD shares its encoding bits with NDS bits for regular EVEX instruction. // Therefore, DST is passed as the second argument to minimize changes in the leaf level routine. - (void) evex_prefix_and_encode_ndd(src1->encoding(), dst->encoding(), src2->encoding(), VEX_SIMD_NONE, /* MAP4 */VEX_OPCODE_0F_3C, &attributes, no_flags); + (void) emit_eevex_prefix_or_demote_ndd(src1->encoding(), dst->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C /* MAP4 */, &attributes, no_flags, true /* use_prefixq */); emit_arith(0x33, 0xC0, src1, src2); } @@ -16317,11 +16304,7 @@ void Assembler::xorq(Register dst, Address src) { void Assembler::exorq(Register dst, Register src1, Address src2, bool no_flags) { InstructionMark im(this); - InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); - attributes.set_address_attributes(/* tuple_type */ EVEX_NOSCALE, /* input_size_in_bits */ EVEX_64bit); - evex_prefix_ndd(src2, dst->encoding(), src1->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags); - emit_int8(0x33); - emit_operand(src1, src2, 0); + emit_eevex_or_demote(dst, src1, src2, VEX_SIMD_NONE, VEX_OPCODE_0F_3C /* MAP4 */, EVEX_64bit, 0x33, no_flags); } void Assembler::xorq(Register dst, int32_t imm32) { @@ -16330,9 +16313,7 @@ void Assembler::xorq(Register dst, int32_t imm32) { } void Assembler::exorq(Register dst, Register src, int32_t imm32, bool no_flags) { - InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); - evex_prefix_and_encode_ndd(0, dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags); - emit_arith_ndd(0x81, 0xF0, src, imm32); + emit_eevex_prefix_or_demote_arith_ndd(dst, src, imm32, VEX_SIMD_NONE, VEX_OPCODE_0F_3C /* MAP4 */, EVEX_64bit, 0x81, 0xF0, no_flags); } void Assembler::xorq(Address dst, int32_t imm32) { @@ -16345,7 +16326,7 @@ void Assembler::exorq(Register dst, Address src, int32_t imm32, bool no_flags) { InstructionMark im(this); InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); attributes.set_address_attributes(/* tuple_type */ EVEX_NOSCALE, /* input_size_in_bits */ EVEX_64bit); - evex_prefix_ndd(src, dst->encoding(), 0, VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags); + eevex_prefix_ndd(src, dst->encoding(), 0, VEX_SIMD_NONE, VEX_OPCODE_0F_3C /* MAP4 */, &attributes, no_flags); emit_arith_operand(0x81, as_Register(6), src, imm32); } @@ -16360,7 +16341,7 @@ void Assembler::esetzucc(Condition cc, Register dst) { assert(0 <= cc && cc < 16, "illegal cc"); InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); // Encoding Format : eevex_prefix (4 bytes) | opcode_cc | modrm - int encode = evex_prefix_and_encode_ndd(0, 0, dst->encoding(), VEX_SIMD_F2, /* MAP4 */VEX_OPCODE_0F_3C, &attributes); + int encode = emit_eevex_prefix_ndd(dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_3C /* MAP4 */, &attributes); // demotion disabled emit_opcode_prefix_and_encoding((0x40 | cc), 0xC0, encode); } @@ -16368,7 +16349,7 @@ void Assembler::exorq(Register dst, Address src1, Register src2, bool no_flags) InstructionMark im(this); InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); attributes.set_address_attributes(/* tuple_type */ EVEX_NOSCALE, /* input_size_in_bits */ EVEX_64bit); - evex_prefix_ndd(src1, dst->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags); + eevex_prefix_ndd(src1, dst->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C /* MAP4 */, &attributes, no_flags); emit_int8(0x31); emit_operand(src2, src1, 0); } diff --git a/src/hotspot/cpu/x86/assembler_x86.hpp b/src/hotspot/cpu/x86/assembler_x86.hpp index 10e6264160c..b1959e23722 100644 --- a/src/hotspot/cpu/x86/assembler_x86.hpp +++ b/src/hotspot/cpu/x86/assembler_x86.hpp @@ -772,25 +772,42 @@ private: void evex_prefix(bool vex_r, bool vex_b, bool vex_x, bool evex_v, bool evex_r, bool evex_b, bool eevex_x, int nds_enc, VexSimdPrefix pre, VexOpcode opc, bool no_flags = false); - void evex_prefix_ndd(Address adr, int ndd_enc, int xreg_enc, VexSimdPrefix pre, VexOpcode opc, - InstructionAttr *attributes, bool no_flags = false); + void eevex_prefix_ndd(Address adr, int ndd_enc, int xreg_enc, VexSimdPrefix pre, VexOpcode opc, + InstructionAttr *attributes, bool no_flags = false); - void evex_prefix_nf(Address adr, int ndd_enc, int xreg_enc, VexSimdPrefix pre, VexOpcode opc, - InstructionAttr *attributes, bool no_flags = false); + void eevex_prefix_nf(Address adr, int ndd_enc, int xreg_enc, VexSimdPrefix pre, VexOpcode opc, + InstructionAttr *attributes, bool no_flags = false); void vex_prefix(Address adr, int nds_enc, int xreg_enc, VexSimdPrefix pre, VexOpcode opc, InstructionAttr *attributes, bool nds_is_ndd = false, bool no_flags = false); - int vex_prefix_and_encode(int dst_enc, int nds_enc, int src_enc, + int vex_prefix_and_encode(int dst_enc, int nds_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc, InstructionAttr *attributes, bool src_is_gpr = false, bool nds_is_ndd = false, bool no_flags = false); - int evex_prefix_and_encode_ndd(int dst_enc, int nds_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc, - InstructionAttr *attributes, bool no_flags = false); - - int evex_prefix_and_encode_nf(int dst_enc, int nds_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc, + int eevex_prefix_and_encode_nf(int dst_enc, int nds_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc, InstructionAttr *attributes, bool no_flags = false); + int emit_eevex_prefix_ndd(int dst_enc, VexSimdPrefix pre, VexOpcode opc, InstructionAttr *attributes, bool no_flags = false); + + int emit_eevex_prefix_or_demote_ndd(int dst_enc, int nds_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc, + InstructionAttr *attributes, bool no_flags = false, bool use_prefixq = false); + + int emit_eevex_prefix_or_demote_ndd(int dst_enc, int nds_enc, VexSimdPrefix pre, VexOpcode opc, + InstructionAttr *attributes, bool no_flags = false, bool use_prefixq = false); + + void emit_eevex_prefix_or_demote_arith_ndd(Register dst, Register nds, int32_t imm32, VexSimdPrefix pre, VexOpcode opc, + int size, int op1, int op2, bool no_flags); + + void emit_eevex_or_demote(Register dst, Register src1, Address src2, VexSimdPrefix pre, VexOpcode opc, + int size, int opcode_byte, bool no_flags = false, bool is_map1 = false); + + void emit_eevex_or_demote(int dst_enc, int nds_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc, + int size, int opcode_byte, bool no_flags, bool is_map1 = false, bool swap = false); + + void emit_eevex_or_demote(int dst_enc, int nds_enc, int src_enc, int8_t imm8, VexSimdPrefix pre, VexOpcode opc, + int size, int opcode_byte, bool no_flags, bool is_map1 = false); + void simd_prefix(XMMRegister xreg, XMMRegister nds, Address adr, VexSimdPrefix pre, VexOpcode opc, InstructionAttr *attributes); @@ -798,10 +815,10 @@ private: VexOpcode opc, InstructionAttr *attributes, bool src_is_gpr = false); // Helper functions for groups of instructions + bool is_demotable(bool no_flags, int dst_enc, int nds_enc); void emit_arith_b(int op1, int op2, Register dst, int imm8); - void emit_arith(int op1, int op2, Register dst, int32_t imm32); - void emit_arith_ndd(int op1, int op2, Register dst, int32_t imm32); + void emit_arith(int op1, int op2, Register dst, int32_t imm32, bool optimize_rax_dst = true); // Force generation of a 4 byte immediate value even if it fits into 8bit void emit_arith_imm32(int op1, int op2, Register dst, int32_t imm32); void emit_arith(int op1, int op2, Register dst, Register src); diff --git a/src/hotspot/cpu/x86/vm_version_x86.cpp b/src/hotspot/cpu/x86/vm_version_x86.cpp index 3f126039684..152866e65f3 100644 --- a/src/hotspot/cpu/x86/vm_version_x86.cpp +++ b/src/hotspot/cpu/x86/vm_version_x86.cpp @@ -909,7 +909,7 @@ void VM_Version::get_processor_features() { } // Check if processor has Intel Ecore - if (FLAG_IS_DEFAULT(EnableX86ECoreOpts) && is_intel() && cpu_family() == 6 && + if (FLAG_IS_DEFAULT(EnableX86ECoreOpts) && is_intel() && is_intel_server_family() && (_model == 0x97 || _model == 0xAA || _model == 0xAC || _model == 0xAF || _model == 0xCC || _model == 0xDD)) { FLAG_SET_DEFAULT(EnableX86ECoreOpts, true); @@ -1594,7 +1594,7 @@ void VM_Version::get_processor_features() { if (FLAG_IS_DEFAULT(UseStoreImmI16)) { UseStoreImmI16 = false; // don't use it on Intel cpus } - if (cpu_family() == 6 || cpu_family() == 15) { + if (is_intel_server_family() || cpu_family() == 15) { if (FLAG_IS_DEFAULT(UseAddressNop)) { // Use it on all Intel cpus starting from PentiumPro UseAddressNop = true; @@ -1610,7 +1610,7 @@ void VM_Version::get_processor_features() { UseXmmRegToRegMoveAll = false; } } - if (cpu_family() == 6 && supports_sse3()) { // New Intel cpus + if (is_intel_server_family() && supports_sse3()) { // New Intel cpus #ifdef COMPILER2 if (FLAG_IS_DEFAULT(MaxLoopPad)) { // For new Intel cpus do the next optimization: @@ -1848,7 +1848,7 @@ void VM_Version::get_processor_features() { FLAG_SET_DEFAULT(AllocatePrefetchDistance, allocate_prefetch_distance(use_watermark_prefetch)); } - if (is_intel() && cpu_family() == 6 && supports_sse3()) { + if (is_intel() && is_intel_server_family() && supports_sse3()) { if (FLAG_IS_DEFAULT(AllocatePrefetchLines) && supports_sse4_2() && supports_ht()) { // Nehalem based cpus FLAG_SET_DEFAULT(AllocatePrefetchLines, 4); @@ -3262,7 +3262,7 @@ int VM_Version::allocate_prefetch_distance(bool use_watermark_prefetch) { return 128; // Athlon } } else { // Intel - if (supports_sse3() && cpu_family() == 6) { + if (supports_sse3() && is_intel_server_family()) { if (supports_sse4_2() && supports_ht()) { // Nehalem based cpus return 192; } else if (use_watermark_prefetch) { // watermark prefetching on Core @@ -3270,7 +3270,7 @@ int VM_Version::allocate_prefetch_distance(bool use_watermark_prefetch) { } } if (supports_sse2()) { - if (cpu_family() == 6) { + if (is_intel_server_family()) { return 256; // Pentium M, Core, Core2 } else { return 512; // Pentium 4 diff --git a/src/hotspot/cpu/x86/vm_version_x86.hpp b/src/hotspot/cpu/x86/vm_version_x86.hpp index a544eeb71b8..3c8971e474b 100644 --- a/src/hotspot/cpu/x86/vm_version_x86.hpp +++ b/src/hotspot/cpu/x86/vm_version_x86.hpp @@ -791,6 +791,7 @@ public: static uint32_t cpu_stepping() { return _cpuid_info.cpu_stepping(); } static int cpu_family() { return _cpu;} static bool is_P6() { return cpu_family() >= 6; } + static bool is_intel_server_family() { return cpu_family() == 6 || cpu_family() == 19; } static bool is_amd() { assert_is_initialized(); return _cpuid_info.std_vendor_name_0 == 0x68747541; } // 'htuA' static bool is_hygon() { assert_is_initialized(); return _cpuid_info.std_vendor_name_0 == 0x6F677948; } // 'ogyH' static bool is_amd_family() { return is_amd() || is_hygon(); } @@ -946,7 +947,7 @@ public: } // Intel Core and newer cpus have fast IDIV instruction (excluding Atom). - static bool has_fast_idiv() { return is_intel() && cpu_family() == 6 && + static bool has_fast_idiv() { return is_intel() && is_intel_server_family() && supports_sse3() && _model != 0x1C; } static bool supports_compare_and_exchange() { return true; } diff --git a/src/hotspot/cpu/x86/x86_64.ad b/src/hotspot/cpu/x86/x86_64.ad index 751e9bda513..22490ba7bb3 100644 --- a/src/hotspot/cpu/x86/x86_64.ad +++ b/src/hotspot/cpu/x86/x86_64.ad @@ -7052,21 +7052,6 @@ instruct addI_rReg_mem(rRegI dst, memory src, rFlagsReg cr) ins_pipe(ialu_reg_mem); %} -instruct addI_rReg_mem_rReg_ndd(rRegI dst, memory src1, rRegI src2, rFlagsReg cr) -%{ - predicate(UseAPX); - match(Set dst (AddI (LoadI src1) src2)); - effect(KILL cr); - flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag); - - ins_cost(150); - format %{ "eaddl $dst, $src1, $src2\t# int ndd" %} - ins_encode %{ - __ eaddl($dst$$Register, $src1$$Address, $src2$$Register, false); - %} - ins_pipe(ialu_reg_mem); -%} - instruct addI_rReg_rReg_mem_ndd(rRegI dst, rRegI src1, memory src2, rFlagsReg cr) %{ predicate(UseAPX); @@ -7370,21 +7355,6 @@ instruct addL_rReg_rReg_mem_ndd(rRegL dst, rRegL src1, memory src2, rFlagsReg cr ins_pipe(ialu_reg_mem); %} -instruct addL_rReg_mem_rReg_ndd(rRegL dst, memory src1, rRegL src2, rFlagsReg cr) -%{ - predicate(UseAPX); - match(Set dst (AddL (LoadL src1) src2)); - effect(KILL cr); - flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag); - - ins_cost(150); - format %{ "eaddq $dst, $src1, $src2\t# long ndd" %} - ins_encode %{ - __ eaddq($dst$$Register, $src1$$Address, $src2$$Register, false); - %} - ins_pipe(ialu_reg_mem); -%} - instruct addL_mem_rReg(memory dst, rRegL src, rFlagsReg cr) %{ match(Set dst (StoreL dst (AddL (LoadL dst) src))); @@ -8596,7 +8566,6 @@ instruct mulI_rReg_ndd(rRegI dst, rRegI src1, rRegI src2, rFlagsReg cr) instruct mulI_rReg_imm(rRegI dst, rRegI src, immI imm, rFlagsReg cr) %{ - predicate(!UseAPX); match(Set dst (MulI src imm)); effect(KILL cr); @@ -8608,20 +8577,6 @@ instruct mulI_rReg_imm(rRegI dst, rRegI src, immI imm, rFlagsReg cr) ins_pipe(ialu_reg_reg_alu0); %} -instruct mulI_rReg_rReg_imm_ndd(rRegI dst, rRegI src1, immI src2, rFlagsReg cr) -%{ - predicate(UseAPX); - match(Set dst (MulI src1 src2)); - effect(KILL cr); - - ins_cost(300); - format %{ "eimull $dst, $src1, $src2\t# int ndd" %} - ins_encode %{ - __ eimull($dst$$Register, $src1$$Register, $src2$$constant, false); - %} - ins_pipe(ialu_reg_reg_alu0); -%} - instruct mulI_mem(rRegI dst, memory src, rFlagsReg cr) %{ predicate(!UseAPX); @@ -8652,7 +8607,6 @@ instruct mulI_rReg_rReg_mem_ndd(rRegI dst, rRegI src1, memory src2, rFlagsReg cr instruct mulI_mem_imm(rRegI dst, memory src, immI imm, rFlagsReg cr) %{ - predicate(!UseAPX); match(Set dst (MulI (LoadI src) imm)); effect(KILL cr); @@ -8664,20 +8618,6 @@ instruct mulI_mem_imm(rRegI dst, memory src, immI imm, rFlagsReg cr) ins_pipe(ialu_reg_mem_alu0); %} -instruct mulI_rReg_mem_imm(rRegI dst, memory src1, immI src2, rFlagsReg cr) -%{ - predicate(UseAPX); - match(Set dst (MulI (LoadI src1) src2)); - effect(KILL cr); - - ins_cost(300); - format %{ "eimull $dst, $src1, $src2\t# int ndd" %} - ins_encode %{ - __ eimull($dst$$Register, $src1$$Address, $src2$$constant, false); - %} - ins_pipe(ialu_reg_mem_alu0); -%} - instruct mulAddS2I_rReg(rRegI dst, rRegI src1, rRegI src2, rRegI src3, rFlagsReg cr) %{ match(Set dst (MulAddS2I (Binary dst src1) (Binary src2 src3))); @@ -8718,7 +8658,6 @@ instruct mulL_rReg_ndd(rRegL dst, rRegL src1, rRegL src2, rFlagsReg cr) instruct mulL_rReg_imm(rRegL dst, rRegL src, immL32 imm, rFlagsReg cr) %{ - predicate(!UseAPX); match(Set dst (MulL src imm)); effect(KILL cr); @@ -8730,20 +8669,6 @@ instruct mulL_rReg_imm(rRegL dst, rRegL src, immL32 imm, rFlagsReg cr) ins_pipe(ialu_reg_reg_alu0); %} -instruct mulL_rReg_rReg_imm_ndd(rRegL dst, rRegL src1, immL32 src2, rFlagsReg cr) -%{ - predicate(UseAPX); - match(Set dst (MulL src1 src2)); - effect(KILL cr); - - ins_cost(300); - format %{ "eimulq $dst, $src1, $src2\t# long ndd" %} - ins_encode %{ - __ eimulq($dst$$Register, $src1$$Register, $src2$$constant, false); - %} - ins_pipe(ialu_reg_reg_alu0); -%} - instruct mulL_mem(rRegL dst, memory src, rFlagsReg cr) %{ predicate(!UseAPX); @@ -8774,7 +8699,6 @@ instruct mulL_rReg_rReg_mem_ndd(rRegL dst, rRegL src1, memory src2, rFlagsReg cr instruct mulL_mem_imm(rRegL dst, memory src, immL32 imm, rFlagsReg cr) %{ - predicate(!UseAPX); match(Set dst (MulL (LoadL src) imm)); effect(KILL cr); @@ -8786,20 +8710,6 @@ instruct mulL_mem_imm(rRegL dst, memory src, immL32 imm, rFlagsReg cr) ins_pipe(ialu_reg_mem_alu0); %} -instruct mulL_rReg_mem_imm_ndd(rRegL dst, memory src1, immL32 src2, rFlagsReg cr) -%{ - predicate(UseAPX); - match(Set dst (MulL (LoadL src1) src2)); - effect(KILL cr); - - ins_cost(300); - format %{ "eimulq $dst, $src1, $src2\t# long ndd" %} - ins_encode %{ - __ eimulq($dst$$Register, $src1$$Address, $src2$$constant, false); - %} - ins_pipe(ialu_reg_mem_alu0); -%} - instruct mulHiL_rReg(rdx_RegL dst, rRegL src, rax_RegL rax, rFlagsReg cr) %{ match(Set dst (MulHiL src rax)); @@ -10689,21 +10599,6 @@ instruct xorI_rReg_rReg_mem_ndd(rRegI dst, rRegI src1, memory src2, rFlagsReg cr ins_pipe(ialu_reg_mem); %} -instruct xorI_rReg_mem_rReg_ndd(rRegI dst, memory src1, rRegI src2, rFlagsReg cr) -%{ - predicate(UseAPX); - match(Set dst (XorI (LoadI src1) src2)); - effect(KILL cr); - flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag); - - ins_cost(150); - format %{ "exorl $dst, $src1, $src2\t# int ndd" %} - ins_encode %{ - __ exorl($dst$$Register, $src1$$Address, $src2$$Register, false); - %} - ins_pipe(ialu_reg_mem); -%} - // Xor Memory with Register instruct xorB_mem_rReg(memory dst, rRegI src, rFlagsReg cr) %{ @@ -10883,21 +10778,6 @@ instruct andL_rReg_rReg_mem_ndd(rRegL dst, rRegL src1, memory src2, rFlagsReg cr ins_pipe(ialu_reg_mem); %} -instruct andL_rReg_mem_rReg_ndd(rRegL dst, memory src1, rRegL src2, rFlagsReg cr) -%{ - predicate(UseAPX); - match(Set dst (AndL (LoadL src1) src2)); - effect(KILL cr); - flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag); - - ins_cost(150); - format %{ "eandq $dst, $src1, $src2\t# long ndd" %} - ins_encode %{ - __ eandq($dst$$Register, $src1$$Address, $src2$$Register, false); - %} - ins_pipe(ialu_reg_mem); -%} - // And Memory with Register instruct andL_mem_rReg(memory dst, rRegL src, rFlagsReg cr) %{ @@ -11393,21 +11273,6 @@ instruct xorL_rReg_rReg_mem_ndd(rRegL dst, rRegL src1, memory src2, rFlagsReg cr ins_pipe(ialu_reg_mem); %} -instruct xorL_rReg_mem_rReg_ndd(rRegL dst, memory src1, rRegL src2, rFlagsReg cr) -%{ - predicate(UseAPX); - match(Set dst (XorL (LoadL src1) src2)); - effect(KILL cr); - flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag); - - ins_cost(150); - format %{ "exorq $dst, $src1, $src2\t# long ndd" %} - ins_encode %{ - __ exorq($dst$$Register, $src1$$Address, $src2$$Register, false); - %} - ins_pipe(ialu_reg_mem); -%} - // Xor Memory with Register instruct xorL_mem_rReg(memory dst, rRegL src, rFlagsReg cr) %{ diff --git a/test/hotspot/gtest/x86/asmtest.out.h b/test/hotspot/gtest/x86/asmtest.out.h index ac4a8a21aeb..a2071bafc20 100644 --- a/test/hotspot/gtest/x86/asmtest.out.h +++ b/test/hotspot/gtest/x86/asmtest.out.h @@ -191,547 +191,765 @@ __ emull(Address(r22, r10, (Address::ScaleFactor)1, -0x3d379b56), false); // {EVEX}mul dword ptr [r22+r10*2-0x3d379b56] IID177 __ emull(Address(r11, -0x3249efaf), true); // {NF}mul dword ptr [r11-0x3249efaf] IID178 __ elzcntl(r9, r16, false); // {EVEX}lzcnt r9d, r16d IID179 - __ elzcntl(r23, r28, true); // {NF}lzcnt r23d, r28d IID180 - __ enegl(r8, r30, false); // {EVEX}neg r8d, r30d IID181 - __ enegl(r23, r11, true); // {NF}neg r23d, r11d IID182 - __ epopcntl(r13, r16, false); // {EVEX}popcnt r13d, r16d IID183 - __ epopcntl(r11, r11, true); // {NF}popcnt r11d, r11d IID184 - __ enotl(r26, rcx); // {EVEX}not r26d, ecx IID185 - __ eroll(rbx, r10, false); // {EVEX}rol ebx, r10d, cl IID186 - __ eroll(r14, r29, true); // {NF}rol r14d, r29d, cl IID187 - __ erorl(r15, r20, false); // {EVEX}ror r15d, r20d, cl IID188 - __ erorl(r17, r12, true); // {NF}ror r17d, r12d, cl IID189 - __ esall(r12, rbx, false); // {EVEX}sal r12d, ebx, cl IID190 - __ esall(r23, r27, true); // {NF}sal r23d, r27d, cl IID191 - __ esarl(r29, r20, false); // {EVEX}sar r29d, r20d, cl IID192 - __ esarl(r28, rdx, true); // {NF}sar r28d, edx, cl IID193 - __ edecl(r8, r27, false); // {EVEX}dec r8d, r27d IID194 - __ edecl(rbx, r15, true); // {NF}dec ebx, r15d IID195 - __ eincl(r11, r27, false); // {EVEX}inc r11d, r27d IID196 - __ eincl(r29, r25, true); // {NF}inc r29d, r25d IID197 - __ eshll(r12, r8, false); // {EVEX}shl r12d, r8d, cl IID198 - __ eshll(r11, r18, true); // {NF}shl r11d, r18d, cl IID199 - __ eshrl(rdx, r13, false); // {EVEX}shr edx, r13d, cl IID200 - __ eshrl(r23, r24, true); // {NF}shr r23d, r24d, cl IID201 - __ etzcntl(r15, r15, false); // {EVEX}tzcnt r15d, r15d IID202 - __ etzcntl(r26, r28, true); // {NF}tzcnt r26d, r28d IID203 - __ elzcntl(rbx, Address(r25, r14, (Address::ScaleFactor)0, +0x1c13fdb6), false); // {EVEX}lzcnt ebx, dword ptr [r25+r14*1+0x1c13fdb6] IID204 - __ elzcntl(r9, Address(r31, r28, (Address::ScaleFactor)3, -0x30bf8b7f), true); // {NF}lzcnt r9d, dword ptr [r31+r28*8-0x30bf8b7f] IID205 - __ enegl(r8, Address(r25, -0x9c80fe2), false); // {EVEX}neg r8d, dword ptr [r25-0x9c80fe2] IID206 - __ enegl(r22, Address(r27, r19, (Address::ScaleFactor)2, +0x38f27c09), true); // {NF}neg r22d, dword ptr [r27+r19*4+0x38f27c09] IID207 - __ epopcntl(r21, Address(r14, r30, (Address::ScaleFactor)2, +0x39f92c7b), false); // {EVEX}popcnt r21d, dword ptr [r14+r30*4+0x39f92c7b] IID208 - __ epopcntl(r26, Address(r23, r14, (Address::ScaleFactor)3, -0x602e1b3d), true); // {NF}popcnt r26d, dword ptr [r23+r14*8-0x602e1b3d] IID209 - __ esall(r25, Address(r28, r23, (Address::ScaleFactor)1, +0x4ff120ef), false); // {EVEX}sal r25d, dword ptr [r28+r23*2+0x4ff120ef], cl IID210 - __ esall(r29, Address(r24, r16, (Address::ScaleFactor)3, -0x6821bb43), true); // {NF}sal r29d, dword ptr [r24+r16*8-0x6821bb43], cl IID211 - __ esarl(r23, Address(r11, r31, (Address::ScaleFactor)2, +0x7f4224bb), false); // {EVEX}sar r23d, dword ptr [r11+r31*4+0x7f4224bb], cl IID212 - __ esarl(r12, Address(r23, r31, (Address::ScaleFactor)1, -0x28f87a8), true); // {NF}sar r12d, dword ptr [r23+r31*2-0x28f87a8], cl IID213 - __ edecl(r19, Address(r16, r30, (Address::ScaleFactor)1, -0x27b89e0d), false); // {EVEX}dec r19d, dword ptr [r16+r30*2-0x27b89e0d] IID214 - __ edecl(r26, Address(r25, +0x3d145d48), true); // {NF}dec r26d, dword ptr [r25+0x3d145d48] IID215 - __ eincl(r13, Address(r27, r24, (Address::ScaleFactor)1, +0x625f3862), false); // {EVEX}inc r13d, dword ptr [r27+r24*2+0x625f3862] IID216 - __ eincl(r11, Address(r22, +0x765904a6), true); // {NF}inc r11d, dword ptr [r22+0x765904a6] IID217 - __ eshrl(r25, Address(rdx, r17, (Address::ScaleFactor)1, -0x7d50376f), false); // {EVEX}shr r25d, dword ptr [rdx+r17*2-0x7d50376f], cl IID218 - __ eshrl(r22, Address(r12, -0x50325da9), true); // {NF}shr r22d, dword ptr [r12-0x50325da9], cl IID219 - __ etzcntl(r13, Address(r13, r20, (Address::ScaleFactor)0, -0xbf3e86c), false); // {EVEX}tzcnt r13d, dword ptr [r13+r20*1-0xbf3e86c] IID220 - __ etzcntl(r26, Address(r14, r19, (Address::ScaleFactor)1, -0x24c59cb9), true); // {NF}tzcnt r26d, dword ptr [r14+r19*2-0x24c59cb9] IID221 - __ eaddl(r22, Address(r27, r31, (Address::ScaleFactor)2, -0x7f80902f), 1048576, false); // {EVEX}add r22d, dword ptr [r27+r31*4-0x7f80902f], 1048576 IID222 - __ eaddl(r31, Address(rdx, r21, (Address::ScaleFactor)3, -0x557cc036), 268435456, true); // {NF}add r31d, dword ptr [rdx+r21*8-0x557cc036], 268435456 IID223 - __ eandl(r10, Address(r26, +0x4e6bebf9), 4096, false); // {EVEX}and r10d, dword ptr [r26+0x4e6bebf9], 4096 IID224 - __ eandl(r13, Address(r30, +0x14f1a5fd), 256, true); // {NF}and r13d, dword ptr [r30+0x14f1a5fd], 256 IID225 - __ eimull(r27, Address(r29, r8, (Address::ScaleFactor)0, +0x37988799), 1, false); // {EVEX}imul r27d, dword ptr [r29+r8*1+0x37988799], 1 IID226 - __ eimull(r27, Address(r9, -0x446d2dc1), 256, true); // {NF}imul r27d, dword ptr [r9-0x446d2dc1], 256 IID227 - __ eorl(r17, Address(r20, r25, (Address::ScaleFactor)0, +0x4957b5db), 16, false); // {EVEX}or r17d, dword ptr [r20+r25*1+0x4957b5db], 16 IID228 - __ eorl(r25, Address(r29, r31, (Address::ScaleFactor)1, +0x3c26a53e), 1, true); // {NF}or r25d, dword ptr [r29+r31*2+0x3c26a53e], 1 IID229 - __ eorb(r15, Address(r9, -0x25974a1e), 64, false); // {EVEX}or r15b, byte ptr [r9-0x25974a1e], 64 IID230 - __ eorb(r11, Address(r16, r15, (Address::ScaleFactor)2, +0x66a0329f), 4, true); // {NF}or r11b, byte ptr [r16+r15*4+0x66a0329f], 4 IID231 - __ esall(rcx, Address(rcx, r27, (Address::ScaleFactor)0, +0x38c6485e), 1, false); // {EVEX}sal ecx, dword ptr [rcx+r27*1+0x38c6485e], 1 IID232 - __ esall(r25, Address(r8, r10, (Address::ScaleFactor)0, +0x79131c34), 8, true); // {NF}sal r25d, dword ptr [r8+r10*1+0x79131c34], 8 IID233 - __ esarl(r13, Address(r9, r31, (Address::ScaleFactor)2, +0x12718ba9), 2, false); // {EVEX}sar r13d, dword ptr [r9+r31*4+0x12718ba9], 2 IID234 - __ esarl(r15, Address(r25, -0x505836f3), 16, true); // {NF}sar r15d, dword ptr [r25-0x505836f3], 16 IID235 - __ eshrl(r15, Address(rcx, r19, (Address::ScaleFactor)0, +0xc5c1510), 1, false); // {EVEX}shr r15d, dword ptr [rcx+r19*1+0xc5c1510], 1 IID236 - __ eshrl(r13, Address(r29, r21, (Address::ScaleFactor)2, -0x6c67309c), 8, true); // {NF}shr r13d, dword ptr [r29+r21*4-0x6c67309c], 8 IID237 - __ esubl(rbx, Address(r12, r8, (Address::ScaleFactor)1, -0x3575087f), 4096, false); // {EVEX}sub ebx, dword ptr [r12+r8*2-0x3575087f], 4096 IID238 - __ esubl(r28, Address(rbx, r21, (Address::ScaleFactor)3, -0x55f83db8), 65536, true); // {NF}sub r28d, dword ptr [rbx+r21*8-0x55f83db8], 65536 IID239 - __ exorl(r30, Address(r21, r26, (Address::ScaleFactor)0, +0x3b4d14e1), 1, false); // {EVEX}xor r30d, dword ptr [r21+r26*1+0x3b4d14e1], 1 IID240 - __ exorl(r28, Address(r18, -0x452348a1), 16777216, true); // {NF}xor r28d, dword ptr [r18-0x452348a1], 16777216 IID241 - __ eaddl(r18, Address(rdx, r10, (Address::ScaleFactor)2, -0x161e1d47), r16, false); // {EVEX}add r18d, dword ptr [rdx+r10*4-0x161e1d47], r16d IID242 - __ eaddl(r27, Address(r25, r18, (Address::ScaleFactor)3, -0x679bb823), rdx, true); // {NF}add r27d, dword ptr [r25+r18*8-0x679bb823], edx IID243 - __ eorl(r27, Address(r31, r29, (Address::ScaleFactor)3, +0x19ed7934), r9, false); // {EVEX}or r27d, dword ptr [r31+r29*8+0x19ed7934], r9d IID244 - __ eorl(r22, Address(r8, r16, (Address::ScaleFactor)2, -0x1bf71f78), r17, true); // {NF}or r22d, dword ptr [r8+r16*4-0x1bf71f78], r17d IID245 - __ eorb(rcx, Address(r15, r28, (Address::ScaleFactor)3, -0x6a4a3934), r16, false); // {EVEX}or cl, byte ptr [r15+r28*8-0x6a4a3934], r16b IID246 - __ eorb(r28, Address(r23, r12, (Address::ScaleFactor)2, +0x3c2449f7), r16, true); // {NF}or r28b, byte ptr [r23+r12*4+0x3c2449f7], r16b IID247 - __ esubl(r22, Address(r27, r10, (Address::ScaleFactor)1, -0x3c29396f), r9, false); // {EVEX}sub r22d, dword ptr [r27+r10*2-0x3c29396f], r9d IID248 - __ esubl(r10, Address(r16, -0x165064ff), r17, true); // {NF}sub r10d, dword ptr [r16-0x165064ff], r17d IID249 - __ exorl(r28, Address(r30, r11, (Address::ScaleFactor)0, +0x17281e3a), r20, false); // {EVEX}xor r28d, dword ptr [r30+r11*1+0x17281e3a], r20d IID250 - __ exorl(rdx, Address(rbx, r31, (Address::ScaleFactor)3, +0x7753d0dc), r17, true); // {NF}xor edx, dword ptr [rbx+r31*8+0x7753d0dc], r17d IID251 - __ exorb(r9, Address(r31, +0x72a4f58e), r30, false); // {EVEX}xor r9b, byte ptr [r31+0x72a4f58e], r30b IID252 - __ exorb(r24, Address(r25, r15, (Address::ScaleFactor)0, +0x20fc1a0a), r16, true); // {NF}xor r24b, byte ptr [r25+r15*1+0x20fc1a0a], r16b IID253 - __ eaddl(r12, rbx, 65536, false); // {EVEX}add r12d, ebx, 65536 IID254 - __ eaddl(rax, r11, 65536, false); // {EVEX}add eax, r11d, 65536 IID255 - __ eaddl(r24, r16, 268435456, true); // {NF}add r24d, r16d, 268435456 IID256 - __ eaddl(rax, r18, 268435456, true); // {NF}add eax, r18d, 268435456 IID257 - __ eandl(r29, r13, 1, false); // {EVEX}and r29d, r13d, 1 IID258 - __ eandl(rax, r13, 1, false); // {EVEX}and eax, r13d, 1 IID259 - __ eandl(r31, r22, 1, true); // {NF}and r31d, r22d, 1 IID260 - __ eandl(rax, r29, 1, true); // {NF}and eax, r29d, 1 IID261 - __ eimull(r23, r29, 65536, false); // {EVEX}imul r23d, r29d, 65536 IID262 - __ eimull(rax, r15, 65536, false); // {EVEX}imul eax, r15d, 65536 IID263 - __ eimull(r21, r9, 268435456, true); // {NF}imul r21d, r9d, 268435456 IID264 - __ eimull(rax, r15, 268435456, true); // {NF}imul eax, r15d, 268435456 IID265 - __ eorl(rdx, r18, 65536, false); // {EVEX}or edx, r18d, 65536 IID266 - __ eorl(rax, r15, 65536, false); // {EVEX}or eax, r15d, 65536 IID267 - __ eorl(r8, r9, 256, true); // {NF}or r8d, r9d, 256 IID268 - __ eorl(rax, r27, 256, true); // {NF}or eax, r27d, 256 IID269 - __ ercll(r9, r15, 8); // {EVEX}rcl r9d, r15d, 8 IID270 - __ ercll(rax, r18, 8); // {EVEX}rcl eax, r18d, 8 IID271 - __ eroll(r12, rbx, 16, false); // {EVEX}rol r12d, ebx, 16 IID272 - __ eroll(rax, r19, 16, false); // {EVEX}rol eax, r19d, 16 IID273 - __ eroll(r10, r11, 16, true); // {NF}rol r10d, r11d, 16 IID274 - __ eroll(rax, r18, 16, true); // {NF}rol eax, r18d, 16 IID275 - __ erorl(rdx, r14, 1, false); // {EVEX}ror edx, r14d, 1 IID276 - __ erorl(rax, r22, 1, false); // {EVEX}ror eax, r22d, 1 IID277 - __ erorl(r25, r31, 16, true); // {NF}ror r25d, r31d, 16 IID278 - __ erorl(rax, r19, 16, true); // {NF}ror eax, r19d, 16 IID279 - __ esall(r9, r15, 2, false); // {EVEX}sal r9d, r15d, 2 IID280 - __ esall(rax, r13, 2, false); // {EVEX}sal eax, r13d, 2 IID281 - __ esall(r21, r16, 1, true); // {NF}sal r21d, r16d, 1 IID282 - __ esall(rax, r21, 1, true); // {NF}sal eax, r21d, 1 IID283 - __ esarl(r26, r23, 8, false); // {EVEX}sar r26d, r23d, 8 IID284 - __ esarl(rax, r28, 8, false); // {EVEX}sar eax, r28d, 8 IID285 - __ esarl(r26, r14, 4, true); // {NF}sar r26d, r14d, 4 IID286 - __ esarl(rax, r10, 4, true); // {NF}sar eax, r10d, 4 IID287 - __ eshll(r22, r9, 1, false); // {EVEX}shl r22d, r9d, 1 IID288 - __ eshll(rax, r18, 1, false); // {EVEX}shl eax, r18d, 1 IID289 - __ eshll(r30, r24, 16, true); // {NF}shl r30d, r24d, 16 IID290 - __ eshll(rax, r23, 16, true); // {NF}shl eax, r23d, 16 IID291 - __ eshrl(r11, r8, 16, false); // {EVEX}shr r11d, r8d, 16 IID292 - __ eshrl(rax, r16, 16, false); // {EVEX}shr eax, r16d, 16 IID293 - __ eshrl(r11, r12, 8, true); // {NF}shr r11d, r12d, 8 IID294 - __ eshrl(rax, r29, 8, true); // {NF}shr eax, r29d, 8 IID295 - __ esubl(r16, r21, 1048576, false); // {EVEX}sub r16d, r21d, 1048576 IID296 - __ esubl(rax, r15, 1048576, false); // {EVEX}sub eax, r15d, 1048576 IID297 - __ esubl(r9, r18, 16777216, true); // {NF}sub r9d, r18d, 16777216 IID298 + __ elzcntl(r23, r23, false); // {EVEX}lzcnt r23d, r23d IID180 + __ elzcntl(r28, r8, true); // {NF}lzcnt r28d, r8d IID181 + __ elzcntl(r30, r30, true); // {NF}lzcnt r30d, r30d IID182 + __ enegl(r23, r11, false); // {EVEX}neg r23d, r11d IID183 + __ enegl(r13, r13, false); // neg r13d IID184 + __ enegl(r16, r11, true); // {NF}neg r16d, r11d IID185 + __ enegl(r11, r11, true); // {NF}neg r11d, r11d IID186 + __ epopcntl(r26, rcx, false); // {EVEX}popcnt r26d, ecx IID187 #endif // _LP64 - __ esubl(rax, rbx, 16777216, true); // {NF}sub eax, ebx, 16777216 IID299 + __ epopcntl(rbx, rbx, false); // {EVEX}popcnt ebx, ebx IID188 #ifdef _LP64 - __ exorl(r19, r23, 65536, false); // {EVEX}xor r19d, r23d, 65536 IID300 - __ exorl(rax, r17, 65536, false); // {EVEX}xor eax, r17d, 65536 IID301 - __ exorl(r29, r18, 1048576, true); // {NF}xor r29d, r18d, 1048576 IID302 - __ exorl(rax, r14, 1048576, true); // {NF}xor eax, r14d, 1048576 IID303 - __ esubl_imm32(r19, r15, 16777216, false); // {EVEX}sub r19d, r15d, 16777216 IID304 - __ esubl_imm32(rax, r27, 16777216, false); // {EVEX}sub eax, r27d, 16777216 IID305 - __ esubl_imm32(r23, r27, 1073741824, true); // {NF}sub r23d, r27d, 1073741824 IID306 - __ esubl_imm32(rax, r23, 1073741824, true); // {NF}sub eax, r23d, 1073741824 IID307 - __ eaddl(r8, r12, Address(r28, r24, (Address::ScaleFactor)3, -0x6d6d7e68), false); // {EVEX}add r8d, r12d, dword ptr [r28+r24*8-0x6d6d7e68] IID308 - __ eaddl(r24, r13, Address(r24, r25, (Address::ScaleFactor)3, +0x784673fd), true); // {NF}add r24d, r13d, dword ptr [r24+r25*8+0x784673fd] IID309 - __ eandl(r24, r21, Address(r8, r13, (Address::ScaleFactor)2, -0x63663889), false); // {EVEX}and r24d, r21d, dword ptr [r8+r13*4-0x63663889] IID310 - __ eandl(r12, r24, Address(r30, -0x67526556), true); // {NF}and r12d, r24d, dword ptr [r30-0x67526556] IID311 - __ eimull(r13, r13, Address(rbx, r25, (Address::ScaleFactor)2, -0x5f394dd9), false); // {EVEX}imul r13d, r13d, dword ptr [rbx+r25*4-0x5f394dd9] IID312 - __ eimull(r26, r25, Address(r25, rdx, (Address::ScaleFactor)3, -0x2e39f79a), true); // {NF}imul r26d, r25d, dword ptr [r25+rdx*8-0x2e39f79a] IID313 - __ eorl(r28, r8, Address(rdx, r24, (Address::ScaleFactor)3, -0xed99a54), false); // {EVEX}or r28d, r8d, dword ptr [rdx+r24*8-0xed99a54] IID314 - __ eorl(r31, r22, Address(r30, r20, (Address::ScaleFactor)3, +0x3ac41cbd), true); // {NF}or r31d, r22d, dword ptr [r30+r20*8+0x3ac41cbd] IID315 - __ esubl(r24, r30, Address(r13, r17, (Address::ScaleFactor)1, +0x1efdc2e3), false); // {EVEX}sub r24d, r30d, dword ptr [r13+r17*2+0x1efdc2e3] IID316 - __ esubl(r16, r16, Address(r9, r15, (Address::ScaleFactor)1, +0x769feb34), true); // {NF}sub r16d, r16d, dword ptr [r9+r15*2+0x769feb34] IID317 - __ exorl(r19, r25, Address(r10, +0x2239b429), false); // {EVEX}xor r19d, r25d, dword ptr [r10+0x2239b429] IID318 - __ exorl(r25, r19, Address(r16, r24, (Address::ScaleFactor)1, +0x1c71faea), true); // {NF}xor r25d, r19d, dword ptr [r16+r24*2+0x1c71faea] IID319 - __ exorb(r19, r10, Address(r28, -0x299a0cfd), false); // {EVEX}xor r19b, r10b, byte ptr [r28-0x299a0cfd] IID320 - __ exorb(rbx, r28, Address(r23, r24, (Address::ScaleFactor)1, -0x5d78ddd9), true); // {NF}xor bl, r28b, byte ptr [r23+r24*2-0x5d78ddd9] IID321 - __ exorw(r10, r9, Address(r13, r30, (Address::ScaleFactor)2, +0x11151188), false); // {EVEX}xor r10w, r9w, word ptr [r13+r30*4+0x11151188] IID322 - __ exorw(r16, r17, Address(rdx, r31, (Address::ScaleFactor)0, +0x61936ce7), true); // {NF}xor r16w, r17w, word ptr [rdx+r31*1+0x61936ce7] IID323 - __ eaddl(r13, rbx, r28, false); // {load}{EVEX}add r13d, ebx, r28d IID324 - __ eaddl(rbx, r29, r22, true); // {load}{NF}add ebx, r29d, r22d IID325 - __ eandl(rbx, r8, r8, false); // {load}{EVEX}and ebx, r8d, r8d IID326 - __ eandl(r11, r16, r13, true); // {load}{NF}and r11d, r16d, r13d IID327 - __ eimull(r12, r15, r17, false); // {load}{EVEX}imul r12d, r15d, r17d IID328 - __ eimull(r23, r31, r20, true); // {load}{NF}imul r23d, r31d, r20d IID329 - __ eorw(r22, r26, r10, false); // {load}{EVEX}or r22w, r26w, r10w IID330 - __ eorw(r25, r19, r11, true); // {load}{NF}or r25w, r19w, r11w IID331 - __ eorl(r19, r30, r8, false); // {load}{EVEX}or r19d, r30d, r8d IID332 - __ eorl(r12, r10, rdx, true); // {load}{NF}or r12d, r10d, edx IID333 - __ eshldl(r22, r20, r30, false); // {load}{EVEX}shld r22d, r20d, r30d, cl IID334 - __ eshldl(r18, r19, r18, true); // {load}{NF}shld r18d, r19d, r18d, cl IID335 - __ eshrdl(r25, r18, rcx, false); // {load}{EVEX}shrd r25d, r18d, ecx, cl IID336 - __ eshrdl(r19, r16, r25, true); // {load}{NF}shrd r19d, r16d, r25d, cl IID337 - __ esubl(r11, r31, r24, false); // {load}{EVEX}sub r11d, r31d, r24d IID338 - __ esubl(r14, r30, r16, true); // {load}{NF}sub r14d, r30d, r16d IID339 - __ exorl(r9, r11, r26, false); // {load}{EVEX}xor r9d, r11d, r26d IID340 - __ exorl(r27, rdx, r31, true); // {load}{NF}xor r27d, edx, r31d IID341 - __ eshldl(r29, r10, rcx, 16, false); // {EVEX}shld r29d, r10d, ecx, 16 IID342 - __ eshldl(r15, r23, r17, 16, true); // {NF}shld r15d, r23d, r17d, 16 IID343 - __ eshrdl(r27, r13, r15, 8, false); // {EVEX}shrd r27d, r13d, r15d, 8 IID344 - __ eshrdl(r15, r29, r26, 16, true); // {NF}shrd r15d, r29d, r26d, 16 IID345 - __ ecmovl (Assembler::Condition::overflow, r18, r9, r9); // cmovo r18d, r9d, r9d IID346 - __ ecmovl (Assembler::Condition::noOverflow, r22, r30, r23); // cmovno r22d, r30d, r23d IID347 - __ ecmovl (Assembler::Condition::below, r11, r20, r11); // cmovb r11d, r20d, r11d IID348 - __ ecmovl (Assembler::Condition::aboveEqual, rbx, r28, r16); // cmovae ebx, r28d, r16d IID349 - __ ecmovl (Assembler::Condition::zero, r20, r17, r24); // cmovz r20d, r17d, r24d IID350 - __ ecmovl (Assembler::Condition::notZero, r22, r16, r15); // cmovnz r22d, r16d, r15d IID351 - __ ecmovl (Assembler::Condition::belowEqual, r15, r28, r29); // cmovbe r15d, r28d, r29d IID352 - __ ecmovl (Assembler::Condition::above, r16, r25, r25); // cmova r16d, r25d, r25d IID353 - __ ecmovl (Assembler::Condition::negative, r17, r13, r17); // cmovs r17d, r13d, r17d IID354 - __ ecmovl (Assembler::Condition::positive, r23, rbx, r30); // cmovns r23d, ebx, r30d IID355 - __ ecmovl (Assembler::Condition::parity, r15, r22, r11); // cmovp r15d, r22d, r11d IID356 - __ ecmovl (Assembler::Condition::noParity, r27, rdx, r22); // cmovnp r27d, edx, r22d IID357 - __ ecmovl (Assembler::Condition::less, r9, r17, r28); // cmovl r9d, r17d, r28d IID358 - __ ecmovl (Assembler::Condition::greaterEqual, r24, r11, r26); // cmovge r24d, r11d, r26d IID359 - __ ecmovl (Assembler::Condition::lessEqual, r12, rcx, rbx); // cmovle r12d, ecx, ebx IID360 - __ ecmovl (Assembler::Condition::greater, r28, r22, r22); // cmovg r28d, r22d, r22d IID361 - __ ecmovl (Assembler::Condition::overflow, r10, r14, Address(rcx, r17, (Address::ScaleFactor)3, -0x7857b23d)); // cmovo r10d, r14d, dword ptr [rcx+r17*8-0x7857b23d] IID362 - __ ecmovl (Assembler::Condition::noOverflow, r17, r12, Address(r26, r24, (Address::ScaleFactor)3, +0x10642223)); // cmovno r17d, r12d, dword ptr [r26+r24*8+0x10642223] IID363 - __ ecmovl (Assembler::Condition::below, r26, r8, Address(r31, -0xb2d2be4)); // cmovb r26d, r8d, dword ptr [r31-0xb2d2be4] IID364 - __ ecmovl (Assembler::Condition::aboveEqual, r12, r20, Address(r12, r22, (Address::ScaleFactor)2, -0x667ff72b)); // cmovae r12d, r20d, dword ptr [r12+r22*4-0x667ff72b] IID365 - __ ecmovl (Assembler::Condition::zero, r22, r9, Address(r27, r23, (Address::ScaleFactor)2, +0x66ce4d22)); // cmovz r22d, r9d, dword ptr [r27+r23*4+0x66ce4d22] IID366 - __ ecmovl (Assembler::Condition::notZero, r12, r8, Address(r30, r27, (Address::ScaleFactor)3, -0x2b9676e1)); // cmovnz r12d, r8d, dword ptr [r30+r27*8-0x2b9676e1] IID367 - __ ecmovl (Assembler::Condition::belowEqual, r17, r20, Address(r9, r30, (Address::ScaleFactor)3, -0x351022df)); // cmovbe r17d, r20d, dword ptr [r9+r30*8-0x351022df] IID368 - __ ecmovl (Assembler::Condition::above, rdx, r8, Address(r14, +0x3d6b7a59)); // cmova edx, r8d, dword ptr [r14+0x3d6b7a59] IID369 - __ ecmovl (Assembler::Condition::negative, rcx, r31, Address(r11, r14, (Address::ScaleFactor)2, +0x2cd585f2)); // cmovs ecx, r31d, dword ptr [r11+r14*4+0x2cd585f2] IID370 - __ ecmovl (Assembler::Condition::positive, r25, r18, Address(r24, r11, (Address::ScaleFactor)2, -0x3f699c34)); // cmovns r25d, r18d, dword ptr [r24+r11*4-0x3f699c34] IID371 - __ ecmovl (Assembler::Condition::parity, r18, r8, Address(r19, r17, (Address::ScaleFactor)2, -0x390da4c5)); // cmovp r18d, r8d, dword ptr [r19+r17*4-0x390da4c5] IID372 - __ ecmovl (Assembler::Condition::noParity, r11, r29, Address(r29, rdx, (Address::ScaleFactor)2, +0x3a94a93f)); // cmovnp r11d, r29d, dword ptr [r29+rdx*4+0x3a94a93f] IID373 - __ ecmovl (Assembler::Condition::less, r13, r29, Address(r15, r23, (Address::ScaleFactor)1, +0x76d43532)); // cmovl r13d, r29d, dword ptr [r15+r23*2+0x76d43532] IID374 - __ ecmovl (Assembler::Condition::greaterEqual, r15, r12, Address(r13, r9, (Address::ScaleFactor)1, +0x16f7a5b)); // cmovge r15d, r12d, dword ptr [r13+r9*2+0x16f7a5b] IID375 - __ ecmovl (Assembler::Condition::lessEqual, r9, rdx, Address(r17, r23, (Address::ScaleFactor)1, +0x43b6bfe1)); // cmovle r9d, edx, dword ptr [r17+r23*2+0x43b6bfe1] IID376 - __ ecmovl (Assembler::Condition::greater, r28, r20, Address(r24, r10, (Address::ScaleFactor)0, -0x326e802f)); // cmovg r28d, r20d, dword ptr [r24+r10*1-0x326e802f] IID377 + __ epopcntl(r10, r14, true); // {NF}popcnt r10d, r14d IID189 + __ epopcntl(r29, r29, true); // {NF}popcnt r29d, r29d IID190 + __ enotl(r15, r20); // {EVEX}not r15d, r20d IID191 + __ enotl(r17, r17); // not r17d IID192 + __ eroll(r12, r12, false); // rol r12d, cl IID193 +#endif // _LP64 + __ eroll(rbx, rbx, false); // rol ebx, cl IID194 +#ifdef _LP64 + __ eroll(r23, r27, true); // {NF}rol r23d, r27d, cl IID195 + __ eroll(r29, r29, true); // {NF}rol r29d, r29d, cl IID196 + __ erorl(r20, r28, false); // {EVEX}ror r20d, r28d, cl IID197 +#endif // _LP64 + __ erorl(rdx, rdx, false); // ror edx, cl IID198 +#ifdef _LP64 + __ erorl(r8, r27, true); // {NF}ror r8d, r27d, cl IID199 +#endif // _LP64 + __ erorl(rbx, rbx, true); // {NF}ror ebx, ebx, cl IID200 +#ifdef _LP64 + __ esall(r15, r11, false); // {EVEX}sal r15d, r11d, cl IID201 + __ esall(r27, r27, false); // sal r27d, cl IID202 + __ esall(r29, r25, true); // {NF}sal r29d, r25d, cl IID203 + __ esall(r12, r12, true); // {NF}sal r12d, r12d, cl IID204 + __ esarl(r8, r11, false); // {EVEX}sar r8d, r11d, cl IID205 + __ esarl(r18, r18, false); // sar r18d, cl IID206 + __ esarl(rdx, r13, true); // {NF}sar edx, r13d, cl IID207 + __ esarl(r23, r23, true); // {NF}sar r23d, r23d, cl IID208 + __ edecl(r24, r15, false); // {EVEX}dec r24d, r15d IID209 + __ edecl(r15, r15, false); // dec r15d IID210 + __ edecl(r26, r28, true); // {NF}dec r26d, r28d IID211 +#endif // _LP64 + __ edecl(rbx, rbx, true); // {NF}dec ebx, ebx IID212 +#ifdef _LP64 + __ eincl(r25, r14, false); // {EVEX}inc r25d, r14d IID213 + __ eincl(r12, r12, false); // inc r12d IID214 + __ eincl(rcx, r23, true); // {NF}inc ecx, r23d IID215 + __ eincl(r29, r29, true); // {NF}inc r29d, r29d IID216 + __ eshll(r22, r24, false); // {EVEX}shl r22d, r24d, cl IID217 + __ eshll(r15, r15, false); // shl r15d, cl IID218 + __ eshll(r9, r31, true); // {NF}shl r9d, r31d, cl IID219 + __ eshll(r28, r28, true); // {NF}shl r28d, r28d, cl IID220 + __ eshrl(r21, r18, false); // {EVEX}shr r21d, r18d, cl IID221 + __ eshrl(r24, r24, false); // shr r24d, cl IID222 + __ eshrl(r14, r19, true); // {NF}shr r14d, r19d, cl IID223 + __ eshrl(r8, r8, true); // {NF}shr r8d, r8d, cl IID224 + __ etzcntl(r25, r9, false); // {EVEX}tzcnt r25d, r9d IID225 + __ etzcntl(r26, r26, false); // {EVEX}tzcnt r26d, r26d IID226 + __ etzcntl(r8, r30, true); // {NF}tzcnt r8d, r30d IID227 + __ etzcntl(r26, r26, true); // {NF}tzcnt r26d, r26d IID228 + __ elzcntl(r29, Address(r25, r20, (Address::ScaleFactor)3, -0x9c80fe2), false); // {EVEX}lzcnt r29d, dword ptr [r25+r20*8-0x9c80fe2] IID229 + __ elzcntl(r22, Address(r27, r19, (Address::ScaleFactor)2, +0x38f27c09), true); // {NF}lzcnt r22d, dword ptr [r27+r19*4+0x38f27c09] IID230 + __ enegl(r21, Address(r14, r30, (Address::ScaleFactor)2, +0x39f92c7b), false); // {EVEX}neg r21d, dword ptr [r14+r30*4+0x39f92c7b] IID231 + __ enegl(r26, Address(r23, r14, (Address::ScaleFactor)3, -0x602e1b3d), true); // {NF}neg r26d, dword ptr [r23+r14*8-0x602e1b3d] IID232 + __ epopcntl(r25, Address(r28, r23, (Address::ScaleFactor)1, +0x4ff120ef), false); // {EVEX}popcnt r25d, dword ptr [r28+r23*2+0x4ff120ef] IID233 + __ epopcntl(r29, Address(r24, r16, (Address::ScaleFactor)3, -0x6821bb43), true); // {NF}popcnt r29d, dword ptr [r24+r16*8-0x6821bb43] IID234 + __ esall(r23, Address(r11, r31, (Address::ScaleFactor)2, +0x7f4224bb), false); // {EVEX}sal r23d, dword ptr [r11+r31*4+0x7f4224bb], cl IID235 + __ esall(r12, Address(r23, r31, (Address::ScaleFactor)1, -0x28f87a8), true); // {NF}sal r12d, dword ptr [r23+r31*2-0x28f87a8], cl IID236 + __ esarl(r19, Address(r16, r30, (Address::ScaleFactor)1, -0x27b89e0d), false); // {EVEX}sar r19d, dword ptr [r16+r30*2-0x27b89e0d], cl IID237 + __ esarl(r26, Address(r25, +0x3d145d48), true); // {NF}sar r26d, dword ptr [r25+0x3d145d48], cl IID238 + __ edecl(r13, Address(r27, r24, (Address::ScaleFactor)1, +0x625f3862), false); // {EVEX}dec r13d, dword ptr [r27+r24*2+0x625f3862] IID239 + __ edecl(r11, Address(r22, +0x765904a6), true); // {NF}dec r11d, dword ptr [r22+0x765904a6] IID240 + __ eincl(r25, Address(rdx, r17, (Address::ScaleFactor)1, -0x7d50376f), false); // {EVEX}inc r25d, dword ptr [rdx+r17*2-0x7d50376f] IID241 + __ eincl(r22, Address(r12, -0x50325da9), true); // {NF}inc r22d, dword ptr [r12-0x50325da9] IID242 + __ eshrl(r13, Address(r13, r20, (Address::ScaleFactor)0, -0xbf3e86c), false); // {EVEX}shr r13d, dword ptr [r13+r20*1-0xbf3e86c], cl IID243 + __ eshrl(r26, Address(r14, r19, (Address::ScaleFactor)1, -0x24c59cb9), true); // {NF}shr r26d, dword ptr [r14+r19*2-0x24c59cb9], cl IID244 + __ etzcntl(r16, Address(r22, r27, (Address::ScaleFactor)2, -0x7f80902f), false); // {EVEX}tzcnt r16d, dword ptr [r22+r27*4-0x7f80902f] IID245 + __ etzcntl(r20, Address(r31, rdx, (Address::ScaleFactor)3, +0x12254818), true); // {NF}tzcnt r20d, dword ptr [r31+rdx*8+0x12254818] IID246 + __ eaddl(r21, Address(r12, r10, (Address::ScaleFactor)3, +0x6417cf06), 1048576, false); // {EVEX}add r21d, dword ptr [r12+r10*8+0x6417cf06], 1048576 IID247 + __ eaddl(r9, Address(r13, +0x14f1a5fd), 4096, true); // {NF}add r9d, dword ptr [r13+0x14f1a5fd], 4096 IID248 + __ eandl(r27, Address(r29, r8, (Address::ScaleFactor)0, +0x37988799), 1, false); // {EVEX}and r27d, dword ptr [r29+r8*1+0x37988799], 1 IID249 + __ eandl(r27, Address(r9, -0x446d2dc1), 256, true); // {NF}and r27d, dword ptr [r9-0x446d2dc1], 256 IID250 + __ eimull(r17, Address(r20, r25, (Address::ScaleFactor)0, +0x4957b5db), 16, false); // {EVEX}imul r17d, dword ptr [r20+r25*1+0x4957b5db], 16 IID251 + __ eimull(r25, Address(r29, r31, (Address::ScaleFactor)1, +0x3c26a53e), 1, true); // {NF}imul r25d, dword ptr [r29+r31*2+0x3c26a53e], 1 IID252 + __ eorl(r15, Address(r9, -0x25974a1e), 268435456, false); // {EVEX}or r15d, dword ptr [r9-0x25974a1e], 268435456 IID253 + __ eorl(r11, Address(r16, r15, (Address::ScaleFactor)2, +0x66a0329f), 4096, true); // {NF}or r11d, dword ptr [r16+r15*4+0x66a0329f], 4096 IID254 + __ eorb(rcx, Address(rcx, r27, (Address::ScaleFactor)0, +0x38c6485e), 1, false); // {EVEX}or cl, byte ptr [rcx+r27*1+0x38c6485e], 1 IID255 + __ eorb(r25, Address(r8, r10, (Address::ScaleFactor)0, +0x79131c34), 64, true); // {NF}or r25b, byte ptr [r8+r10*1+0x79131c34], 64 IID256 + __ esall(r13, Address(r9, r31, (Address::ScaleFactor)2, +0x12718ba9), 2, false); // {EVEX}sal r13d, dword ptr [r9+r31*4+0x12718ba9], 2 IID257 + __ esall(r15, Address(r25, -0x505836f3), 16, true); // {NF}sal r15d, dword ptr [r25-0x505836f3], 16 IID258 + __ esarl(r15, Address(rcx, r19, (Address::ScaleFactor)0, +0xc5c1510), 1, false); // {EVEX}sar r15d, dword ptr [rcx+r19*1+0xc5c1510], 1 IID259 + __ esarl(r13, Address(r29, r21, (Address::ScaleFactor)2, -0x6c67309c), 8, true); // {NF}sar r13d, dword ptr [r29+r21*4-0x6c67309c], 8 IID260 + __ eshrl(r11, Address(rbx, +0x749f67d0), 16, false); // {EVEX}shr r11d, dword ptr [rbx+0x749f67d0], 16 IID261 + __ eshrl(r14, Address(r14, -0x55f83db8), 4, true); // {NF}shr r14d, dword ptr [r14-0x55f83db8], 4 IID262 + __ esubl(r30, Address(r21, r26, (Address::ScaleFactor)0, +0x3b4d14e1), 1, false); // {EVEX}sub r30d, dword ptr [r21+r26*1+0x3b4d14e1], 1 IID263 + __ esubl(r28, Address(r18, -0x452348a1), 16777216, true); // {NF}sub r28d, dword ptr [r18-0x452348a1], 16777216 IID264 + __ exorl(rdx, Address(r10, r16, (Address::ScaleFactor)2, -0x161e1d47), 16777216, false); // {EVEX}xor edx, dword ptr [r10+r16*4-0x161e1d47], 16777216 IID265 + __ exorl(rdx, Address(r29, r23, (Address::ScaleFactor)1, +0x1b34e2f8), 16777216, true); // {NF}xor edx, dword ptr [r29+r23*2+0x1b34e2f8], 16777216 IID266 + __ eaddl(r19, Address(r27, r31, (Address::ScaleFactor)0, +0x1f3ce7d8), r29, false); // {EVEX}add r19d, dword ptr [r27+r31*1+0x1f3ce7d8], r29d IID267 + __ eaddl(r28, Address(r24, rcx, (Address::ScaleFactor)3, -0x6053edc2), r28, false); // {EVEX}add r28d, dword ptr [r24+rcx*8-0x6053edc2], r28d IID268 + __ eaddl(r17, Address(r18, r24, (Address::ScaleFactor)3, -0x1bf71f78), r29, true); // {NF}add r17d, dword ptr [r18+r24*8-0x1bf71f78], r29d IID269 + __ eaddl(rcx, Address(r15, r28, (Address::ScaleFactor)1, +0x15b8216), rcx, true); // {NF}add ecx, dword ptr [r15+r28*2+0x15b8216], ecx IID270 + __ eorl(r30, Address(rbx, rdx, (Address::ScaleFactor)3, -0x463540b4), r28, false); // {EVEX}or r30d, dword ptr [rbx+rdx*8-0x463540b4], r28d IID271 + __ eorl(r18, Address(r28, r10, (Address::ScaleFactor)3, +0x3523a73b), r18, false); // {EVEX}or r18d, dword ptr [r28+r10*8+0x3523a73b], r18d IID272 + __ eorl(r9, Address(r15, r15, (Address::ScaleFactor)1, -0x2a0bdd56), r21, true); // {NF}or r9d, dword ptr [r15+r15*2-0x2a0bdd56], r21d IID273 + __ eorl(r16, Address(r23, -0x165064ff), r16, true); // {NF}or r16d, dword ptr [r23-0x165064ff], r16d IID274 + __ eorb(r28, Address(r30, r11, (Address::ScaleFactor)0, +0x17281e3a), r20, false); // {EVEX}or r28b, byte ptr [r30+r11*1+0x17281e3a], r20b IID275 + __ eorb(rdx, Address(rbx, r31, (Address::ScaleFactor)2, +0x2477b5bb), rdx, false); // {EVEX}or dl, byte ptr [rbx+r31*4+0x2477b5bb], dl IID276 + __ eorb(r16, Address(r11, rcx, (Address::ScaleFactor)1, -0x3175d1af), r24, true); // {NF}or r16b, byte ptr [r11+rcx*2-0x3175d1af], r24b IID277 + __ eorb(rbx, Address(r11, r20, (Address::ScaleFactor)3, -0x22d67bd3), rbx, true); // {NF}or bl, byte ptr [r11+r20*8-0x22d67bd3], bl IID278 + __ esubl(r26, Address(r27, r30, (Address::ScaleFactor)1, -0x3d9bce2e), rdx, false); // {EVEX}sub r26d, dword ptr [r27+r30*2-0x3d9bce2e], edx IID279 + __ esubl(r31, Address(r22, r29, (Address::ScaleFactor)1, +0x14218519), r31, false); // {EVEX}sub r31d, dword ptr [r22+r29*2+0x14218519], r31d IID280 + __ esubl(r21, Address(r9, -0x1050127a), r13, true); // {NF}sub r21d, dword ptr [r9-0x1050127a], r13d IID281 + __ esubl(r31, Address(r9, r8, (Address::ScaleFactor)0, -0xae18961), r31, true); // {NF}sub r31d, dword ptr [r9+r8*1-0xae18961], r31d IID282 + __ exorl(r15, Address(r18, +0x5c2bbce5), r12, false); // {EVEX}xor r15d, dword ptr [r18+0x5c2bbce5], r12d IID283 + __ exorl(r27, Address(r25, r23, (Address::ScaleFactor)0, +0x5c6078b3), r27, false); // {EVEX}xor r27d, dword ptr [r25+r23*1+0x5c6078b3], r27d IID284 + __ exorl(r18, Address(r8, rdx, (Address::ScaleFactor)3, -0x9ed3881), r14, true); // {NF}xor r18d, dword ptr [r8+rdx*8-0x9ed3881], r14d IID285 + __ exorl(r9, Address(r15, +0x775acdad), r9, true); // {NF}xor r9d, dword ptr [r15+0x775acdad], r9d IID286 + __ exorb(r21, Address(r18, r26, (Address::ScaleFactor)1, +0x2fe31fd5), r23, false); // {EVEX}xor r21b, byte ptr [r18+r26*2+0x2fe31fd5], r23b IID287 + __ exorb(r10, Address(r27, +0xa3150de), r10, false); // {EVEX}xor r10b, byte ptr [r27+0xa3150de], r10b IID288 + __ exorb(r18, Address(r22, r30, (Address::ScaleFactor)3, +0x1ad4e897), r24, true); // {NF}xor r18b, byte ptr [r22+r30*8+0x1ad4e897], r24b IID289 + __ exorb(r8, Address(r16, r20, (Address::ScaleFactor)0, +0x626eae82), r8, true); // {NF}xor r8b, byte ptr [r16+r20*1+0x626eae82], r8b IID290 + __ eaddl(r21, r15, 1048576, false); // {EVEX}add r21d, r15d, 1048576 IID291 + __ eaddl(rax, r18, 1048576, false); // {EVEX}add eax, r18d, 1048576 IID292 + __ eaddl(r18, r18, 256, false); // add r18d, 256 IID293 + __ eaddl(r13, r19, 16, true); // {NF}add r13d, r19d, 16 IID294 + __ eaddl(rax, r23, 16, true); // {NF}add eax, r23d, 16 IID295 + __ eaddl(r25, r25, 16777216, true); // {NF}add r25d, r25d, 16777216 IID296 + __ eandl(r29, r18, 1048576, false); // {EVEX}and r29d, r18d, 1048576 IID297 + __ eandl(rax, r14, 1048576, false); // {EVEX}and eax, r14d, 1048576 IID298 + __ eandl(r19, r19, 65536, false); // and r19d, 65536 IID299 + __ eandl(r27, r25, 1048576, true); // {NF}and r27d, r25d, 1048576 IID300 + __ eandl(rax, r20, 1048576, true); // {NF}and eax, r20d, 1048576 IID301 + __ eandl(r28, r28, 16, true); // {NF}and r28d, r28d, 16 IID302 + __ eimull(r31, r22, 4096, false); // {EVEX}imul r31d, r22d, 4096 IID303 +#endif // _LP64 + __ eimull(rax, rbx, 4096, false); // {EVEX}imul eax, ebx, 4096 IID304 +#ifdef _LP64 + __ eimull(r24, r24, 1048576, false); // {EVEX}imul r24d, r24d, 1048576 IID305 + __ eimull(r21, r16, 65536, true); // {NF}imul r21d, r16d, 65536 IID306 + __ eimull(rax, r24, 65536, true); // {NF}imul eax, r24d, 65536 IID307 + __ eimull(r13, r13, 16, true); // {NF}imul r13d, r13d, 16 IID308 + __ eorl(r29, r8, 16777216, false); // {EVEX}or r29d, r8d, 16777216 IID309 + __ eorl(rax, r12, 16777216, false); // {EVEX}or eax, r12d, 16777216 IID310 + __ eorl(r30, r30, 4096, false); // or r30d, 4096 IID311 + __ eorl(r24, rdx, 16, true); // {NF}or r24d, edx, 16 IID312 + __ eorl(rax, r8, 16, true); // {NF}or eax, r8d, 16 IID313 + __ eorl(r13, r13, 4096, true); // {NF}or r13d, r13d, 4096 IID314 + __ ercll(r25, r13, 1); // {EVEX}rcl r25d, r13d, 1 IID315 + __ ercll(rax, r18, 1); // {EVEX}rcl eax, r18d, 1 IID316 + __ ercll(r9, r9, 16); // rcl r9d, 16 IID317 + __ eroll(r26, r25, 8, false); // {EVEX}rol r26d, r25d, 8 IID318 +#endif // _LP64 + __ eroll(rax, rdx, 8, false); // {EVEX}rol eax, edx, 8 IID319 +#ifdef _LP64 + __ eroll(r24, r24, 16, false); // rol r24d, 16 IID320 + __ eroll(r24, rcx, 8, true); // {NF}rol r24d, ecx, 8 IID321 + __ eroll(rax, r30, 8, true); // {NF}rol eax, r30d, 8 IID322 + __ eroll(r28, r28, 16, true); // {NF}rol r28d, r28d, 16 IID323 + __ erorl(r17, r28, 4, false); // {EVEX}ror r17d, r28d, 4 IID324 +#endif // _LP64 + __ erorl(rax, rdx, 4, false); // {EVEX}ror eax, edx, 4 IID325 +#ifdef _LP64 + __ erorl(r8, r8, 16, false); // ror r8d, 16 IID326 + __ erorl(r19, rdx, 16, true); // {NF}ror r19d, edx, 16 IID327 + __ erorl(rax, r31, 16, true); // {NF}ror eax, r31d, 16 IID328 + __ erorl(r22, r22, 8, true); // {NF}ror r22d, r22d, 8 IID329 + __ esall(r23, r25, 16, false); // {EVEX}sal r23d, r25d, 16 IID330 + __ esall(rax, r14, 16, false); // {EVEX}sal eax, r14d, 16 IID331 + __ esall(r31, r31, 8, false); // sal r31d, 8 IID332 + __ esall(r30, r24, 2, true); // {NF}sal r30d, r24d, 2 IID333 + __ esall(rax, r29, 2, true); // {NF}sal eax, r29d, 2 IID334 + __ esall(r8, r8, 2, true); // {NF}sal r8d, r8d, 2 IID335 + __ esarl(r18, r24, 16, false); // {EVEX}sar r18d, r24d, 16 IID336 + __ esarl(rax, r13, 16, false); // {EVEX}sar eax, r13d, 16 IID337 + __ esarl(r24, r24, 1, false); // sar r24d, 1 IID338 + __ esarl(r28, r17, 16, true); // {NF}sar r28d, r17d, 16 IID339 + __ esarl(rax, r24, 16, true); // {NF}sar eax, r24d, 16 IID340 + __ esarl(r17, r17, 4, true); // {NF}sar r17d, r17d, 4 IID341 + __ eshll(r24, rcx, 4, false); // {EVEX}shl r24d, ecx, 4 IID342 + __ eshll(rax, r16, 4, false); // {EVEX}shl eax, r16d, 4 IID343 + __ eshll(r15, r15, 2, false); // shl r15d, 2 IID344 + __ eshll(r14, r27, 4, true); // {NF}shl r14d, r27d, 4 IID345 + __ eshll(rax, r23, 4, true); // {NF}shl eax, r23d, 4 IID346 + __ eshll(r30, r30, 4, true); // {NF}shl r30d, r30d, 4 IID347 + __ eshrl(r27, rdx, 2, false); // {EVEX}shr r27d, edx, 2 IID348 + __ eshrl(rax, r19, 2, false); // {EVEX}shr eax, r19d, 2 IID349 + __ eshrl(r20, r20, 2, false); // shr r20d, 2 IID350 + __ eshrl(r21, r23, 1, true); // {NF}shr r21d, r23d, 1 IID351 + __ eshrl(rax, r30, 1, true); // {NF}shr eax, r30d, 1 IID352 + __ eshrl(r25, r25, 2, true); // {NF}shr r25d, r25d, 2 IID353 + __ esubl(r24, r19, 1048576, false); // {EVEX}sub r24d, r19d, 1048576 IID354 + __ esubl(rax, r14, 1048576, false); // {EVEX}sub eax, r14d, 1048576 IID355 + __ esubl(r22, r22, 268435456, false); // sub r22d, 268435456 IID356 + __ esubl(r24, r24, 65536, true); // {NF}sub r24d, r24d, 65536 IID357 + __ esubl(rax, r14, 65536, true); // {NF}sub eax, r14d, 65536 IID358 + __ esubl(r28, r28, 268435456, true); // {NF}sub r28d, r28d, 268435456 IID359 + __ exorl(rbx, r20, 256, false); // {EVEX}xor ebx, r20d, 256 IID360 + __ exorl(rax, r15, 256, false); // {EVEX}xor eax, r15d, 256 IID361 +#endif // _LP64 + __ exorl(rbx, rbx, 4096, false); // xor ebx, 4096 IID362 +#ifdef _LP64 + __ exorl(r24, r30, 65536, true); // {NF}xor r24d, r30d, 65536 IID363 + __ exorl(rax, r31, 65536, true); // {NF}xor eax, r31d, 65536 IID364 + __ exorl(r31, r31, 4096, true); // {NF}xor r31d, r31d, 4096 IID365 + __ esubl_imm32(r20, r10, 1048576, false); // {EVEX}sub r20d, r10d, 1048576 IID366 + __ esubl_imm32(rax, r13, 1048576, false); // {EVEX}sub eax, r13d, 1048576 IID367 + __ esubl_imm32(r25, r25, 1048576, false); // sub r25d, 1048576 IID368 + __ esubl_imm32(r23, r12, 1073741824, true); // {NF}sub r23d, r12d, 1073741824 IID369 + __ esubl_imm32(rax, r16, 1073741824, true); // {NF}sub eax, r16d, 1073741824 IID370 + __ esubl_imm32(r31, r31, 65536, true); // {NF}sub r31d, r31d, 65536 IID371 + __ eaddl(r17, r13, Address(r9, +0x7fef2f98), false); // {EVEX}add r17d, r13d, dword ptr [r9+0x7fef2f98] IID372 + __ eaddl(r29, r8, Address(r22, -0x4df70aac), true); // {NF}add r29d, r8d, dword ptr [r22-0x4df70aac] IID373 + __ eandl(r13, r17, Address(r12, r15, (Address::ScaleFactor)3, +0x50a8a902), false); // {EVEX}and r13d, r17d, dword ptr [r12+r15*8+0x50a8a902] IID374 + __ eandl(r22, r25, Address(r26, r10, (Address::ScaleFactor)2, +0x70ea2754), true); // {NF}and r22d, r25d, dword ptr [r26+r10*4+0x70ea2754] IID375 + __ eimull(r19, r12, Address(r30, r8, (Address::ScaleFactor)0, +0x6a1a0a73), false); // {EVEX}imul r19d, r12d, dword ptr [r30+r8*1+0x6a1a0a73] IID376 + __ eimull(r30, r18, Address(r18, r19, (Address::ScaleFactor)2, -0x7fcd28c7), true); // {NF}imul r30d, r18d, dword ptr [r18+r19*4-0x7fcd28c7] IID377 + __ eorl(r16, r31, Address(r25, r11, (Address::ScaleFactor)3, +0x482d5dbc), false); // {EVEX}or r16d, r31d, dword ptr [r25+r11*8+0x482d5dbc] IID378 + __ eorl(r9, r27, Address(r11, +0x43d5ee01), true); // {NF}or r9d, r27d, dword ptr [r11+0x43d5ee01] IID379 + __ esubl(rcx, r23, Address(r21, r15, (Address::ScaleFactor)2, +0x2825c2bc), false); // {EVEX}sub ecx, r23d, dword ptr [r21+r15*4+0x2825c2bc] IID380 + __ esubl(r27, r22, Address(r13, r15, (Address::ScaleFactor)1, +0x771f0da7), true); // {NF}sub r27d, r22d, dword ptr [r13+r15*2+0x771f0da7] IID381 + __ exorl(r9, r30, Address(r9, r22, (Address::ScaleFactor)3, -0x4ad6c88e), false); // {EVEX}xor r9d, r30d, dword ptr [r9+r22*8-0x4ad6c88e] IID382 + __ exorl(r11, r16, Address(rbx, r28, (Address::ScaleFactor)2, +0xb0223ee), true); // {NF}xor r11d, r16d, dword ptr [rbx+r28*4+0xb0223ee] IID383 + __ exorb(r15, r29, Address(r15, r28, (Address::ScaleFactor)1, -0x1f297a69), false); // {EVEX}xor r15b, r29b, byte ptr [r15+r28*2-0x1f297a69] IID384 + __ exorb(r17, r30, Address(r23, rbx, (Address::ScaleFactor)1, +0xadc7545), true); // {NF}xor r17b, r30b, byte ptr [r23+rbx*2+0xadc7545] IID385 + __ exorw(r27, r9, Address(rdx, r22, (Address::ScaleFactor)2, -0x43d90f61), false); // {EVEX}xor r27w, r9w, word ptr [rdx+r22*4-0x43d90f61] IID386 + __ exorw(rbx, r22, Address(r28, r22, (Address::ScaleFactor)0, -0x7d30a0b1), true); // {NF}xor bx, r22w, word ptr [r28+r22*1-0x7d30a0b1] IID387 + __ eaddl(r14, r24, rcx, false); // {load}{EVEX}add r14d, r24d, ecx IID388 + __ eaddl(r8, r8, r17, false); // {load}add r8d, r17d IID389 + __ eaddl(r26, r24, r12, true); // {load}{NF}add r26d, r24d, r12d IID390 + __ eaddl(r24, r24, r23, true); // {load}{NF}add r24d, r24d, r23d IID391 + __ eandl(r13, r26, r31, false); // {load}{EVEX}and r13d, r26d, r31d IID392 + __ eandl(r11, r11, r8, false); // {load}and r11d, r8d IID393 + __ eandl(rcx, r19, r15, true); // {load}{NF}and ecx, r19d, r15d IID394 + __ eandl(r12, r12, r12, true); // {load}{NF}and r12d, r12d, r12d IID395 + __ eimull(r22, r20, r19, false); // {load}{EVEX}imul r22d, r20d, r19d IID396 + __ eimull(r8, r8, rdx, false); // {load}imul r8d, edx IID397 + __ eimull(r22, r27, r23, true); // {load}{NF}imul r22d, r27d, r23d IID398 + __ eimull(r9, r9, r18, true); // {load}{NF}imul r9d, r9d, r18d IID399 + __ eorw(rcx, r30, r13, false); // {load}{EVEX}or cx, r30w, r13w IID400 + __ eorw(r28, r28, r19, false); // {load}or r28w, r19w IID401 + __ eorw(r12, r30, r27, true); // {load}{NF}or r12w, r30w, r27w IID402 + __ eorw(r8, r8, r22, true); // {load}{NF}or r8w, r8w, r22w IID403 + __ eorl(r16, rcx, r30, false); // {load}{EVEX}or r16d, ecx, r30d IID404 + __ eorl(r10, r10, r25, false); // {load}or r10d, r25d IID405 + __ eorl(r15, r17, r17, true); // {load}{NF}or r15d, r17d, r17d IID406 + __ eorl(r9, r9, r30, true); // {load}{NF}or r9d, r9d, r30d IID407 + __ eshldl(r20, r21, r8, false); // {load}{EVEX}shld r20d, r21d, r8d, cl IID408 + __ eshldl(r26, r26, r14, false); // {load}shld r26d, r14d IID409 + __ eshldl(r16, rdx, r14, true); // {load}{NF}shld r16d, edx, r14d, cl IID410 + __ eshldl(r19, r19, r8, true); // {load}{NF}shld r19d, r19d, r8d, cl IID411 + __ eshrdl(r27, rbx, r26, false); // {load}{EVEX}shrd r27d, ebx, r26d, cl IID412 + __ eshrdl(r28, r28, r19, false); // {load}shrd r28d, r19d IID413 + __ eshrdl(rcx, r11, r14, true); // {load}{NF}shrd ecx, r11d, r14d, cl IID414 + __ eshrdl(r31, r31, r19, true); // {load}{NF}shrd r31d, r31d, r19d, cl IID415 + __ esubl(r26, r13, r25, false); // {load}{EVEX}sub r26d, r13d, r25d IID416 + __ esubl(r24, r24, r11, false); // {load}sub r24d, r11d IID417 + __ esubl(r18, r20, r13, true); // {load}{NF}sub r18d, r20d, r13d IID418 + __ esubl(r16, r16, r18, true); // {load}{NF}sub r16d, r16d, r18d IID419 + __ exorl(r19, r17, r8, false); // {load}{EVEX}xor r19d, r17d, r8d IID420 + __ exorl(r19, r19, r13, false); // {load}xor r19d, r13d IID421 + __ exorl(r23, r13, r15, true); // {load}{NF}xor r23d, r13d, r15d IID422 + __ exorl(r11, r11, r29, true); // {load}{NF}xor r11d, r11d, r29d IID423 + __ eshldl(r29, r17, r17, 1, false); // {EVEX}shld r29d, r17d, r17d, 1 IID424 + __ eshldl(r22, r22, r24, 4, false); // shld r22d, r24d, 4 IID425 + __ eshldl(r8, r28, r11, 16, true); // {NF}shld r8d, r28d, r11d, 16 IID426 + __ eshldl(r15, r15, r23, 4, true); // {NF}shld r15d, r15d, r23d, 4 IID427 + __ eshrdl(r29, r22, r16, 4, false); // {EVEX}shrd r29d, r22d, r16d, 4 IID428 + __ eshrdl(r13, r13, r9, 4, false); // shrd r13d, r9d, 4 IID429 + __ eshrdl(r15, r21, r12, 2, true); // {NF}shrd r15d, r21d, r12d, 2 IID430 + __ eshrdl(r17, r17, r23, 2, true); // {NF}shrd r17d, r17d, r23d, 2 IID431 + __ ecmovl (Assembler::Condition::overflow, rdx, r16, r29); // cmovo edx, r16d, r29d IID432 + __ ecmovl (Assembler::Condition::overflow, r10, r10, r21); // cmovo r10d, r21d IID433 + __ ecmovl (Assembler::Condition::noOverflow, r17, r29, r18); // cmovno r17d, r29d, r18d IID434 + __ ecmovl (Assembler::Condition::noOverflow, r28, r28, r24); // cmovno r28d, r24d IID435 + __ ecmovl (Assembler::Condition::below, r10, r20, r27); // cmovb r10d, r20d, r27d IID436 + __ ecmovl (Assembler::Condition::below, r10, r10, r14); // cmovb r10d, r14d IID437 + __ ecmovl (Assembler::Condition::aboveEqual, r11, r27, rcx); // cmovae r11d, r27d, ecx IID438 + __ ecmovl (Assembler::Condition::aboveEqual, r22, r22, r15); // cmovae r22d, r15d IID439 + __ ecmovl (Assembler::Condition::zero, r31, r30, r19); // cmovz r31d, r30d, r19d IID440 + __ ecmovl (Assembler::Condition::zero, r19, r19, r26); // cmovz r19d, r26d IID441 + __ ecmovl (Assembler::Condition::notZero, r21, r14, r26); // cmovnz r21d, r14d, r26d IID442 + __ ecmovl (Assembler::Condition::notZero, r20, r20, r15); // cmovnz r20d, r15d IID443 + __ ecmovl (Assembler::Condition::belowEqual, r12, r13, r23); // cmovbe r12d, r13d, r23d IID444 + __ ecmovl (Assembler::Condition::belowEqual, r28, r28, r20); // cmovbe r28d, r20d IID445 + __ ecmovl (Assembler::Condition::above, r20, r24, r11); // cmova r20d, r24d, r11d IID446 + __ ecmovl (Assembler::Condition::above, r10, r10, r15); // cmova r10d, r15d IID447 + __ ecmovl (Assembler::Condition::negative, r19, r20, r23); // cmovs r19d, r20d, r23d IID448 + __ ecmovl (Assembler::Condition::negative, r15, r15, r26); // cmovs r15d, r26d IID449 + __ ecmovl (Assembler::Condition::positive, r19, r24, r23); // cmovns r19d, r24d, r23d IID450 + __ ecmovl (Assembler::Condition::positive, r28, r28, r11); // cmovns r28d, r11d IID451 + __ ecmovl (Assembler::Condition::parity, r13, r13, rdx); // cmovp r13d, edx IID452 + __ ecmovl (Assembler::Condition::parity, r31, r31, r23); // cmovp r31d, r23d IID453 + __ ecmovl (Assembler::Condition::noParity, r23, r9, r27); // cmovnp r23d, r9d, r27d IID454 + __ ecmovl (Assembler::Condition::noParity, r21, r21, r20); // cmovnp r21d, r20d IID455 + __ ecmovl (Assembler::Condition::less, r24, r21, r29); // cmovl r24d, r21d, r29d IID456 + __ ecmovl (Assembler::Condition::less, rbx, rbx, r11); // cmovl ebx, r11d IID457 + __ ecmovl (Assembler::Condition::greaterEqual, r21, rbx, rcx); // cmovge r21d, ebx, ecx IID458 + __ ecmovl (Assembler::Condition::greaterEqual, r31, r31, r21); // cmovge r31d, r21d IID459 + __ ecmovl (Assembler::Condition::lessEqual, r15, r25, r30); // cmovle r15d, r25d, r30d IID460 + __ ecmovl (Assembler::Condition::lessEqual, r23, r23, r25); // cmovle r23d, r25d IID461 + __ ecmovl (Assembler::Condition::greater, r18, rcx, r10); // cmovg r18d, ecx, r10d IID462 + __ ecmovl (Assembler::Condition::greater, rcx, rcx, r31); // cmovg ecx, r31d IID463 + __ ecmovl (Assembler::Condition::overflow, r21, r19, Address(r26, -0x6e290873)); // cmovo r21d, r19d, dword ptr [r26-0x6e290873] IID464 + __ ecmovl (Assembler::Condition::noOverflow, r24, r19, Address(r22, rcx, (Address::ScaleFactor)0, +0x11f85f9a)); // cmovno r24d, r19d, dword ptr [r22+rcx*1+0x11f85f9a] IID465 + __ ecmovl (Assembler::Condition::below, r17, r24, Address(r20, +0x534d775e)); // cmovb r17d, r24d, dword ptr [r20+0x534d775e] IID466 + __ ecmovl (Assembler::Condition::aboveEqual, r20, r18, Address(r20, -0x47c94ecd)); // cmovae r20d, r18d, dword ptr [r20-0x47c94ecd] IID467 + __ ecmovl (Assembler::Condition::zero, r9, r13, Address(r23, -0x4b83c563)); // cmovz r9d, r13d, dword ptr [r23-0x4b83c563] IID468 + __ ecmovl (Assembler::Condition::notZero, r11, r25, Address(r24, r14, (Address::ScaleFactor)1, -0x446507af)); // cmovnz r11d, r25d, dword ptr [r24+r14*2-0x446507af] IID469 + __ ecmovl (Assembler::Condition::belowEqual, r14, r24, Address(r30, r13, (Address::ScaleFactor)2, +0xd0661d)); // cmovbe r14d, r24d, dword ptr [r30+r13*4+0xd0661d] IID470 + __ ecmovl (Assembler::Condition::above, r13, r25, Address(r14, r27, (Address::ScaleFactor)3, +0x47e1403)); // cmova r13d, r25d, dword ptr [r14+r27*8+0x47e1403] IID471 + __ ecmovl (Assembler::Condition::negative, r24, r19, Address(rcx, rdx, (Address::ScaleFactor)3, -0x644a5318)); // cmovs r24d, r19d, dword ptr [rcx+rdx*8-0x644a5318] IID472 + __ ecmovl (Assembler::Condition::positive, r26, r24, Address(r22, r22, (Address::ScaleFactor)0, +0x70352446)); // cmovns r26d, r24d, dword ptr [r22+r22*1+0x70352446] IID473 + __ ecmovl (Assembler::Condition::parity, r19, r26, Address(r8, r30, (Address::ScaleFactor)2, +0x78a12f5c)); // cmovp r19d, r26d, dword ptr [r8+r30*4+0x78a12f5c] IID474 + __ ecmovl (Assembler::Condition::noParity, r29, r11, Address(r25, r20, (Address::ScaleFactor)0, +0x27a8303a)); // cmovnp r29d, r11d, dword ptr [r25+r20*1+0x27a8303a] IID475 + __ ecmovl (Assembler::Condition::less, r22, r24, Address(r27, r16, (Address::ScaleFactor)1, +0x2541a10)); // cmovl r22d, r24d, dword ptr [r27+r16*2+0x2541a10] IID476 + __ ecmovl (Assembler::Condition::greaterEqual, r31, r15, Address(r8, r16, (Address::ScaleFactor)3, +0x558e3251)); // cmovge r31d, r15d, dword ptr [r8+r16*8+0x558e3251] IID477 + __ ecmovl (Assembler::Condition::lessEqual, r27, r18, Address(r8, r10, (Address::ScaleFactor)0, -0x471987b7)); // cmovle r27d, r18d, dword ptr [r8+r10*1-0x471987b7] IID478 + __ ecmovl (Assembler::Condition::greater, r18, r16, Address(r18, r19, (Address::ScaleFactor)2, -0x120ae81e)); // cmovg r18d, r16d, dword ptr [r18+r19*4-0x120ae81e] IID479 #endif // _LP64 #ifdef _LP64 - __ adcq(r27, rcx); // {load}adc r27, rcx IID378 - __ cmpq(r22, r15); // {load}cmp r22, r15 IID379 - __ imulq(r31, r30); // {load}imul r31, r30 IID380 - __ popcntq(r19, r19); // {load}popcnt r19, r19 IID381 - __ sbbq(r26, r21); // {load}sbb r26, r21 IID382 - __ subq(r14, r26); // {load}sub r14, r26 IID383 - __ tzcntq(r20, r15); // {load}tzcnt r20, r15 IID384 - __ lzcntq(r12, r13); // {load}lzcnt r12, r13 IID385 - __ addq(r23, r28); // {load}add r23, r28 IID386 - __ andq(r20, r20); // {load}and r20, r20 IID387 - __ orq(r24, r11); // {load}or r24, r11 IID388 - __ xorq(r10, r15); // {load}xor r10, r15 IID389 - __ movq(r19, r20); // {load}mov r19, r20 IID390 - __ bsfq(r23, r15); // {load}bsf r23, r15 IID391 - __ bsrq(r26, r19); // {load}bsr r26, r19 IID392 - __ btq(r24, r23); // {load}bt r24, r23 IID393 - __ xchgq(r28, r11); // {load}xchg r28, r11 IID394 - __ testq(r13, r13); // {load}test r13, r13 IID395 - __ addq(Address(r31, r23, (Address::ScaleFactor)3, +0x59da0437), rdx); // add qword ptr [r31+r23*8+0x59da0437], rdx IID396 - __ andq(Address(r21, r20, (Address::ScaleFactor)3, +0x6fd0d557), r27); // and qword ptr [r21+r20*8+0x6fd0d557], r27 IID397 - __ cmpq(Address(r21, +0x23ef6744), r11); // cmp qword ptr [r21+0x23ef6744], r11 IID398 - __ orq(Address(r10, rcx, (Address::ScaleFactor)3, +0x7e8544ab), rcx); // or qword ptr [r10+rcx*8+0x7e8544ab], rcx IID399 - __ xorq(Address(rcx, r24, (Address::ScaleFactor)3, -0x79ca4889), rbx); // xor qword ptr [rcx+r24*8-0x79ca4889], rbx IID400 - __ subq(Address(r27, r31, (Address::ScaleFactor)0, +0x11f85f9a), r27); // sub qword ptr [r27+r31*1+0x11f85f9a], r27 IID401 - __ movq(Address(r20, r16, (Address::ScaleFactor)3, +0x72158dda), r17); // mov qword ptr [r20+r16*8+0x72158dda], r17 IID402 - __ xaddq(Address(r29, r9, (Address::ScaleFactor)2, +0x6e8febd1), r12); // xadd qword ptr [r29+r9*4+0x6e8febd1], r12 IID403 - __ andq(Address(r15, -0x47c94ecd), 268435456); // and qword ptr [r15-0x47c94ecd], 268435456 IID404 - __ addq(Address(r23, r19, (Address::ScaleFactor)1, +0x32bfde3f), 256); // add qword ptr [r23+r19*2+0x32bfde3f], 256 IID405 - __ cmpq(Address(r15, r11, (Address::ScaleFactor)3, +0x548e7560), 4096); // cmp qword ptr [r15+r11*8+0x548e7560], 4096 IID406 - __ sarq(Address(r20, r14, (Address::ScaleFactor)1, +0x1b43fc34), 2); // sar qword ptr [r20+r14*2+0x1b43fc34], 2 IID407 - __ salq(Address(r26, r21, (Address::ScaleFactor)0, -0x3bae50c3), 8); // sal qword ptr [r26+r21*1-0x3bae50c3], 8 IID408 - __ sbbq(Address(r22, r10, (Address::ScaleFactor)3, +0x47e1403), 65536); // sbb qword ptr [r22+r10*8+0x47e1403], 65536 IID409 - __ shrq(Address(rcx, rdx, (Address::ScaleFactor)2, +0x7ea3924d), 16); // shr qword ptr [rcx+rdx*4+0x7ea3924d], 16 IID410 - __ subq(Address(rcx, r26, (Address::ScaleFactor)3, -0x356ea53e), 16); // sub qword ptr [rcx+r26*8-0x356ea53e], 16 IID411 - __ xorq(Address(r30, r26, (Address::ScaleFactor)2, +0x78a12f5c), 16); // xor qword ptr [r30+r26*4+0x78a12f5c], 16 IID412 - __ orq(Address(r11, r10, (Address::ScaleFactor)1, +0x3713b5b5), 268435456); // or qword ptr [r11+r10*2+0x3713b5b5], 268435456 IID413 - __ movq(Address(r30, r30, (Address::ScaleFactor)3, +0x2541a10), 65536); // mov qword ptr [r30+r30*8+0x2541a10], 65536 IID414 - __ testq(Address(r16, r15, (Address::ScaleFactor)3, +0x558e3251), -16); // test qword ptr [r16+r15*8+0x558e3251], -16 IID415 - __ addq(r27, Address(r8, r10, (Address::ScaleFactor)2, +0x635f732d)); // add r27, qword ptr [r8+r10*4+0x635f732d] IID416 - __ andq(r21, Address(r12, r31, (Address::ScaleFactor)0, -0x75e8c4a0)); // and r21, qword ptr [r12+r31*1-0x75e8c4a0] IID417 - __ cmpq(r18, Address(r19, r16, (Address::ScaleFactor)2, -0x120ae81e)); // cmp r18, qword ptr [r19+r16*4-0x120ae81e] IID418 - __ lzcntq(rbx, Address(r31, r30, (Address::ScaleFactor)0, +0x1ec3265d)); // lzcnt rbx, qword ptr [r31+r30*1+0x1ec3265d] IID419 - __ orq(r16, Address(rdx, r26, (Address::ScaleFactor)0, +0x3586831b)); // or r16, qword ptr [rdx+r26*1+0x3586831b] IID420 - __ adcq(r12, Address(r18, -0x3c3e9f7a)); // adc r12, qword ptr [r18-0x3c3e9f7a] IID421 - __ imulq(rcx, Address(r8, r21, (Address::ScaleFactor)3, +0x6b1515ab)); // imul rcx, qword ptr [r8+r21*8+0x6b1515ab] IID422 - __ popcntq(r29, Address(rcx, r23, (Address::ScaleFactor)2, +0x4ff06c4d)); // popcnt r29, qword ptr [rcx+r23*4+0x4ff06c4d] IID423 - __ sbbq(r26, Address(r24, r10, (Address::ScaleFactor)1, -0x75d9a189)); // sbb r26, qword ptr [r24+r10*2-0x75d9a189] IID424 - __ subq(r17, Address(rbx, rbx, (Address::ScaleFactor)0, +0x4033d59c)); // sub r17, qword ptr [rbx+rbx*1+0x4033d59c] IID425 - __ tzcntq(r18, Address(r22, r12, (Address::ScaleFactor)3, -0x3893347d)); // tzcnt r18, qword ptr [r22+r12*8-0x3893347d] IID426 - __ xorq(r12, Address(r20, r23, (Address::ScaleFactor)3, +0x4b311560)); // xor r12, qword ptr [r20+r23*8+0x4b311560] IID427 - __ movq(r29, Address(r10, r28, (Address::ScaleFactor)2, +0x5c3a2657)); // mov r29, qword ptr [r10+r28*4+0x5c3a2657] IID428 - __ leaq(r22, Address(r13, r25, (Address::ScaleFactor)3, +0x1a3d6f3f)); // lea r22, qword ptr [r13+r25*8+0x1a3d6f3f] IID429 - __ cvttsd2siq(r25, Address(r17, r24, (Address::ScaleFactor)3, -0x35addbd8)); // cvttsd2si r25, qword ptr [r17+r24*8-0x35addbd8] IID430 - __ xchgq(r18, Address(r25, +0x632184c3)); // xchg r18, qword ptr [r25+0x632184c3] IID431 - __ testq(r29, Address(r18, r13, (Address::ScaleFactor)1, -0x5039fd8a)); // test r29, qword ptr [r18+r13*2-0x5039fd8a] IID432 - __ addq(r20, 4096); // add r20, 4096 IID433 - __ andq(r9, 16); // and r9, 16 IID434 - __ adcq(rdx, 256); // adc rdx, 256 IID435 - __ cmpq(r22, 16777216); // cmp r22, 16777216 IID436 - __ rclq(r17, 1); // rcl r17, 1 IID437 - __ rcrq(r31, 1); // rcr r31, 1 IID438 - __ rolq(r27, 4); // rol r27, 4 IID439 - __ rorq(r28, 2); // ror r28, 2 IID440 - __ sarq(rcx, 16); // sar rcx, 16 IID441 - __ salq(r31, 8); // sal r31, 8 IID442 - __ sbbq(r27, 1048576); // sbb r27, 1048576 IID443 - __ shlq(r20, 16); // shl r20, 16 IID444 - __ shrq(r31, 8); // shr r31, 8 IID445 - __ subq(r27, 1048576); // sub r27, 1048576 IID446 - __ xorq(r22, 4096); // xor r22, 4096 IID447 - __ movq(r8, 4096); // mov r8, 4096 IID448 - __ mov64(r28, 1099511627776); // mov r28, 1099511627776 IID449 - __ btq(r13, 1); // bt r13, 1 IID450 - __ testq(r16, -1048576); // test r16, -1048576 IID451 - __ orq_imm32(r20, 262144); // or r20, 262144 IID452 - __ subq_imm32(r18, 1048576); // sub r18, 1048576 IID453 - __ cmovq(Assembler::Condition::overflow, rbx, Address(r29, r8, (Address::ScaleFactor)0, +0x1d022615)); // cmovo rbx, qword ptr [r29+r8*1+0x1d022615] IID454 - __ cmovq(Assembler::Condition::noOverflow, rdx, Address(r12, r28, (Address::ScaleFactor)1, -0x34c898e2)); // cmovno rdx, qword ptr [r12+r28*2-0x34c898e2] IID455 - __ cmovq(Assembler::Condition::below, r27, Address(r10, rcx, (Address::ScaleFactor)3, -0x1ef7abf1)); // cmovb r27, qword ptr [r10+rcx*8-0x1ef7abf1] IID456 - __ cmovq(Assembler::Condition::aboveEqual, r14, Address(r13, r29, (Address::ScaleFactor)2, -0x7c4c8369)); // cmovae r14, qword ptr [r13+r29*4-0x7c4c8369] IID457 - __ cmovq(Assembler::Condition::zero, r15, Address(r23, rcx, (Address::ScaleFactor)2, -0x6bd22ccf)); // cmovz r15, qword ptr [r23+rcx*4-0x6bd22ccf] IID458 - __ cmovq(Assembler::Condition::notZero, r24, Address(r15, r10, (Address::ScaleFactor)1, -0x7ffb3d09)); // cmovnz r24, qword ptr [r15+r10*2-0x7ffb3d09] IID459 - __ cmovq(Assembler::Condition::belowEqual, r23, Address(r11, +0x276a863b)); // cmovbe r23, qword ptr [r11+0x276a863b] IID460 - __ cmovq(Assembler::Condition::above, r28, Address(r29, +0x3fb4396e)); // cmova r28, qword ptr [r29+0x3fb4396e] IID461 - __ cmovq(Assembler::Condition::negative, r26, Address(r27, rcx, (Address::ScaleFactor)3, +0x4ddea61c)); // cmovs r26, qword ptr [r27+rcx*8+0x4ddea61c] IID462 - __ cmovq(Assembler::Condition::positive, r10, Address(r22, r19, (Address::ScaleFactor)1, +0x2a126966)); // cmovns r10, qword ptr [r22+r19*2+0x2a126966] IID463 - __ cmovq(Assembler::Condition::parity, r12, Address(r10, +0x3d7c59f)); // cmovp r12, qword ptr [r10+0x3d7c59f] IID464 - __ cmovq(Assembler::Condition::noParity, r10, Address(r8, r8, (Address::ScaleFactor)3, -0xe61862d)); // cmovnp r10, qword ptr [r8+r8*8-0xe61862d] IID465 - __ cmovq(Assembler::Condition::less, r23, Address(r29, -0x777ed96d)); // cmovl r23, qword ptr [r29-0x777ed96d] IID466 - __ cmovq(Assembler::Condition::greaterEqual, rcx, Address(rbx, r19, (Address::ScaleFactor)1, +0x53c601cb)); // cmovge rcx, qword ptr [rbx+r19*2+0x53c601cb] IID467 - __ cmovq(Assembler::Condition::lessEqual, r14, Address(r17, rbx, (Address::ScaleFactor)0, -0x768bf073)); // cmovle r14, qword ptr [r17+rbx*1-0x768bf073] IID468 - __ cmovq(Assembler::Condition::greater, r29, Address(r10, r19, (Address::ScaleFactor)1, +0x30c98d3c)); // cmovg r29, qword ptr [r10+r19*2+0x30c98d3c] IID469 - __ call(r10); // call r10 IID470 - __ divq(r16); // div r16 IID471 - __ idivq(r27); // idiv r27 IID472 - __ imulq(r9); // imul r9 IID473 - __ mulq(r13); // mul r13 IID474 - __ negq(r14); // neg r14 IID475 - __ notq(r18); // not r18 IID476 - __ rolq(r28); // rol r28, cl IID477 - __ rorq(r28); // ror r28, cl IID478 - __ sarq(r22); // sar r22, cl IID479 - __ salq(r8); // sal r8, cl IID480 - __ shlq(r12); // shl r12, cl IID481 - __ shrq(rbx); // shr rbx, cl IID482 - __ incrementq(rcx); // inc rcx IID483 - __ decrementq(r23); // dec r23 IID484 - __ pushp(rcx); // pushp rcx IID485 - __ popp(r26); // popp r26 IID486 - __ call(Address(r29, r10, (Address::ScaleFactor)0, +0x5655bc9f)); // call qword ptr [r29+r10*1+0x5655bc9f] IID487 - __ mulq(Address(rdx, r21, (Address::ScaleFactor)3, -0x6798a630)); // mul qword ptr [rdx+r21*8-0x6798a630] IID488 - __ negq(Address(r31, r24, (Address::ScaleFactor)0, -0x20071802)); // neg qword ptr [r31+r24*1-0x20071802] IID489 - __ sarq(Address(r21, rdx, (Address::ScaleFactor)2, -0x343cb9e5)); // sar qword ptr [r21+rdx*4-0x343cb9e5], cl IID490 - __ salq(Address(r20, r24, (Address::ScaleFactor)3, +0xa667574)); // sal qword ptr [r20+r24*8+0xa667574], cl IID491 - __ shrq(Address(r27, +0x76b77974)); // shr qword ptr [r27+0x76b77974], cl IID492 - __ incrementq(Address(r25, -0x534e8d31)); // inc qword ptr [r25-0x534e8d31] IID493 - __ decrementq(Address(r20, -0x180d3ea1)); // dec qword ptr [r20-0x180d3ea1] IID494 - __ imulq(r17, Address(r16, -0x2af2fd58), 4096); // imul r17, qword ptr [r16-0x2af2fd58], 4096 IID495 - __ imulq(r28, r25, 16); // imul r28, r25, 16 IID496 - __ shldq(r27, r13, 16); // shld r27, r13, 16 IID497 - __ shrdq(r8, r10, 16); // shrd r8, r10, 16 IID498 - __ pop2(r14, r8); // {load}pop2 r8, r14 IID499 - __ pop2p(r18, rbx); // {load}pop2p rbx, r18 IID500 - __ push2(r23, r19); // {load}push2 r19, r23 IID501 - __ push2p(r12, rbx); // {load}push2p rbx, r12 IID502 - __ movzbq(r9, Address(r14, r23, (Address::ScaleFactor)3, -0x428d2646)); // movzx r9, byte ptr [r14+r23*8-0x428d2646] IID503 - __ movzwq(r28, Address(r9, rcx, (Address::ScaleFactor)2, -0x72611661)); // movzx r28, word ptr [r9+rcx*4-0x72611661] IID504 - __ movsbq(rbx, Address(r24, r21, (Address::ScaleFactor)2, +0x3a6be990)); // movsx rbx, byte ptr [r24+r21*4+0x3a6be990] IID505 - __ movswq(r16, Address(r22, r10, (Address::ScaleFactor)0, +0x7ef8bdd)); // movsx r16, word ptr [r22+r10*1+0x7ef8bdd] IID506 - __ movzbq(r28, r14); // movzx r28, r14b IID507 - __ movzwq(r13, r28); // movzx r13, r28w IID508 - __ movsbq(r11, rdx); // movsx r11, dl IID509 - __ movswq(r12, r26); // movsx r12, r26w IID510 - __ cmpxchgq(r20, Address(r10, -0xbd2a8da)); // cmpxchg qword ptr [r10-0xbd2a8da], r20 IID511 - __ eidivq(r15, false); // {EVEX}idiv r15 IID512 - __ eidivq(r23, true); // {NF}idiv r23 IID513 - __ edivq(r14, false); // {EVEX}div r14 IID514 - __ edivq(r14, true); // {NF}div r14 IID515 - __ eimulq(r15, false); // {EVEX}imul r15 IID516 - __ eimulq(r20, true); // {NF}imul r20 IID517 - __ emulq(rcx, false); // {EVEX}mul rcx IID518 - __ emulq(r21, true); // {NF}mul r21 IID519 - __ emulq(Address(r16, r10, (Address::ScaleFactor)3, +0x5f66ac1e), false); // {EVEX}mul qword ptr [r16+r10*8+0x5f66ac1e] IID520 - __ emulq(Address(r21, r22, (Address::ScaleFactor)3, -0xbbc807d), true); // {NF}mul qword ptr [r21+r22*8-0xbbc807d] IID521 - __ eimulq(r22, r26, false); // {EVEX}imul r22, r26 IID522 - __ eimulq(r25, r21, true); // {NF}imul r25, r21 IID523 - __ elzcntq(r20, r13, false); // {EVEX}lzcnt r20, r13 IID524 - __ elzcntq(r25, r19, true); // {NF}lzcnt r25, r19 IID525 - __ enegq(r21, r30, false); // {EVEX}neg r21, r30 IID526 - __ enegq(r29, r11, true); // {NF}neg r29, r11 IID527 - __ enotq(r22, r8); // {EVEX}not r22, r8 IID528 - __ epopcntq(r12, r19, false); // {EVEX}popcnt r12, r19 IID529 - __ epopcntq(r29, r23, true); // {NF}popcnt r29, r23 IID530 - __ erolq(r28, r24, false); // {EVEX}rol r28, r24, cl IID531 - __ erolq(rdx, r20, true); // {NF}rol rdx, r20, cl IID532 - __ erorq(rbx, r30, false); // {EVEX}ror rbx, r30, cl IID533 - __ erorq(r10, r15, true); // {NF}ror r10, r15, cl IID534 - __ esalq(r17, r13, false); // {EVEX}sal r17, r13, cl IID535 - __ esalq(r21, r24, true); // {NF}sal r21, r24, cl IID536 - __ esarq(r31, r12, false); // {EVEX}sar r31, r12, cl IID537 - __ esarq(rdx, r24, true); // {NF}sar rdx, r24, cl IID538 - __ edecq(r21, r24, false); // {EVEX}dec r21, r24 IID539 - __ edecq(r15, r31, true); // {NF}dec r15, r31 IID540 - __ eincq(r10, rbx, false); // {EVEX}inc r10, rbx IID541 - __ eincq(r18, r8, true); // {NF}inc r18, r8 IID542 - __ eshlq(r10, r26, false); // {EVEX}shl r10, r26, cl IID543 - __ eshlq(r28, r14, true); // {NF}shl r28, r14, cl IID544 - __ eshrq(r10, r19, false); // {EVEX}shr r10, r19, cl IID545 - __ eshrq(r28, r21, true); // {NF}shr r28, r21, cl IID546 - __ etzcntq(r21, r22, false); // {EVEX}tzcnt r21, r22 IID547 - __ etzcntq(r16, r23, true); // {NF}tzcnt r16, r23 IID548 - __ eimulq(r11, Address(r18, r9, (Address::ScaleFactor)2, -0x132285a1), false); // {EVEX}imul r11, qword ptr [r18+r9*4-0x132285a1] IID549 - __ eimulq(r13, Address(r24, r15, (Address::ScaleFactor)3, +0x48f50ca0), true); // {NF}imul r13, qword ptr [r24+r15*8+0x48f50ca0] IID550 - __ elzcntq(r9, Address(r13, +0x2115cf0e), false); // {EVEX}lzcnt r9, qword ptr [r13+0x2115cf0e] IID551 - __ elzcntq(r27, Address(r30, +0x49cabbb), true); // {NF}lzcnt r27, qword ptr [r30+0x49cabbb] IID552 - __ enegq(r21, Address(r13, r31, (Address::ScaleFactor)2, +0x50a8f4d2), false); // {EVEX}neg r21, qword ptr [r13+r31*4+0x50a8f4d2] IID553 - __ enegq(r22, Address(r18, r20, (Address::ScaleFactor)1, -0x5da0584c), true); // {NF}neg r22, qword ptr [r18+r20*2-0x5da0584c] IID554 - __ epopcntq(r14, Address(rbx, r22, (Address::ScaleFactor)2, -0x606349d1), false); // {EVEX}popcnt r14, qword ptr [rbx+r22*4-0x606349d1] IID555 - __ epopcntq(r26, Address(r23, r22, (Address::ScaleFactor)3, -0x72c66c23), true); // {NF}popcnt r26, qword ptr [r23+r22*8-0x72c66c23] IID556 - __ esalq(r26, Address(r9, +0x334aba09), false); // {EVEX}sal r26, qword ptr [r9+0x334aba09], cl IID557 - __ esalq(r9, Address(r9, r30, (Address::ScaleFactor)3, -0x219a6102), true); // {NF}sal r9, qword ptr [r9+r30*8-0x219a6102], cl IID558 - __ esarq(r25, Address(r20, -0x2131bab1), false); // {EVEX}sar r25, qword ptr [r20-0x2131bab1], cl IID559 - __ esarq(r16, Address(r28, r16, (Address::ScaleFactor)1, +0x48c483b9), true); // {NF}sar r16, qword ptr [r28+r16*2+0x48c483b9], cl IID560 - __ edecq(r30, Address(r9, r16, (Address::ScaleFactor)0, -0x88ce84f), false); // {EVEX}dec r30, qword ptr [r9+r16*1-0x88ce84f] IID561 - __ edecq(r11, Address(r30, r29, (Address::ScaleFactor)2, +0x3eeb8fd0), true); // {NF}dec r11, qword ptr [r30+r29*4+0x3eeb8fd0] IID562 - __ eincq(r26, Address(r29, r10, (Address::ScaleFactor)3, +0x3ef4822e), false); // {EVEX}inc r26, qword ptr [r29+r10*8+0x3ef4822e] IID563 - __ eincq(r29, Address(r19, r20, (Address::ScaleFactor)2, -0x3f0f3db9), true); // {NF}inc r29, qword ptr [r19+r20*4-0x3f0f3db9] IID564 - __ eshrq(r8, Address(r30, r20, (Address::ScaleFactor)0, +0x15b56a17), false); // {EVEX}shr r8, qword ptr [r30+r20*1+0x15b56a17], cl IID565 - __ eshrq(r26, Address(r11, -0x2de86561), true); // {NF}shr r26, qword ptr [r11-0x2de86561], cl IID566 - __ etzcntq(r11, Address(rcx, r30, (Address::ScaleFactor)1, -0x32ffb1c2), false); // {EVEX}tzcnt r11, qword ptr [rcx+r30*2-0x32ffb1c2] IID567 - __ etzcntq(r23, Address(r9, r12, (Address::ScaleFactor)1, -0x54823e69), true); // {NF}tzcnt r23, qword ptr [r9+r12*2-0x54823e69] IID568 - __ eaddq(r20, Address(r13, rcx, (Address::ScaleFactor)3, -0x46116c0d), r15, false); // {EVEX}add r20, qword ptr [r13+rcx*8-0x46116c0d], r15 IID569 - __ eaddq(r13, Address(r9, r23, (Address::ScaleFactor)1, -0x286c7605), r16, true); // {NF}add r13, qword ptr [r9+r23*2-0x286c7605], r16 IID570 - __ eandq(r21, Address(r30, r17, (Address::ScaleFactor)0, +0xf4e30b2), r29, false); // {EVEX}and r21, qword ptr [r30+r17*1+0xf4e30b2], r29 IID571 - __ eandq(r30, Address(r17, r31, (Address::ScaleFactor)0, +0x3ab9dec4), r17, true); // {NF}and r30, qword ptr [r17+r31*1+0x3ab9dec4], r17 IID572 - __ eorq(r10, Address(r27, r30, (Address::ScaleFactor)1, -0x197f1266), r28, false); // {EVEX}or r10, qword ptr [r27+r30*2-0x197f1266], r28 IID573 - __ eorq(r9, Address(r29, r30, (Address::ScaleFactor)0, -0x24ea9b08), r11, true); // {NF}or r9, qword ptr [r29+r30*1-0x24ea9b08], r11 IID574 - __ esubq(r15, Address(r14, -0x4f44bf90), r16, false); // {EVEX}sub r15, qword ptr [r14-0x4f44bf90], r16 IID575 - __ esubq(rcx, Address(r21, r18, (Address::ScaleFactor)1, -0x11d0ac8f), r28, true); // {NF}sub rcx, qword ptr [r21+r18*2-0x11d0ac8f], r28 IID576 - __ exorq(r19, Address(r19, r18, (Address::ScaleFactor)0, -0xa5e55ec), r8, false); // {EVEX}xor r19, qword ptr [r19+r18*1-0xa5e55ec], r8 IID577 - __ exorq(r28, Address(r17, r28, (Address::ScaleFactor)1, -0x6eb42fe0), r16, true); // {NF}xor r28, qword ptr [r17+r28*2-0x6eb42fe0], r16 IID578 - __ eaddq(r17, Address(r18, -0x60ab1105), 16777216, false); // {EVEX}add r17, qword ptr [r18-0x60ab1105], 16777216 IID579 - __ eaddq(r25, Address(r19, r25, (Address::ScaleFactor)0, +0x122444d9), 65536, true); // {NF}add r25, qword ptr [r19+r25*1+0x122444d9], 65536 IID580 - __ eandq(r30, Address(r9, r28, (Address::ScaleFactor)1, -0x25b00cf3), 4096, false); // {EVEX}and r30, qword ptr [r9+r28*2-0x25b00cf3], 4096 IID581 - __ eandq(r9, Address(r22, rbx, (Address::ScaleFactor)1, -0x7e465026), 268435456, true); // {NF}and r9, qword ptr [r22+rbx*2-0x7e465026], 268435456 IID582 - __ eimulq(r12, Address(r25, r25, (Address::ScaleFactor)1, -0x432d68cc), 1, false); // {EVEX}imul r12, qword ptr [r25+r25*2-0x432d68cc], 1 IID583 - __ eimulq(r15, Address(r17, r31, (Address::ScaleFactor)3, -0x2b97565e), 16, true); // {NF}imul r15, qword ptr [r17+r31*8-0x2b97565e], 16 IID584 - __ eorq(r28, Address(rdx, r31, (Address::ScaleFactor)0, +0x3f1363b1), 256, false); // {EVEX}or r28, qword ptr [rdx+r31*1+0x3f1363b1], 256 IID585 - __ eorq(r16, Address(r12, r23, (Address::ScaleFactor)3, -0x1785863c), 16777216, true); // {NF}or r16, qword ptr [r12+r23*8-0x1785863c], 16777216 IID586 - __ esalq(r8, Address(r14, r24, (Address::ScaleFactor)2, -0x714290a5), 2, false); // {EVEX}sal r8, qword ptr [r14+r24*4-0x714290a5], 2 IID587 - __ esalq(r8, Address(r15, r14, (Address::ScaleFactor)2, +0x21f13243), 16, true); // {NF}sal r8, qword ptr [r15+r14*4+0x21f13243], 16 IID588 - __ esarq(r10, Address(r13, r29, (Address::ScaleFactor)0, +0x7d04cb72), 2, false); // {EVEX}sar r10, qword ptr [r13+r29*1+0x7d04cb72], 2 IID589 - __ esarq(r11, Address(r21, r31, (Address::ScaleFactor)3, -0x2176b4dc), 8, true); // {NF}sar r11, qword ptr [r21+r31*8-0x2176b4dc], 8 IID590 - __ eshrq(rcx, Address(r16, r12, (Address::ScaleFactor)1, +0x260c9a38), 4, false); // {EVEX}shr rcx, qword ptr [r16+r12*2+0x260c9a38], 4 IID591 - __ eshrq(r22, Address(r26, r9, (Address::ScaleFactor)0, -0x5e56bb62), 8, true); // {NF}shr r22, qword ptr [r26+r9*1-0x5e56bb62], 8 IID592 - __ esubq(r31, Address(rbx, r28, (Address::ScaleFactor)1, +0x2b00bb10), 1, false); // {EVEX}sub r31, qword ptr [rbx+r28*2+0x2b00bb10], 1 IID593 - __ esubq(r21, Address(r31, -0x6c10f4ad), 4096, true); // {NF}sub r21, qword ptr [r31-0x6c10f4ad], 4096 IID594 - __ exorq(r11, Address(r23, r30, (Address::ScaleFactor)1, +0x51a6026b), 65536, false); // {EVEX}xor r11, qword ptr [r23+r30*2+0x51a6026b], 65536 IID595 - __ exorq(r14, Address(r27, r10, (Address::ScaleFactor)2, -0x34ad9bab), 16, true); // {NF}xor r14, qword ptr [r27+r10*4-0x34ad9bab], 16 IID596 - __ eaddq(r20, r23, 16777216, false); // {EVEX}add r20, r23, 16777216 IID597 - __ eaddq(rax, r30, 16777216, false); // {EVEX}add rax, r30, 16777216 IID598 - __ eaddq(r9, r21, 4096, true); // {NF}add r9, r21, 4096 IID599 - __ eaddq(rax, rbx, 4096, true); // {NF}add rax, rbx, 4096 IID600 - __ eandq(rdx, r21, 268435456, false); // {EVEX}and rdx, r21, 268435456 IID601 - __ eandq(rax, r8, 268435456, false); // {EVEX}and rax, r8, 268435456 IID602 - __ eandq(r19, r31, 65536, true); // {NF}and r19, r31, 65536 IID603 - __ eandq(rax, rbx, 65536, true); // {NF}and rax, rbx, 65536 IID604 - __ eimulq(r21, r9, 16777216, false); // {EVEX}imul r21, r9, 16777216 IID605 - __ eimulq(rax, r30, 16777216, false); // {EVEX}imul rax, r30, 16777216 IID606 - __ eimulq(r30, r18, 65536, true); // {NF}imul r30, r18, 65536 IID607 - __ eimulq(rax, r19, 65536, true); // {NF}imul rax, r19, 65536 IID608 - __ eorq(r20, r16, 1048576, false); // {EVEX}or r20, r16, 1048576 IID609 - __ eorq(rax, r28, 1048576, false); // {EVEX}or rax, r28, 1048576 IID610 - __ eorq(rbx, r24, 4096, true); // {NF}or rbx, r24, 4096 IID611 - __ eorq(rax, r22, 4096, true); // {NF}or rax, r22, 4096 IID612 - __ erclq(r20, r30, 4); // {EVEX}rcl r20, r30, 4 IID613 - __ erclq(rax, r22, 4); // {EVEX}rcl rax, r22, 4 IID614 - __ erolq(rcx, r28, 2, false); // {EVEX}rol rcx, r28, 2 IID615 - __ erolq(rax, r21, 2, false); // {EVEX}rol rax, r21, 2 IID616 - __ erolq(r26, r15, 4, true); // {NF}rol r26, r15, 4 IID617 - __ erolq(rax, r19, 4, true); // {NF}rol rax, r19, 4 IID618 - __ erorq(r24, r19, 8, false); // {EVEX}ror r24, r19, 8 IID619 - __ erorq(rax, r28, 8, false); // {EVEX}ror rax, r28, 8 IID620 - __ erorq(r25, r18, 4, true); // {NF}ror r25, r18, 4 IID621 - __ erorq(rax, r13, 4, true); // {NF}ror rax, r13, 4 IID622 - __ esalq(r27, r17, 2, false); // {EVEX}sal r27, r17, 2 IID623 - __ esalq(rax, rdx, 2, false); // {EVEX}sal rax, rdx, 2 IID624 - __ esalq(rbx, r28, 16, true); // {NF}sal rbx, r28, 16 IID625 - __ esalq(rax, r15, 16, true); // {NF}sal rax, r15, 16 IID626 - __ esarq(rbx, r12, 4, false); // {EVEX}sar rbx, r12, 4 IID627 - __ esarq(rax, rbx, 4, false); // {EVEX}sar rax, rbx, 4 IID628 - __ esarq(r17, rdx, 2, true); // {NF}sar r17, rdx, 2 IID629 - __ esarq(rax, r31, 2, true); // {NF}sar rax, r31, 2 IID630 - __ eshlq(r21, rbx, 4, false); // {EVEX}shl r21, rbx, 4 IID631 - __ eshlq(rax, r24, 4, false); // {EVEX}shl rax, r24, 4 IID632 - __ eshlq(r27, r13, 16, true); // {NF}shl r27, r13, 16 IID633 - __ eshlq(rax, r25, 16, true); // {NF}shl rax, r25, 16 IID634 - __ eshrq(rcx, r22, 16, false); // {EVEX}shr rcx, r22, 16 IID635 - __ eshrq(rax, r14, 16, false); // {EVEX}shr rax, r14, 16 IID636 - __ eshrq(r11, r30, 4, true); // {NF}shr r11, r30, 4 IID637 - __ eshrq(rax, r24, 4, true); // {NF}shr rax, r24, 4 IID638 - __ esubq(r20, r19, 256, false); // {EVEX}sub r20, r19, 256 IID639 - __ esubq(rax, r17, 256, false); // {EVEX}sub rax, r17, 256 IID640 - __ esubq(r31, r30, 65536, true); // {NF}sub r31, r30, 65536 IID641 - __ esubq(rax, r18, 65536, true); // {NF}sub rax, r18, 65536 IID642 - __ exorq(r18, r11, 4096, false); // {EVEX}xor r18, r11, 4096 IID643 - __ exorq(rax, r10, 4096, false); // {EVEX}xor rax, r10, 4096 IID644 - __ exorq(r24, r18, 268435456, true); // {NF}xor r24, r18, 268435456 IID645 - __ exorq(rax, rbx, 268435456, true); // {NF}xor rax, rbx, 268435456 IID646 - __ eorq_imm32(r26, r21, 4194304, false); // {EVEX}or r26, r21, 4194304 IID647 - __ eorq_imm32(rax, r8, 4194304, false); // {EVEX}or rax, r8, 4194304 IID648 - __ eorq_imm32(r22, r21, 262144, false); // {EVEX}or r22, r21, 262144 IID649 - __ eorq_imm32(rax, r27, 262144, false); // {EVEX}or rax, r27, 262144 IID650 - __ esubq_imm32(r16, r8, 4194304, false); // {EVEX}sub r16, r8, 4194304 IID651 - __ esubq_imm32(rax, rdx, 4194304, false); // {EVEX}sub rax, rdx, 4194304 IID652 - __ esubq_imm32(r20, r31, 1048576, true); // {NF}sub r20, r31, 1048576 IID653 - __ esubq_imm32(rax, r21, 1048576, true); // {NF}sub rax, r21, 1048576 IID654 - __ eaddq(r20, r14, Address(rcx, r16, (Address::ScaleFactor)0, +0x7c6654d9), false); // {EVEX}add r20, r14, qword ptr [rcx+r16*1+0x7c6654d9] IID655 - __ eaddq(r29, rcx, Address(r15, r23, (Address::ScaleFactor)0, +0x45b7f72d), true); // {NF}add r29, rcx, qword ptr [r15+r23*1+0x45b7f72d] IID656 - __ eandq(r19, r17, Address(r13, r22, (Address::ScaleFactor)1, -0x750c1996), false); // {EVEX}and r19, r17, qword ptr [r13+r22*2-0x750c1996] IID657 - __ eandq(r13, r8, Address(r31, r23, (Address::ScaleFactor)1, -0x2211b6b2), true); // {NF}and r13, r8, qword ptr [r31+r23*2-0x2211b6b2] IID658 - __ eorq(r11, r28, Address(r13, r11, (Address::ScaleFactor)3, +0x5c0013ab), false); // {EVEX}or r11, r28, qword ptr [r13+r11*8+0x5c0013ab] IID659 - __ eorq(rdx, r18, Address(r18, rcx, (Address::ScaleFactor)0, +0x59557e71), true); // {NF}or rdx, r18, qword ptr [r18+rcx*1+0x59557e71] IID660 - __ eimulq(r27, r11, Address(r22, -0x28469649), false); // {EVEX}imul r27, r11, qword ptr [r22-0x28469649] IID661 - __ eimulq(r10, r9, Address(r24, +0x49691d54), true); // {NF}imul r10, r9, qword ptr [r24+0x49691d54] IID662 - __ esubq(r24, r12, Address(r19, +0x22d529aa), false); // {EVEX}sub r24, r12, qword ptr [r19+0x22d529aa] IID663 - __ esubq(r20, r18, Address(r9, r10, (Address::ScaleFactor)2, -0x264a7a48), true); // {NF}sub r20, r18, qword ptr [r9+r10*4-0x264a7a48] IID664 - __ exorq(rbx, r9, Address(r14, r27, (Address::ScaleFactor)0, +0xf71c02f), false); // {EVEX}xor rbx, r9, qword ptr [r14+r27*1+0xf71c02f] IID665 - __ exorq(r25, r15, Address(r10, r12, (Address::ScaleFactor)1, +0x732367bd), true); // {NF}xor r25, r15, qword ptr [r10+r12*2+0x732367bd] IID666 - __ eaddq(r11, r9, r10, false); // {load}{EVEX}add r11, r9, r10 IID667 - __ eaddq(r25, r13, r16, true); // {load}{NF}add r25, r13, r16 IID668 - __ eadcxq(r11, r21, r25); // {load}{EVEX}adcx r11, r21, r25 IID669 - __ eadoxq(rdx, r20, rbx); // {load}{EVEX}adox rdx, r20, rbx IID670 - __ eandq(r25, r21, r26, false); // {load}{EVEX}and r25, r21, r26 IID671 - __ eandq(r23, r27, r21, true); // {load}{NF}and r23, r27, r21 IID672 - __ eimulq(r10, r10, r12, false); // {load}{EVEX}imul r10, r10, r12 IID673 - __ eimulq(r31, r12, r23, true); // {load}{NF}imul r31, r12, r23 IID674 - __ eorq(r16, r29, r14, false); // {load}{EVEX}or r16, r29, r14 IID675 - __ eorq(r19, r24, r23, true); // {load}{NF}or r19, r24, r23 IID676 - __ esubq(r14, r21, r15, false); // {load}{EVEX}sub r14, r21, r15 IID677 - __ esubq(r25, r9, r29, true); // {load}{NF}sub r25, r9, r29 IID678 - __ exorq(rdx, r11, r25, false); // {load}{EVEX}xor rdx, r11, r25 IID679 - __ exorq(r19, r10, r16, true); // {load}{NF}xor r19, r10, r16 IID680 - __ eshldq(r8, r23, r31, 8, false); // {EVEX}shld r8, r23, r31, 8 IID681 - __ eshldq(r31, rbx, r16, 2, true); // {NF}shld r31, rbx, r16, 2 IID682 - __ eshrdq(r24, r10, r9, 2, false); // {EVEX}shrd r24, r10, r9, 2 IID683 - __ eshrdq(r28, r26, r18, 16, true); // {NF}shrd r28, r26, r18, 16 IID684 - __ ecmovq (Assembler::Condition::overflow, r25, r20, r16); // cmovo r25, r20, r16 IID685 - __ ecmovq (Assembler::Condition::noOverflow, r21, rbx, r28); // cmovno r21, rbx, r28 IID686 - __ ecmovq (Assembler::Condition::below, r22, r19, r13); // cmovb r22, r19, r13 IID687 - __ ecmovq (Assembler::Condition::aboveEqual, r15, rdx, r8); // cmovae r15, rdx, r8 IID688 - __ ecmovq (Assembler::Condition::zero, r22, r14, r12); // cmovz r22, r14, r12 IID689 - __ ecmovq (Assembler::Condition::notZero, r24, r14, r24); // cmovnz r24, r14, r24 IID690 - __ ecmovq (Assembler::Condition::belowEqual, r13, r21, rbx); // cmovbe r13, r21, rbx IID691 - __ ecmovq (Assembler::Condition::above, rbx, r27, r14); // cmova rbx, r27, r14 IID692 - __ ecmovq (Assembler::Condition::negative, r24, r27, r17); // cmovs r24, r27, r17 IID693 - __ ecmovq (Assembler::Condition::positive, r21, r27, r27); // cmovns r21, r27, r27 IID694 - __ ecmovq (Assembler::Condition::parity, r27, r14, r24); // cmovp r27, r14, r24 IID695 - __ ecmovq (Assembler::Condition::noParity, r28, r29, r22); // cmovnp r28, r29, r22 IID696 - __ ecmovq (Assembler::Condition::less, r15, r13, r31); // cmovl r15, r13, r31 IID697 - __ ecmovq (Assembler::Condition::greaterEqual, r21, r15, r30); // cmovge r21, r15, r30 IID698 - __ ecmovq (Assembler::Condition::lessEqual, r20, r8, r13); // cmovle r20, r8, r13 IID699 - __ ecmovq (Assembler::Condition::greater, r31, r25, r27); // cmovg r31, r25, r27 IID700 - __ ecmovq (Assembler::Condition::overflow, r31, r15, Address(r14, r13, (Address::ScaleFactor)1, -0x6e68556)); // cmovo r31, r15, qword ptr [r14+r13*2-0x6e68556] IID701 - __ ecmovq (Assembler::Condition::noOverflow, r12, r28, Address(r30, r15, (Address::ScaleFactor)3, +0x3ba33f9e)); // cmovno r12, r28, qword ptr [r30+r15*8+0x3ba33f9e] IID702 - __ ecmovq (Assembler::Condition::below, r16, r25, Address(r12, r9, (Address::ScaleFactor)0, -0x28e03b33)); // cmovb r16, r25, qword ptr [r12+r9*1-0x28e03b33] IID703 - __ ecmovq (Assembler::Condition::aboveEqual, r8, r27, Address(r8, r25, (Address::ScaleFactor)3, -0x1e42bd95)); // cmovae r8, r27, qword ptr [r8+r25*8-0x1e42bd95] IID704 - __ ecmovq (Assembler::Condition::zero, rcx, r20, Address(r27, rbx, (Address::ScaleFactor)2, +0x46823c58)); // cmovz rcx, r20, qword ptr [r27+rbx*4+0x46823c58] IID705 - __ ecmovq (Assembler::Condition::notZero, rbx, r12, Address(r21, -0x635b8c8)); // cmovnz rbx, r12, qword ptr [r21-0x635b8c8] IID706 - __ ecmovq (Assembler::Condition::belowEqual, r23, rbx, Address(r27, r26, (Address::ScaleFactor)3, +0x922bcc0)); // cmovbe r23, rbx, qword ptr [r27+r26*8+0x922bcc0] IID707 - __ ecmovq (Assembler::Condition::above, r25, r9, Address(r23, +0xd2a14ec)); // cmova r25, r9, qword ptr [r23+0xd2a14ec] IID708 - __ ecmovq (Assembler::Condition::negative, r11, r19, Address(r11, -0xfb95a9d)); // cmovs r11, r19, qword ptr [r11-0xfb95a9d] IID709 - __ ecmovq (Assembler::Condition::positive, r13, r18, Address(r28, r19, (Address::ScaleFactor)0, +0x716b9b7e)); // cmovns r13, r18, qword ptr [r28+r19*1+0x716b9b7e] IID710 - __ ecmovq (Assembler::Condition::parity, r21, r16, Address(rcx, r29, (Address::ScaleFactor)0, -0x5af0441e)); // cmovp r21, r16, qword ptr [rcx+r29*1-0x5af0441e] IID711 - __ ecmovq (Assembler::Condition::noParity, r12, r31, Address(r20, r26, (Address::ScaleFactor)0, +0xe0b7fb1)); // cmovnp r12, r31, qword ptr [r20+r26*1+0xe0b7fb1] IID712 - __ ecmovq (Assembler::Condition::less, r15, r24, Address(r30, +0x2d3b7b4f)); // cmovl r15, r24, qword ptr [r30+0x2d3b7b4f] IID713 - __ ecmovq (Assembler::Condition::greaterEqual, r12, r15, Address(r14, r21, (Address::ScaleFactor)2, -0x1222aee8)); // cmovge r12, r15, qword ptr [r14+r21*4-0x1222aee8] IID714 - __ ecmovq (Assembler::Condition::lessEqual, rbx, r31, Address(r23, r20, (Address::ScaleFactor)0, -0x96e4d6a)); // cmovle rbx, r31, qword ptr [r23+r20*1-0x96e4d6a] IID715 - __ ecmovq (Assembler::Condition::greater, rdx, rdx, Address(r10, rdx, (Address::ScaleFactor)3, +0x3875f17c)); // cmovg rdx, rdx, qword ptr [r10+rdx*8+0x3875f17c] IID716 + __ adcq(rbx, r31); // {load}adc rbx, r31 IID480 + __ cmpq(r30, r31); // {load}cmp r30, r31 IID481 + __ imulq(r29, r28); // {load}imul r29, r28 IID482 + __ popcntq(r25, r10); // {load}popcnt r25, r10 IID483 + __ sbbq(r24, r20); // {load}sbb r24, r20 IID484 + __ subq(r16, rdx); // {load}sub r16, rdx IID485 + __ tzcntq(r26, r28); // {load}tzcnt r26, r28 IID486 + __ lzcntq(r28, r9); // {load}lzcnt r28, r9 IID487 + __ addq(r20, r24); // {load}add r20, r24 IID488 + __ andq(r24, r29); // {load}and r24, r29 IID489 + __ orq(r23, r27); // {load}or r23, r27 IID490 + __ xorq(r15, r12); // {load}xor r15, r12 IID491 + __ movq(r18, r19); // {load}mov r18, r19 IID492 + __ bsfq(r31, rcx); // {load}bsf r31, rcx IID493 + __ bsrq(r9, r13); // {load}bsr r9, r13 IID494 + __ btq(r20, rcx); // {load}bt r20, rcx IID495 + __ xchgq(r8, r21); // {load}xchg r8, r21 IID496 + __ testq(r24, r14); // {load}test r24, r14 IID497 + __ addq(Address(rcx, r23, (Address::ScaleFactor)2, +0x4ff06c4d), r29); // add qword ptr [rcx+r23*4+0x4ff06c4d], r29 IID498 + __ andq(Address(r24, r10, (Address::ScaleFactor)1, -0x75d9a189), r26); // and qword ptr [r24+r10*2-0x75d9a189], r26 IID499 + __ cmpq(Address(rbx, rbx, (Address::ScaleFactor)0, +0x4033d59c), r17); // cmp qword ptr [rbx+rbx*1+0x4033d59c], r17 IID500 + __ orq(Address(r22, r12, (Address::ScaleFactor)3, -0x3893347d), r18); // or qword ptr [r22+r12*8-0x3893347d], r18 IID501 + __ xorq(Address(r20, r23, (Address::ScaleFactor)3, +0x4b311560), r12); // xor qword ptr [r20+r23*8+0x4b311560], r12 IID502 + __ subq(Address(r10, r28, (Address::ScaleFactor)2, +0x5c3a2657), r29); // sub qword ptr [r10+r28*4+0x5c3a2657], r29 IID503 + __ movq(Address(r13, r25, (Address::ScaleFactor)3, +0x1a3d6f3f), r22); // mov qword ptr [r13+r25*8+0x1a3d6f3f], r22 IID504 + __ xaddq(Address(r17, r24, (Address::ScaleFactor)3, -0x35addbd8), r25); // xadd qword ptr [r17+r24*8-0x35addbd8], r25 IID505 + __ andq(Address(r25, +0x632184c3), 16777216); // and qword ptr [r25+0x632184c3], 16777216 IID506 + __ addq(Address(r13, r13, (Address::ScaleFactor)0, -0x3972eac6), 16777216); // add qword ptr [r13+r13*1-0x3972eac6], 16777216 IID507 + __ cmpq(Address(r9, -0x13b4c806), 4096); // cmp qword ptr [r9-0x13b4c806], 4096 IID508 + __ sarq(Address(r31, +0x4fa7f551), 1); // sar qword ptr [r31+0x4fa7f551], 1 IID509 + __ salq(Address(r21, r31, (Address::ScaleFactor)2, +0x31aa8232), 1); // sal qword ptr [r21+r31*4+0x31aa8232], 1 IID510 + __ sbbq(Address(r24, r31, (Address::ScaleFactor)2, -0x466538b7), 268435456); // sbb qword ptr [r24+r31*4-0x466538b7], 268435456 IID511 + __ shrq(Address(r28, r22, (Address::ScaleFactor)0, -0x3efe85b1), 2); // shr qword ptr [r28+r22*1-0x3efe85b1], 2 IID512 + __ subq(Address(r16, -0x1389a3eb), 1048576); // sub qword ptr [r16-0x1389a3eb], 1048576 IID513 + __ xorq(Address(r29, r8, (Address::ScaleFactor)0, +0x1d022615), 16); // xor qword ptr [r29+r8*1+0x1d022615], 16 IID514 + __ orq(Address(r12, r28, (Address::ScaleFactor)1, -0x34c898e2), 1); // or qword ptr [r12+r28*2-0x34c898e2], 1 IID515 + __ movq(Address(rcx, r24, (Address::ScaleFactor)2, -0x1644eb08), 256); // mov qword ptr [rcx+r24*4-0x1644eb08], 256 IID516 + __ testq(Address(r29, -0x7d23890b), -65536); // test qword ptr [r29-0x7d23890b], -65536 IID517 + __ addq(r23, Address(rcx, r19, (Address::ScaleFactor)2, +0x70eac654)); // add r23, qword ptr [rcx+r19*4+0x70eac654] IID518 + __ andq(rdx, Address(r24, r15, (Address::ScaleFactor)0, -0x204ddaa9)); // and rdx, qword ptr [r24+r15*1-0x204ddaa9] IID519 + __ cmpq(rdx, Address(r23, r11, (Address::ScaleFactor)3, +0x32c930bd)); // cmp rdx, qword ptr [r23+r11*8+0x32c930bd] IID520 + __ lzcntq(r28, Address(rdx, -0x5433c28f)); // lzcnt r28, qword ptr [rdx-0x5433c28f] IID521 + __ orq(r22, Address(r19, r14, (Address::ScaleFactor)1, -0x2cc67d38)); // or r22, qword ptr [r19+r14*2-0x2cc67d38] IID522 + __ adcq(r10, Address(r10, +0x3d7c59f)); // adc r10, qword ptr [r10+0x3d7c59f] IID523 + __ imulq(r10, Address(r8, r8, (Address::ScaleFactor)3, -0xe61862d)); // imul r10, qword ptr [r8+r8*8-0xe61862d] IID524 + __ popcntq(r23, Address(r29, -0x777ed96d)); // popcnt r23, qword ptr [r29-0x777ed96d] IID525 + __ sbbq(rcx, Address(rbx, r19, (Address::ScaleFactor)1, +0x53c601cb)); // sbb rcx, qword ptr [rbx+r19*2+0x53c601cb] IID526 + __ subq(r14, Address(r17, rbx, (Address::ScaleFactor)0, -0x768bf073)); // sub r14, qword ptr [r17+rbx*1-0x768bf073] IID527 + __ tzcntq(r29, Address(r10, r19, (Address::ScaleFactor)1, +0x30c98d3c)); // tzcnt r29, qword ptr [r10+r19*2+0x30c98d3c] IID528 + __ xorq(r10, Address(r16, r27, (Address::ScaleFactor)0, -0x3d08d602)); // xor r10, qword ptr [r16+r27*1-0x3d08d602] IID529 + __ movq(r18, Address(r28, r28, (Address::ScaleFactor)3, -0x62fbac91)); // mov r18, qword ptr [r28+r28*8-0x62fbac91] IID530 + __ leaq(rbx, Address(rcx, +0x450602a5)); // lea rbx, qword ptr [rcx+0x450602a5] IID531 + __ cvttsd2siq(r12, Address(r30, r31, (Address::ScaleFactor)0, -0x6798a630)); // cvttsd2si r12, qword ptr [r30+r31*1-0x6798a630] IID532 + __ xchgq(r31, Address(r24, r10, (Address::ScaleFactor)1, -0x706712ed)); // xchg r31, qword ptr [r24+r10*2-0x706712ed] IID533 + __ testq(r14, Address(r13, r20, (Address::ScaleFactor)3, +0x171081f2)); // test r14, qword ptr [r13+r20*8+0x171081f2] IID534 + __ addq(r31, 16); // add r31, 16 IID535 + __ andq(r25, 16); // and r25, 16 IID536 + __ adcq(r23, 256); // adc r23, 256 IID537 + __ cmpq(r19, 268435456); // cmp r19, 268435456 IID538 + __ rclq(r31, 1); // rcl r31, 1 IID539 + __ rcrq(r17, 1); // rcr r17, 1 IID540 + __ rolq(r25, 2); // rol r25, 2 IID541 + __ rorq(r17, 4); // ror r17, 4 IID542 + __ sarq(r28, 1); // sar r28, 1 IID543 + __ salq(r15, 4); // sal r15, 4 IID544 + __ sbbq(rbx, 65536); // sbb rbx, 65536 IID545 + __ shlq(r21, 1); // shl r21, 1 IID546 + __ shrq(r10, 1); // shr r10, 1 IID547 + __ subq(r14, 16); // sub r14, 16 IID548 + __ xorq(r18, 268435456); // xor r18, 268435456 IID549 + __ movq(r23, 16); // mov r23, 16 IID550 + __ mov64(r12, 1099511627776); // mov r12, 1099511627776 IID551 + __ btq(r14, 4); // bt r14, 4 IID552 + __ testq(r24, -4096); // test r24, -4096 IID553 + __ orq_imm32(r19, 1048576); // or r19, 1048576 IID554 + __ subq_imm32(rcx, 268435456); // sub rcx, 268435456 IID555 + __ cmovq(Assembler::Condition::overflow, rdx, Address(r19, rbx, (Address::ScaleFactor)3, +0x211c8c4)); // cmovo rdx, qword ptr [r19+rbx*8+0x211c8c4] IID556 + __ cmovq(Assembler::Condition::noOverflow, rbx, Address(r21, +0x49267743)); // cmovno rbx, qword ptr [r21+0x49267743] IID557 + __ cmovq(Assembler::Condition::below, r21, Address(r8, r28, (Address::ScaleFactor)1, -0x4c8c2946)); // cmovb r21, qword ptr [r8+r28*2-0x4c8c2946] IID558 + __ cmovq(Assembler::Condition::aboveEqual, r12, Address(r26, r20, (Address::ScaleFactor)0, -0x264df89c)); // cmovae r12, qword ptr [r26+r20*1-0x264df89c] IID559 + __ cmovq(Assembler::Condition::zero, r17, Address(r28, r9, (Address::ScaleFactor)2, +0x3497196b)); // cmovz r17, qword ptr [r28+r9*4+0x3497196b] IID560 + __ cmovq(Assembler::Condition::notZero, r13, Address(r15, r23, (Address::ScaleFactor)1, -0x27a30999)); // cmovnz r13, qword ptr [r15+r23*2-0x27a30999] IID561 + __ cmovq(Assembler::Condition::belowEqual, r22, Address(r22, +0xf39ab05)); // cmovbe r22, qword ptr [r22+0xf39ab05] IID562 + __ cmovq(Assembler::Condition::above, rcx, Address(r22, r26, (Address::ScaleFactor)3, -0x48c954c)); // cmova rcx, qword ptr [r22+r26*8-0x48c954c] IID563 + __ cmovq(Assembler::Condition::negative, r25, Address(r19, r21, (Address::ScaleFactor)0, +0xe405b0b)); // cmovs r25, qword ptr [r19+r21*1+0xe405b0b] IID564 + __ cmovq(Assembler::Condition::positive, r12, Address(r19, r29, (Address::ScaleFactor)3, -0x7762044b)); // cmovns r12, qword ptr [r19+r29*8-0x7762044b] IID565 + __ cmovq(Assembler::Condition::parity, rbx, Address(r30, r10, (Address::ScaleFactor)1, -0x19798323)); // cmovp rbx, qword ptr [r30+r10*2-0x19798323] IID566 + __ cmovq(Assembler::Condition::noParity, r21, Address(r24, r31, (Address::ScaleFactor)0, -0x5731652b)); // cmovnp r21, qword ptr [r24+r31*1-0x5731652b] IID567 + __ cmovq(Assembler::Condition::less, r18, Address(r8, r10, (Address::ScaleFactor)1, -0x5613be89)); // cmovl r18, qword ptr [r8+r10*2-0x5613be89] IID568 + __ cmovq(Assembler::Condition::greaterEqual, r28, Address(r21, r21, (Address::ScaleFactor)3, +0x65a0fdc4)); // cmovge r28, qword ptr [r21+r21*8+0x65a0fdc4] IID569 + __ cmovq(Assembler::Condition::lessEqual, r23, Address(r11, r18, (Address::ScaleFactor)0, -0x1d1af10c)); // cmovle r23, qword ptr [r11+r18*1-0x1d1af10c] IID570 + __ cmovq(Assembler::Condition::greater, r22, Address(r18, r12, (Address::ScaleFactor)1, +0x1a5f1c38)); // cmovg r22, qword ptr [r18+r12*2+0x1a5f1c38] IID571 + __ call(r23); // call r23 IID572 + __ divq(r30); // div r30 IID573 + __ idivq(r19); // idiv r19 IID574 + __ imulq(r9); // imul r9 IID575 + __ mulq(r13); // mul r13 IID576 + __ negq(r16); // neg r16 IID577 + __ notq(r29); // not r29 IID578 + __ rolq(rcx); // rol rcx, cl IID579 + __ rorq(r25); // ror r25, cl IID580 + __ sarq(r8); // sar r8, cl IID581 + __ salq(r27); // sal r27, cl IID582 + __ shlq(r30); // shl r30, cl IID583 + __ shrq(r23); // shr r23, cl IID584 + __ incrementq(rbx); // inc rbx IID585 + __ decrementq(r14); // dec r14 IID586 + __ pushp(r21); // pushp r21 IID587 + __ popp(r21); // popp r21 IID588 + __ call(Address(r20, r21, (Address::ScaleFactor)1, +0x56c6af2f)); // call qword ptr [r20+r21*2+0x56c6af2f] IID589 + __ mulq(Address(r31, r19, (Address::ScaleFactor)3, -0x1b4eb23)); // mul qword ptr [r31+r19*8-0x1b4eb23] IID590 + __ negq(Address(r27, r27, (Address::ScaleFactor)0, -0x58dbfc1f)); // neg qword ptr [r27+r27*1-0x58dbfc1f] IID591 + __ sarq(Address(rbx, r22, (Address::ScaleFactor)2, -0x606349d1)); // sar qword ptr [rbx+r22*4-0x606349d1], cl IID592 + __ salq(Address(r26, r23, (Address::ScaleFactor)3, +0xb95a079)); // sal qword ptr [r26+r23*8+0xb95a079], cl IID593 + __ shrq(Address(r14, r26, (Address::ScaleFactor)0, +0x3544e09)); // shr qword ptr [r14+r26*1+0x3544e09], cl IID594 + __ incrementq(Address(r27, rdx, (Address::ScaleFactor)0, +0x120b3250)); // inc qword ptr [r27+rdx*1+0x120b3250] IID595 + __ decrementq(Address(r9, r25, (Address::ScaleFactor)2, -0x34aaeccb)); // dec qword ptr [r9+r25*4-0x34aaeccb] IID596 + __ imulq(r20, Address(r16, r28, (Address::ScaleFactor)1, -0x59de05a5), 1048576); // imul r20, qword ptr [r16+r28*2-0x59de05a5], 1048576 IID597 + __ imulq(r17, r23, 256); // imul r17, r23, 256 IID598 + __ shldq(r19, r11, 8); // shld r19, r11, 8 IID599 + __ shrdq(r28, r10, 8); // shrd r28, r10, 8 IID600 + __ pop2(r29, r26); // {load}pop2 r26, r29 IID601 + __ pop2p(r22, r10); // {load}pop2p r10, r22 IID602 + __ push2(r25, r30); // {load}push2 r30, r25 IID603 + __ push2p(r28, r15); // {load}push2p r15, r28 IID604 + __ movzbq(r11, Address(r29, r19, (Address::ScaleFactor)2, -0x12368d34)); // movzx r11, byte ptr [r29+r19*4-0x12368d34] IID605 + __ movzwq(r14, Address(r8, r30, (Address::ScaleFactor)2, -0x4a9392de)); // movzx r14, word ptr [r8+r30*4-0x4a9392de] IID606 + __ movsbq(r28, Address(r23, r15, (Address::ScaleFactor)0, +0x6189cb54)); // movsx r28, byte ptr [r23+r15*1+0x6189cb54] IID607 + __ movswq(r28, Address(rbx, r23, (Address::ScaleFactor)3, -0x2de86561)); // movsx r28, word ptr [rbx+r23*8-0x2de86561] IID608 + __ movzbq(r11, rcx); // movzx r11, cl IID609 + __ movzwq(r30, r15); // movzx r30, r15w IID610 + __ movsbq(r14, rcx); // movsx r14, cl IID611 + __ movswq(r23, r9); // movsx r23, r9w IID612 + __ cmpxchgq(r12, Address(r13, r10, (Address::ScaleFactor)1, -0x7c62c3a)); // cmpxchg qword ptr [r13+r10*2-0x7c62c3a], r12 IID613 + __ eidivq(rcx, false); // {EVEX}idiv rcx IID614 + __ eidivq(r15, true); // {NF}idiv r15 IID615 + __ edivq(r23, false); // {EVEX}div r23 IID616 + __ edivq(r24, true); // {NF}div r24 IID617 + __ eimulq(r27, false); // {EVEX}imul r27 IID618 + __ eimulq(r30, true); // {NF}imul r30 IID619 + __ emulq(r12, false); // {EVEX}mul r12 IID620 + __ emulq(rcx, true); // {NF}mul rcx IID621 + __ emulq(Address(r13, r9, (Address::ScaleFactor)3, -0x226aab94), false); // {EVEX}mul qword ptr [r13+r9*8-0x226aab94] IID622 + __ emulq(Address(r13, r24, (Address::ScaleFactor)3, -0x286c7605), true); // {NF}mul qword ptr [r13+r24*8-0x286c7605] IID623 + __ eimulq(r21, r30, false); // {EVEX}imul r21, r30 IID624 + __ eimulq(r17, r17, false); // imul r17 IID625 + __ eimulq(r29, r12, true); // {NF}imul r29, r12 IID626 + __ eimulq(r30, r30, true); // {NF}imul r30, r30 IID627 + __ elzcntq(r24, r15, false); // {EVEX}lzcnt r24, r15 IID628 + __ elzcntq(r25, r25, false); // {EVEX}lzcnt r25, r25 IID629 + __ elzcntq(r25, r21, true); // {NF}lzcnt r25, r21 IID630 + __ elzcntq(r22, r22, true); // {NF}lzcnt r22, r22 IID631 + __ enegq(r17, r30, false); // {EVEX}neg r17, r30 IID632 + __ enegq(r17, r17, false); // neg r17 IID633 + __ enegq(r31, r17, true); // {NF}neg r31, r17 IID634 + __ enegq(r29, r29, true); // {NF}neg r29, r29 IID635 + __ enotq(r10, r9); // {EVEX}not r10, r9 IID636 + __ enotq(r24, r24); // not r24 IID637 + __ epopcntq(r28, r15, false); // {EVEX}popcnt r28, r15 IID638 + __ epopcntq(r10, r10, false); // {EVEX}popcnt r10, r10 IID639 + __ epopcntq(r27, r30, true); // {NF}popcnt r27, r30 IID640 + __ epopcntq(r28, r28, true); // {NF}popcnt r28, r28 IID641 + __ erolq(r28, r14, false); // {EVEX}rol r28, r14, cl IID642 + __ erolq(r23, r23, false); // rol r23, cl IID643 + __ erolq(r23, r24, true); // {NF}rol r23, r24, cl IID644 + __ erolq(r21, r21, true); // {NF}rol r21, r21, cl IID645 + __ erorq(r31, r22, false); // {EVEX}ror r31, r22, cl IID646 + __ erorq(r28, r28, false); // ror r28, cl IID647 + __ erorq(r17, r10, true); // {NF}ror r17, r10, cl IID648 + __ erorq(r9, r9, true); // {NF}ror r9, r9, cl IID649 + __ esalq(r29, r30, false); // {EVEX}sal r29, r30, cl IID650 + __ esalq(r11, r11, false); // sal r11, cl IID651 + __ esalq(r26, r11, true); // {NF}sal r26, r11, cl IID652 + __ esalq(r16, r16, true); // {NF}sal r16, r16, cl IID653 + __ esarq(rbx, r15, false); // {EVEX}sar rbx, r15, cl IID654 + __ esarq(r14, r14, false); // sar r14, cl IID655 + __ esarq(r25, r16, true); // {NF}sar r25, r16, cl IID656 + __ esarq(r8, r8, true); // {NF}sar r8, r8, cl IID657 + __ edecq(r11, r13, false); // {EVEX}dec r11, r13 IID658 + __ edecq(rcx, rcx, false); // dec rcx IID659 + __ edecq(r21, r18, true); // {NF}dec r21, r18 IID660 + __ edecq(r28, r28, true); // {NF}dec r28, r28 IID661 + __ eincq(r16, r16, false); // inc r16 IID662 + __ eincq(r29, r29, false); // inc r29 IID663 + __ eincq(r18, r9, true); // {NF}inc r18, r9 IID664 + __ eincq(r19, r19, true); // {NF}inc r19, r19 IID665 + __ eshlq(r19, r18, false); // {EVEX}shl r19, r18, cl IID666 + __ eshlq(r8, r8, false); // shl r8, cl IID667 + __ eshlq(r12, r15, true); // {NF}shl r12, r15, cl IID668 + __ eshlq(r29, r29, true); // {NF}shl r29, r29, cl IID669 + __ eshrq(r28, r24, false); // {EVEX}shr r28, r24, cl IID670 + __ eshrq(r19, r19, false); // shr r19, cl IID671 + __ eshrq(r8, r28, true); // {NF}shr r8, r28, cl IID672 + __ eshrq(r17, r17, true); // {NF}shr r17, r17, cl IID673 + __ etzcntq(r28, r16, false); // {EVEX}tzcnt r28, r16 IID674 + __ etzcntq(r14, r14, false); // {EVEX}tzcnt r14, r14 IID675 + __ etzcntq(r12, r31, true); // {NF}tzcnt r12, r31 IID676 + __ etzcntq(r14, r14, true); // {NF}tzcnt r14, r14 IID677 + __ eimulq(r31, Address(r13, -0x69c4b352), false); // {EVEX}imul r31, qword ptr [r13-0x69c4b352] IID678 + __ eimulq(r17, Address(r18, -0x60ab1105), true); // {NF}imul r17, qword ptr [r18-0x60ab1105] IID679 + __ elzcntq(r27, Address(r14, r25, (Address::ScaleFactor)2, +0x2798bf83), false); // {EVEX}lzcnt r27, qword ptr [r14+r25*4+0x2798bf83] IID680 + __ elzcntq(r23, Address(r10, r11, (Address::ScaleFactor)0, -0x378e635d), true); // {NF}lzcnt r23, qword ptr [r10+r11*1-0x378e635d] IID681 + __ enegq(rcx, Address(r19, r9, (Address::ScaleFactor)3, -0x6847d440), false); // {EVEX}neg rcx, qword ptr [r19+r9*8-0x6847d440] IID682 + __ enegq(rcx, Address(rbx, rcx, (Address::ScaleFactor)0, +0x6f92d38d), true); // {NF}neg rcx, qword ptr [rbx+rcx*1+0x6f92d38d] IID683 + __ epopcntq(r20, Address(r12, -0x2a8b27d6), false); // {EVEX}popcnt r20, qword ptr [r12-0x2a8b27d6] IID684 + __ epopcntq(r31, Address(r30, +0x4603f6d0), true); // {NF}popcnt r31, qword ptr [r30+0x4603f6d0] IID685 + __ esalq(rbx, Address(r24, +0x567d06f9), false); // {EVEX}sal rbx, qword ptr [r24+0x567d06f9], cl IID686 + __ esalq(r12, Address(r24, r28, (Address::ScaleFactor)0, -0x1c4c584e), true); // {NF}sal r12, qword ptr [r24+r28*1-0x1c4c584e], cl IID687 + __ esarq(r12, Address(r23, r24, (Address::ScaleFactor)2, -0x3157bcba), false); // {EVEX}sar r12, qword ptr [r23+r24*4-0x3157bcba], cl IID688 + __ esarq(r8, Address(r14, r24, (Address::ScaleFactor)2, -0x714290a5), true); // {NF}sar r8, qword ptr [r14+r24*4-0x714290a5], cl IID689 + __ edecq(r23, Address(r8, r15, (Address::ScaleFactor)1, -0x5ae272dd), false); // {EVEX}dec r23, qword ptr [r8+r15*2-0x5ae272dd] IID690 + __ edecq(r13, Address(r29, r9, (Address::ScaleFactor)3, -0x5b5174a9), true); // {NF}dec r13, qword ptr [r29+r9*8-0x5b5174a9] IID691 + __ eincq(r11, Address(r21, r31, (Address::ScaleFactor)3, -0x2176b4dc), false); // {EVEX}inc r11, qword ptr [r21+r31*8-0x2176b4dc] IID692 + __ eincq(r13, Address(rcx, r16, (Address::ScaleFactor)0, -0x36b448c9), true); // {NF}inc r13, qword ptr [rcx+r16*1-0x36b448c9] IID693 + __ eshrq(r26, Address(r25, rcx, (Address::ScaleFactor)2, -0x5f894993), false); // {EVEX}shr r26, qword ptr [r25+rcx*4-0x5f894993], cl IID694 + __ eshrq(r25, Address(r9, +0x51798d21), true); // {NF}shr r25, qword ptr [r9+0x51798d21], cl IID695 + __ etzcntq(r28, Address(r13, r26, (Address::ScaleFactor)2, +0x207196f6), false); // {EVEX}tzcnt r28, qword ptr [r13+r26*4+0x207196f6] IID696 + __ etzcntq(rbx, Address(r19, r13, (Address::ScaleFactor)0, -0x24d937d5), true); // {NF}tzcnt rbx, qword ptr [r19+r13*1-0x24d937d5] IID697 + __ eaddq(r17, Address(r30, +0x3935ccff), r31, false); // {EVEX}add r17, qword ptr [r30+0x3935ccff], r31 IID698 + __ eaddq(r14, Address(r27, r10, (Address::ScaleFactor)2, -0x34ad9bab), r14, false); // {EVEX}add r14, qword ptr [r27+r10*4-0x34ad9bab], r14 IID699 + __ eaddq(r18, Address(r20, r23, (Address::ScaleFactor)0, +0x5ad3ed4b), r30, true); // {NF}add r18, qword ptr [r20+r23*1+0x5ad3ed4b], r30 IID700 + __ eaddq(r20, Address(rdx, -0x322a99e5), r20, true); // {NF}add r20, qword ptr [rdx-0x322a99e5], r20 IID701 + __ eandq(r31, Address(rbx, r27, (Address::ScaleFactor)3, +0x4ce247d2), r17, false); // {EVEX}and r31, qword ptr [rbx+r27*8+0x4ce247d2], r17 IID702 + __ eandq(r30, Address(r18, r19, (Address::ScaleFactor)1, -0x4ee3d14), r30, false); // {EVEX}and r30, qword ptr [r18+r19*2-0x4ee3d14], r30 IID703 + __ eandq(r28, Address(r11, rbx, (Address::ScaleFactor)3, -0x28994bbf), r24, true); // {NF}and r28, qword ptr [r11+rbx*8-0x28994bbf], r24 IID704 + __ eandq(r30, Address(r22, +0x7d21c24), r30, true); // {NF}and r30, qword ptr [r22+0x7d21c24], r30 IID705 + __ eorq(r26, Address(r15, r19, (Address::ScaleFactor)3, +0x58c21792), r20, false); // {EVEX}or r26, qword ptr [r15+r19*8+0x58c21792], r20 IID706 + __ eorq(r13, Address(r10, r27, (Address::ScaleFactor)2, -0x2c70d333), r13, false); // {EVEX}or r13, qword ptr [r10+r27*4-0x2c70d333], r13 IID707 + __ eorq(rbx, Address(r12, rbx, (Address::ScaleFactor)0, -0x1fb0f1bc), r26, true); // {NF}or rbx, qword ptr [r12+rbx*1-0x1fb0f1bc], r26 IID708 + __ eorq(r31, Address(r27, r31, (Address::ScaleFactor)1, +0x28d1756), r31, true); // {NF}or r31, qword ptr [r27+r31*2+0x28d1756], r31 IID709 + __ esubq(r24, Address(r28, r23, (Address::ScaleFactor)1, +0x6980f610), r27, false); // {EVEX}sub r24, qword ptr [r28+r23*2+0x6980f610], r27 IID710 + __ esubq(r15, Address(r11, r30, (Address::ScaleFactor)3, -0x49777e7), r15, false); // {EVEX}sub r15, qword ptr [r11+r30*8-0x49777e7], r15 IID711 + __ esubq(r17, Address(r25, r13, (Address::ScaleFactor)2, +0x31619e46), r31, true); // {NF}sub r17, qword ptr [r25+r13*4+0x31619e46], r31 IID712 + __ esubq(r18, Address(r11, r10, (Address::ScaleFactor)2, +0x1922861a), r18, true); // {NF}sub r18, qword ptr [r11+r10*4+0x1922861a], r18 IID713 + __ exorq(rbx, Address(r11, -0x4716d420), r21, false); // {EVEX}xor rbx, qword ptr [r11-0x4716d420], r21 IID714 + __ exorq(r8, Address(rdx, r9, (Address::ScaleFactor)2, -0x4cfe39c), r8, false); // {EVEX}xor r8, qword ptr [rdx+r9*4-0x4cfe39c], r8 IID715 + __ exorq(r16, Address(r14, r27, (Address::ScaleFactor)0, +0x7c6654d9), r25, true); // {NF}xor r16, qword ptr [r14+r27*1+0x7c6654d9], r25 IID716 + __ exorq(r29, Address(r15, -0x5efab479), r29, true); // {NF}xor r29, qword ptr [r15-0x5efab479], r29 IID717 + __ eaddq(r19, Address(r13, r22, (Address::ScaleFactor)2, +0x68b64559), 16777216, false); // {EVEX}add r19, qword ptr [r13+r22*4+0x68b64559], 16777216 IID718 + __ eaddq(r16, Address(r13, r31, (Address::ScaleFactor)3, -0x65143af5), 1, true); // {NF}add r16, qword ptr [r13+r31*8-0x65143af5], 1 IID719 + __ eandq(r31, Address(r24, r13, (Address::ScaleFactor)1, -0x25b16a0e), 1, false); // {EVEX}and r31, qword ptr [r24+r13*2-0x25b16a0e], 1 IID720 + __ eandq(r11, Address(r28, -0xf6d4b26), 65536, true); // {NF}and r11, qword ptr [r28-0xf6d4b26], 65536 IID721 + __ eimulq(rcx, Address(r18, r10, (Address::ScaleFactor)0, +0x46ec6da1), 16777216, false); // {EVEX}imul rcx, qword ptr [r18+r10*1+0x46ec6da1], 16777216 IID722 + __ eimulq(r15, Address(r9, r10, (Address::ScaleFactor)3, -0x7fc36af3), 16, true); // {NF}imul r15, qword ptr [r9+r10*8-0x7fc36af3], 16 IID723 + __ eorq(r17, Address(r27, r30, (Address::ScaleFactor)0, +0x1b4cda2c), 1, false); // {EVEX}or r17, qword ptr [r27+r30*1+0x1b4cda2c], 1 IID724 + __ eorq(rdx, Address(r25, r14, (Address::ScaleFactor)2, -0x59aa6b85), 4096, true); // {NF}or rdx, qword ptr [r25+r14*4-0x59aa6b85], 4096 IID725 + __ esalq(r17, Address(r26, r21, (Address::ScaleFactor)1, -0x6ab1f15f), 8, false); // {EVEX}sal r17, qword ptr [r26+r21*2-0x6ab1f15f], 8 IID726 + __ esalq(r12, Address(r22, r17, (Address::ScaleFactor)0, -0x43ac14ab), 2, true); // {NF}sal r12, qword ptr [r22+r17*1-0x43ac14ab], 2 IID727 + __ esarq(r29, Address(r18, r16, (Address::ScaleFactor)0, -0x59dc0c61), 4, false); // {EVEX}sar r29, qword ptr [r18+r16*1-0x59dc0c61], 4 IID728 + __ esarq(r16, Address(r11, -0x7bdd314), 4, true); // {NF}sar r16, qword ptr [r11-0x7bdd314], 4 IID729 + __ eshrq(r26, Address(r23, r27, (Address::ScaleFactor)3, -0x55b92314), 16, false); // {EVEX}shr r26, qword ptr [r23+r27*8-0x55b92314], 16 IID730 + __ eshrq(r23, Address(r16, r29, (Address::ScaleFactor)1, +0x71311a1d), 2, true); // {NF}shr r23, qword ptr [r16+r29*2+0x71311a1d], 2 IID731 + __ esubq(r25, Address(r9, -0x9532bac), 1048576, false); // {EVEX}sub r25, qword ptr [r9-0x9532bac], 1048576 IID732 + __ esubq(r17, Address(r8, r23, (Address::ScaleFactor)0, +0x55d06ca2), 1048576, true); // {NF}sub r17, qword ptr [r8+r23*1+0x55d06ca2], 1048576 IID733 + __ exorq(r29, Address(r9, r24, (Address::ScaleFactor)0, -0x2c141c1), 1048576, false); // {EVEX}xor r29, qword ptr [r9+r24*1-0x2c141c1], 1048576 IID734 + __ exorq(r28, Address(r22, r19, (Address::ScaleFactor)1, -0x2d9d9abd), 16, true); // {NF}xor r28, qword ptr [r22+r19*2-0x2d9d9abd], 16 IID735 + __ eaddq(r22, r14, 16, false); // {EVEX}add r22, r14, 16 IID736 + __ eaddq(rax, r12, 16, false); // {EVEX}add rax, r12, 16 IID737 + __ eaddq(r24, r24, 65536, false); // add r24, 65536 IID738 + __ eaddq(r21, rbx, 65536, true); // {NF}add r21, rbx, 65536 IID739 + __ eaddq(rax, rbx, 65536, true); // {NF}add rax, rbx, 65536 IID740 + __ eaddq(r24, r24, 65536, true); // {NF}add r24, r24, 65536 IID741 + __ eandq(r21, r27, 16777216, false); // {EVEX}and r21, r27, 16777216 IID742 + __ eandq(rax, r27, 16777216, false); // {EVEX}and rax, r27, 16777216 IID743 + __ eandq(r24, r24, 65536, false); // and r24, 65536 IID744 + __ eandq(r13, r31, 1048576, true); // {NF}and r13, r31, 1048576 IID745 + __ eandq(rax, r21, 1048576, true); // {NF}and rax, r21, 1048576 IID746 + __ eandq(r30, r30, 1048576, true); // {NF}and r30, r30, 1048576 IID747 + __ eimulq(r8, r13, 268435456, false); // {EVEX}imul r8, r13, 268435456 IID748 + __ eimulq(rax, r31, 268435456, false); // {EVEX}imul rax, r31, 268435456 IID749 + __ eimulq(r13, r13, 65536, false); // {EVEX}imul r13, r13, 65536 IID750 + __ eimulq(r14, r29, 1048576, true); // {NF}imul r14, r29, 1048576 IID751 + __ eimulq(rax, r22, 1048576, true); // {NF}imul rax, r22, 1048576 IID752 + __ eimulq(r8, r8, 268435456, true); // {NF}imul r8, r8, 268435456 IID753 + __ eorq(r30, r15, 4096, false); // {EVEX}or r30, r15, 4096 IID754 + __ eorq(rax, r28, 4096, false); // {EVEX}or rax, r28, 4096 IID755 + __ eorq(r26, r26, 1048576, false); // or r26, 1048576 IID756 + __ eorq(r16, r12, 268435456, true); // {NF}or r16, r12, 268435456 IID757 + __ eorq(rax, r9, 268435456, true); // {NF}or rax, r9, 268435456 IID758 + __ eorq(r23, r23, 256, true); // {NF}or r23, r23, 256 IID759 + __ erclq(r15, r9, 16); // {EVEX}rcl r15, r9, 16 IID760 + __ erclq(rax, r8, 16); // {EVEX}rcl rax, r8, 16 IID761 + __ erclq(r25, r25, 1); // rcl r25, 1 IID762 + __ erolq(r9, r17, 16, false); // {EVEX}rol r9, r17, 16 IID763 + __ erolq(rax, r20, 16, false); // {EVEX}rol rax, r20, 16 IID764 + __ erolq(r27, r27, 1, false); // rol r27, 1 IID765 + __ erolq(r20, r31, 1, true); // {NF}rol r20, r31, 1 IID766 + __ erolq(rax, r18, 1, true); // {NF}rol rax, r18, 1 IID767 + __ erolq(r28, r28, 16, true); // {NF}rol r28, r28, 16 IID768 + __ erorq(r26, r18, 16, false); // {EVEX}ror r26, r18, 16 IID769 + __ erorq(rax, r24, 16, false); // {EVEX}ror rax, r24, 16 IID770 + __ erorq(r22, r22, 16, false); // ror r22, 16 IID771 + __ erorq(r27, r29, 1, true); // {NF}ror r27, r29, 1 IID772 + __ erorq(rax, r18, 1, true); // {NF}ror rax, r18, 1 IID773 + __ erorq(r21, r21, 1, true); // {NF}ror r21, r21, 1 IID774 + __ esalq(r12, rcx, 2, false); // {EVEX}sal r12, rcx, 2 IID775 + __ esalq(rax, r24, 2, false); // {EVEX}sal rax, r24, 2 IID776 + __ esalq(r22, r22, 8, false); // sal r22, 8 IID777 + __ esalq(r17, r23, 8, true); // {NF}sal r17, r23, 8 IID778 + __ esalq(rax, r27, 8, true); // {NF}sal rax, r27, 8 IID779 + __ esalq(r23, r23, 1, true); // {NF}sal r23, r23, 1 IID780 + __ esarq(r8, r25, 16, false); // {EVEX}sar r8, r25, 16 IID781 + __ esarq(rax, r23, 16, false); // {EVEX}sar rax, r23, 16 IID782 + __ esarq(r9, r9, 4, false); // sar r9, 4 IID783 + __ esarq(r22, r13, 1, true); // {NF}sar r22, r13, 1 IID784 + __ esarq(rax, r11, 1, true); // {NF}sar rax, r11, 1 IID785 + __ esarq(r12, r12, 2, true); // {NF}sar r12, r12, 2 IID786 + __ eshlq(rcx, r30, 8, false); // {EVEX}shl rcx, r30, 8 IID787 + __ eshlq(rax, r19, 8, false); // {EVEX}shl rax, r19, 8 IID788 + __ eshlq(r13, r13, 2, false); // shl r13, 2 IID789 + __ eshlq(r18, r11, 8, true); // {NF}shl r18, r11, 8 IID790 + __ eshlq(rax, r9, 8, true); // {NF}shl rax, r9, 8 IID791 + __ eshlq(rcx, rcx, 16, true); // {NF}shl rcx, rcx, 16 IID792 + __ eshrq(r10, r22, 4, false); // {EVEX}shr r10, r22, 4 IID793 + __ eshrq(rax, r9, 4, false); // {EVEX}shr rax, r9, 4 IID794 + __ eshrq(r12, r12, 2, false); // shr r12, 2 IID795 + __ eshrq(r26, r31, 8, true); // {NF}shr r26, r31, 8 IID796 + __ eshrq(rax, r12, 8, true); // {NF}shr rax, r12, 8 IID797 + __ eshrq(r28, r28, 1, true); // {NF}shr r28, r28, 1 IID798 + __ esubq(r15, r30, 65536, false); // {EVEX}sub r15, r30, 65536 IID799 + __ esubq(rax, rcx, 65536, false); // {EVEX}sub rax, rcx, 65536 IID800 + __ esubq(r26, r26, 16, false); // sub r26, 16 IID801 + __ esubq(r12, r14, 1, true); // {NF}sub r12, r14, 1 IID802 + __ esubq(rax, r21, 1, true); // {NF}sub rax, r21, 1 IID803 + __ esubq(r20, r20, 1048576, true); // {NF}sub r20, r20, 1048576 IID804 + __ exorq(r11, rbx, 16777216, false); // {EVEX}xor r11, rbx, 16777216 IID805 + __ exorq(rax, r23, 16777216, false); // {EVEX}xor rax, r23, 16777216 IID806 + __ exorq(r31, r31, 268435456, false); // xor r31, 268435456 IID807 + __ exorq(r29, r28, 4096, true); // {NF}xor r29, r28, 4096 IID808 + __ exorq(rax, r19, 4096, true); // {NF}xor rax, r19, 4096 IID809 + __ exorq(rdx, rdx, 268435456, true); // {NF}xor rdx, rdx, 268435456 IID810 + __ eorq_imm32(rdx, rdx, 1048576, false); // or rdx, 1048576 IID811 + __ eorq_imm32(rax, r22, 1048576, false); // {EVEX}or rax, r22, 1048576 IID812 + __ eorq_imm32(r29, r29, 1048576, false); // or r29, 1048576 IID813 + __ eorq_imm32(r17, rcx, 4194304, false); // {EVEX}or r17, rcx, 4194304 IID814 + __ eorq_imm32(rax, r25, 4194304, false); // {EVEX}or rax, r25, 4194304 IID815 + __ eorq_imm32(r27, r27, 1073741824, false); // or r27, 1073741824 IID816 + __ esubq_imm32(r16, r19, 4194304, false); // {EVEX}sub r16, r19, 4194304 IID817 + __ esubq_imm32(rax, r31, 4194304, false); // {EVEX}sub rax, r31, 4194304 IID818 + __ esubq_imm32(r26, r26, 262144, false); // sub r26, 262144 IID819 + __ esubq_imm32(r17, r22, 1073741824, true); // {NF}sub r17, r22, 1073741824 IID820 + __ esubq_imm32(rax, r18, 1073741824, true); // {NF}sub rax, r18, 1073741824 IID821 + __ esubq_imm32(r23, r23, 268435456, true); // {NF}sub r23, r23, 268435456 IID822 + __ eaddq(r13, r30, Address(r24, r19, (Address::ScaleFactor)1, +0x56ea3a3b), false); // {EVEX}add r13, r30, qword ptr [r24+r19*2+0x56ea3a3b] IID823 + __ eaddq(r29, r15, Address(r26, r27, (Address::ScaleFactor)3, -0x4b113958), true); // {NF}add r29, r15, qword ptr [r26+r27*8-0x4b113958] IID824 + __ eandq(r12, r30, Address(r31, -0x46103c74), false); // {EVEX}and r12, r30, qword ptr [r31-0x46103c74] IID825 + __ eandq(r27, r10, Address(r22, r25, (Address::ScaleFactor)1, +0x6a1ebee5), true); // {NF}and r27, r10, qword ptr [r22+r25*2+0x6a1ebee5] IID826 + __ eorq(r30, r26, Address(r11, r18, (Address::ScaleFactor)2, -0x2b9fff29), false); // {EVEX}or r30, r26, qword ptr [r11+r18*4-0x2b9fff29] IID827 + __ eorq(r9, r12, Address(r18, r17, (Address::ScaleFactor)0, +0xb4859f6), true); // {NF}or r9, r12, qword ptr [r18+r17*1+0xb4859f6] IID828 + __ eimulq(rdx, r17, Address(r24, rdx, (Address::ScaleFactor)2, +0x3d284cd8), false); // {EVEX}imul rdx, r17, qword ptr [r24+rdx*4+0x3d284cd8] IID829 + __ eimulq(r29, r26, Address(r30, r12, (Address::ScaleFactor)1, +0x6e813124), true); // {NF}imul r29, r26, qword ptr [r30+r12*2+0x6e813124] IID830 + __ esubq(rbx, r13, Address(r22, -0x702a289e), false); // {EVEX}sub rbx, r13, qword ptr [r22-0x702a289e] IID831 + __ esubq(r23, r29, Address(r25, rdx, (Address::ScaleFactor)0, -0x6252a7ed), true); // {NF}sub r23, r29, qword ptr [r25+rdx*1-0x6252a7ed] IID832 + __ exorq(r8, r18, Address(r19, r14, (Address::ScaleFactor)2, -0xebfa697), false); // {EVEX}xor r8, r18, qword ptr [r19+r14*4-0xebfa697] IID833 + __ exorq(r10, r28, Address(r26, +0x168381ca), true); // {NF}xor r10, r28, qword ptr [r26+0x168381ca] IID834 + __ eaddq(rcx, r18, r8, false); // {load}{EVEX}add rcx, r18, r8 IID835 + __ eaddq(rcx, rcx, r14, false); // {load}add rcx, r14 IID836 + __ eaddq(r23, r10, r16, true); // {load}{NF}add r23, r10, r16 IID837 + __ eaddq(r11, r11, r24, true); // {load}{NF}add r11, r11, r24 IID838 + __ eadcxq(r9, r18, rdx); // {load}{EVEX}adcx r9, r18, rdx IID839 + __ eadcxq(r8, r8, r15); // {load}adcx r8, r15 IID840 + __ eadoxq(r15, r22, r26); // {load}{EVEX}adox r15, r22, r26 IID841 + __ eadoxq(r11, r11, rdx); // {load}adox r11, rdx IID842 + __ eandq(r19, rdx, r22, false); // {load}{EVEX}and r19, rdx, r22 IID843 + __ eandq(r29, r29, r17, false); // {load}and r29, r17 IID844 + __ eandq(r23, r27, r15, true); // {load}{NF}and r23, r27, r15 IID845 + __ eandq(r9, r9, r13, true); // {load}{NF}and r9, r9, r13 IID846 + __ eimulq(r18, r15, r16, false); // {load}{EVEX}imul r18, r15, r16 IID847 + __ eimulq(rcx, rcx, r17, false); // {load}imul rcx, r17 IID848 + __ eimulq(r23, r12, r20, true); // {load}{NF}imul r23, r12, r20 IID849 + __ eimulq(r10, r10, r9, true); // {load}{NF}imul r10, r10, r9 IID850 + __ eorq(rdx, r19, r14, false); // {load}{EVEX}or rdx, r19, r14 IID851 + __ eorq(rcx, rcx, r13, false); // {load}or rcx, r13 IID852 + __ eorq(r9, r25, r29, true); // {load}{NF}or r9, r25, r29 IID853 + __ eorq(rdx, rdx, r25, true); // {load}{NF}or rdx, rdx, r25 IID854 + __ esubq(r23, r8, r16, false); // {load}{EVEX}sub r23, r8, r16 IID855 + __ esubq(r13, r13, r13, false); // {load}sub r13, r13 IID856 + __ esubq(r19, r12, r15, true); // {load}{NF}sub r19, r12, r15 IID857 + __ esubq(r9, r9, rdx, true); // {load}{NF}sub r9, r9, rdx IID858 + __ exorq(r13, r16, r31, false); // {load}{EVEX}xor r13, r16, r31 IID859 + __ exorq(r17, r17, r30, false); // {load}xor r17, r30 IID860 + __ exorq(r19, r30, r20, true); // {load}{NF}xor r19, r30, r20 IID861 + __ exorq(r31, r31, r13, true); // {load}{NF}xor r31, r31, r13 IID862 + __ eshldq(r22, r10, r13, 4, false); // {EVEX}shld r22, r10, r13, 4 IID863 + __ eshldq(r24, r24, r21, 16, false); // shld r24, r21, 16 IID864 + __ eshldq(r20, r13, r27, 16, true); // {NF}shld r20, r13, r27, 16 IID865 + __ eshldq(r31, r31, r19, 2, true); // {NF}shld r31, r31, r19, 2 IID866 + __ eshrdq(r30, r20, r11, 8, false); // {EVEX}shrd r30, r20, r11, 8 IID867 + __ eshrdq(rdx, rdx, r15, 1, false); // shrd rdx, r15, 1 IID868 + __ eshrdq(r28, r30, r14, 2, true); // {NF}shrd r28, r30, r14, 2 IID869 + __ eshrdq(r20, r20, r16, 1, true); // {NF}shrd r20, r20, r16, 1 IID870 + __ ecmovq (Assembler::Condition::overflow, r21, r17, r28); // cmovo r21, r17, r28 IID871 + __ ecmovq (Assembler::Condition::overflow, r15, r15, r30); // cmovo r15, r30 IID872 + __ ecmovq (Assembler::Condition::noOverflow, rcx, r15, r15); // cmovno rcx, r15, r15 IID873 + __ ecmovq (Assembler::Condition::noOverflow, rcx, rcx, r13); // cmovno rcx, r13 IID874 + __ ecmovq (Assembler::Condition::below, rdx, r26, r26); // cmovb rdx, r26, r26 IID875 + __ ecmovq (Assembler::Condition::below, r28, r28, r15); // cmovb r28, r15 IID876 + __ ecmovq (Assembler::Condition::aboveEqual, r8, rdx, rcx); // cmovae r8, rdx, rcx IID877 + __ ecmovq (Assembler::Condition::aboveEqual, rcx, rcx, rcx); // cmovae rcx, rcx IID878 + __ ecmovq (Assembler::Condition::zero, r10, r13, r9); // cmovz r10, r13, r9 IID879 + __ ecmovq (Assembler::Condition::zero, r14, r14, r27); // cmovz r14, r27 IID880 + __ ecmovq (Assembler::Condition::notZero, r11, r23, r9); // cmovnz r11, r23, r9 IID881 + __ ecmovq (Assembler::Condition::notZero, r11, r11, rdx); // cmovnz r11, rdx IID882 + __ ecmovq (Assembler::Condition::belowEqual, r31, r14, r25); // cmovbe r31, r14, r25 IID883 + __ ecmovq (Assembler::Condition::belowEqual, r20, r20, r12); // cmovbe r20, r12 IID884 + __ ecmovq (Assembler::Condition::above, rdx, r10, r28); // cmova rdx, r10, r28 IID885 + __ ecmovq (Assembler::Condition::above, r8, r8, r17); // cmova r8, r17 IID886 + __ ecmovq (Assembler::Condition::negative, rcx, r30, r23); // cmovs rcx, r30, r23 IID887 + __ ecmovq (Assembler::Condition::negative, r26, r26, r18); // cmovs r26, r18 IID888 + __ ecmovq (Assembler::Condition::positive, rdx, rbx, r18); // cmovns rdx, rbx, r18 IID889 + __ ecmovq (Assembler::Condition::positive, r21, r21, r13); // cmovns r21, r13 IID890 + __ ecmovq (Assembler::Condition::parity, r27, r28, r27); // cmovp r27, r28, r27 IID891 + __ ecmovq (Assembler::Condition::parity, r11, r11, r30); // cmovp r11, r30 IID892 + __ ecmovq (Assembler::Condition::noParity, rcx, r21, r18); // cmovnp rcx, r21, r18 IID893 + __ ecmovq (Assembler::Condition::noParity, rcx, rcx, r29); // cmovnp rcx, r29 IID894 + __ ecmovq (Assembler::Condition::less, rdx, r21, r12); // cmovl rdx, r21, r12 IID895 + __ ecmovq (Assembler::Condition::less, rdx, rdx, r26); // cmovl rdx, r26 IID896 + __ ecmovq (Assembler::Condition::greaterEqual, r17, rbx, r22); // cmovge r17, rbx, r22 IID897 + __ ecmovq (Assembler::Condition::greaterEqual, rdx, rdx, r11); // cmovge rdx, r11 IID898 + __ ecmovq (Assembler::Condition::lessEqual, rdx, r14, r8); // cmovle rdx, r14, r8 IID899 + __ ecmovq (Assembler::Condition::lessEqual, r14, r14, r8); // cmovle r14, r8 IID900 + __ ecmovq (Assembler::Condition::greater, r25, r29, r21); // cmovg r25, r29, r21 IID901 + __ ecmovq (Assembler::Condition::greater, r26, r26, r30); // cmovg r26, r30 IID902 + __ ecmovq (Assembler::Condition::overflow, r24, r21, Address(r13, r11, (Address::ScaleFactor)1, +0x439c521e)); // cmovo r24, r21, qword ptr [r13+r11*2+0x439c521e] IID903 + __ ecmovq (Assembler::Condition::noOverflow, r11, r18, Address(r29, r16, (Address::ScaleFactor)0, +0x632127f)); // cmovno r11, r18, qword ptr [r29+r16*1+0x632127f] IID904 + __ ecmovq (Assembler::Condition::below, r16, r8, Address(r8, r26, (Address::ScaleFactor)1, +0x10633def)); // cmovb r16, r8, qword ptr [r8+r26*2+0x10633def] IID905 + __ ecmovq (Assembler::Condition::aboveEqual, r13, r14, Address(r18, -0x54f69e38)); // cmovae r13, r14, qword ptr [r18-0x54f69e38] IID906 + __ ecmovq (Assembler::Condition::zero, r12, r8, Address(r31, r26, (Address::ScaleFactor)1, -0x7a1e447a)); // cmovz r12, r8, qword ptr [r31+r26*2-0x7a1e447a] IID907 + __ ecmovq (Assembler::Condition::notZero, r29, r29, Address(r19, r11, (Address::ScaleFactor)2, -0x35d82dd2)); // cmovnz r29, qword ptr [r19+r11*4-0x35d82dd2] IID908 + __ ecmovq (Assembler::Condition::belowEqual, rcx, r18, Address(r25, r28, (Address::ScaleFactor)0, +0x30be64a0)); // cmovbe rcx, r18, qword ptr [r25+r28*1+0x30be64a0] IID909 + __ ecmovq (Assembler::Condition::above, r28, r12, Address(r10, r16, (Address::ScaleFactor)1, -0x22b8fefa)); // cmova r28, r12, qword ptr [r10+r16*2-0x22b8fefa] IID910 + __ ecmovq (Assembler::Condition::negative, r11, r8, Address(rbx, r11, (Address::ScaleFactor)3, +0x25cc9e96)); // cmovs r11, r8, qword ptr [rbx+r11*8+0x25cc9e96] IID911 + __ ecmovq (Assembler::Condition::positive, r12, r27, Address(r11, -0xc2d70fe)); // cmovns r12, r27, qword ptr [r11-0xc2d70fe] IID912 + __ ecmovq (Assembler::Condition::parity, r8, r26, Address(r19, rbx, (Address::ScaleFactor)1, -0x486db7ea)); // cmovp r8, r26, qword ptr [r19+rbx*2-0x486db7ea] IID913 + __ ecmovq (Assembler::Condition::noParity, r30, r10, Address(r14, r18, (Address::ScaleFactor)3, +0x14884884)); // cmovnp r30, r10, qword ptr [r14+r18*8+0x14884884] IID914 + __ ecmovq (Assembler::Condition::less, r27, r8, Address(r29, r14, (Address::ScaleFactor)2, +0x92b7a8)); // cmovl r27, r8, qword ptr [r29+r14*4+0x92b7a8] IID915 + __ ecmovq (Assembler::Condition::greaterEqual, r14, r28, Address(r19, rdx, (Address::ScaleFactor)0, +0x9c2d45)); // cmovge r14, r28, qword ptr [r19+rdx*1+0x9c2d45] IID916 + __ ecmovq (Assembler::Condition::lessEqual, r25, r8, Address(rcx, r18, (Address::ScaleFactor)2, +0x6655c86b)); // cmovle r25, r8, qword ptr [rcx+r18*4+0x6655c86b] IID917 + __ ecmovq (Assembler::Condition::greater, r19, r21, Address(r10, r25, (Address::ScaleFactor)0, -0x1005430b)); // cmovg r19, r21, qword ptr [r10+r25*1-0x1005430b] IID918 #endif // _LP64 static const uint8_t insns[] = @@ -927,545 +1145,763 @@ 0x62, 0xbc, 0x7c, 0x08, 0xf7, 0xa4, 0x56, 0xaa, 0x64, 0xc8, 0xc2, // IID177 0x62, 0xd4, 0x7c, 0x0c, 0xf7, 0xa3, 0x51, 0x10, 0xb6, 0xcd, // IID178 0x62, 0x7c, 0x7c, 0x08, 0xf5, 0xc8, // IID179 - 0x62, 0xcc, 0x7c, 0x0c, 0xf5, 0xfc, // IID180 - 0x62, 0xdc, 0x3c, 0x18, 0xf7, 0xde, // IID181 - 0x62, 0xd4, 0x44, 0x14, 0xf7, 0xdb, // IID182 - 0x62, 0x7c, 0x7c, 0x08, 0x88, 0xe8, // IID183 - 0x62, 0x54, 0x7c, 0x0c, 0x88, 0xdb, // IID184 - 0x62, 0xf4, 0x2c, 0x10, 0xf7, 0xd1, // IID185 - 0x62, 0xd4, 0x64, 0x18, 0xd3, 0xc2, // IID186 - 0x62, 0xdc, 0x0c, 0x1c, 0xd3, 0xc5, // IID187 - 0x62, 0xfc, 0x04, 0x18, 0xd3, 0xcc, // IID188 - 0x62, 0xd4, 0x74, 0x14, 0xd3, 0xcc, // IID189 - 0x62, 0xf4, 0x1c, 0x18, 0xd3, 0xe3, // IID190 - 0x62, 0xdc, 0x44, 0x14, 0xd3, 0xe3, // IID191 - 0x62, 0xfc, 0x14, 0x10, 0xd3, 0xfc, // IID192 - 0x62, 0xf4, 0x1c, 0x14, 0xd3, 0xfa, // IID193 - 0x62, 0xdc, 0x3c, 0x18, 0xff, 0xcb, // IID194 - 0x62, 0xd4, 0x64, 0x1c, 0xff, 0xcf, // IID195 - 0x62, 0xdc, 0x24, 0x18, 0xff, 0xc3, // IID196 - 0x62, 0xdc, 0x14, 0x14, 0xff, 0xc1, // IID197 - 0x62, 0xd4, 0x1c, 0x18, 0xd3, 0xe0, // IID198 - 0x62, 0xfc, 0x24, 0x1c, 0xd3, 0xe2, // IID199 - 0x62, 0xd4, 0x6c, 0x18, 0xd3, 0xed, // IID200 - 0x62, 0xdc, 0x44, 0x14, 0xd3, 0xe8, // IID201 - 0x62, 0x54, 0x7c, 0x08, 0xf4, 0xff, // IID202 - 0x62, 0x4c, 0x7c, 0x0c, 0xf4, 0xd4, // IID203 - 0x62, 0x9c, 0x7c, 0x08, 0xf5, 0x9c, 0x31, 0xb6, 0xfd, 0x13, 0x1c, // IID204 - 0x62, 0x1c, 0x78, 0x0c, 0xf5, 0x8c, 0xe7, 0x81, 0x74, 0x40, 0xcf, // IID205 - 0x62, 0xdc, 0x3c, 0x18, 0xf7, 0x99, 0x1e, 0xf0, 0x37, 0xf6, // IID206 - 0x62, 0xdc, 0x48, 0x14, 0xf7, 0x9c, 0x9b, 0x09, 0x7c, 0xf2, 0x38, // IID207 - 0x62, 0x84, 0x78, 0x08, 0x88, 0xac, 0xb6, 0x7b, 0x2c, 0xf9, 0x39, // IID208 - 0x62, 0x2c, 0x7c, 0x0c, 0x88, 0x94, 0xf7, 0xc3, 0xe4, 0xd1, 0x9f, // IID209 - 0x62, 0xdc, 0x30, 0x10, 0xd3, 0xa4, 0x7c, 0xef, 0x20, 0xf1, 0x4f, // IID210 - 0x62, 0xdc, 0x10, 0x14, 0xd3, 0xa4, 0xc0, 0xbd, 0x44, 0xde, 0x97, // IID211 - 0x62, 0x94, 0x40, 0x10, 0xd3, 0xbc, 0xbb, 0xbb, 0x24, 0x42, 0x7f, // IID212 - 0x62, 0xbc, 0x18, 0x1c, 0xd3, 0xbc, 0x7f, 0x58, 0x78, 0x70, 0xfd, // IID213 - 0x62, 0xbc, 0x60, 0x10, 0xff, 0x8c, 0x70, 0xf3, 0x61, 0x47, 0xd8, // IID214 - 0x62, 0xdc, 0x2c, 0x14, 0xff, 0x89, 0x48, 0x5d, 0x14, 0x3d, // IID215 - 0x62, 0x9c, 0x10, 0x18, 0xff, 0x84, 0x43, 0x62, 0x38, 0x5f, 0x62, // IID216 - 0x62, 0xfc, 0x24, 0x1c, 0xff, 0x86, 0xa6, 0x04, 0x59, 0x76, // IID217 - 0x62, 0xf4, 0x30, 0x10, 0xd3, 0xac, 0x4a, 0x91, 0xc8, 0xaf, 0x82, // IID218 - 0x62, 0xd4, 0x4c, 0x14, 0xd3, 0xac, 0x24, 0x57, 0xa2, 0xcd, 0xaf, // IID219 - 0x62, 0x54, 0x78, 0x08, 0xf4, 0xac, 0x25, 0x94, 0x17, 0x0c, 0xf4, // IID220 - 0x62, 0x44, 0x78, 0x0c, 0xf4, 0x94, 0x5e, 0x47, 0x63, 0x3a, 0xdb, // IID221 - 0x62, 0x9c, 0x48, 0x10, 0x81, 0x84, 0xbb, 0xd1, 0x6f, 0x7f, 0x80, 0x00, 0x00, 0x10, 0x00, // IID222 - 0x62, 0xf4, 0x00, 0x14, 0x81, 0x84, 0xea, 0xca, 0x3f, 0x83, 0xaa, 0x00, 0x00, 0x00, 0x10, // IID223 - 0x62, 0xdc, 0x2c, 0x18, 0x81, 0xa2, 0xf9, 0xeb, 0x6b, 0x4e, 0x00, 0x10, 0x00, 0x00, // IID224 - 0x62, 0xdc, 0x14, 0x1c, 0x81, 0xa6, 0xfd, 0xa5, 0xf1, 0x14, 0x00, 0x01, 0x00, 0x00, // IID225 - 0x62, 0x0c, 0x7c, 0x08, 0x6b, 0x9c, 0x05, 0x99, 0x87, 0x98, 0x37, 0x01, // IID226 - 0x62, 0x44, 0x7c, 0x0c, 0x69, 0x99, 0x3f, 0xd2, 0x92, 0xbb, 0x00, 0x01, 0x00, 0x00, // IID227 - 0x62, 0xbc, 0x70, 0x10, 0x83, 0x8c, 0x0c, 0xdb, 0xb5, 0x57, 0x49, 0x10, // IID228 - 0x62, 0x9c, 0x30, 0x14, 0x83, 0x8c, 0x7d, 0x3e, 0xa5, 0x26, 0x3c, 0x01, // IID229 - 0x62, 0xd4, 0x04, 0x18, 0x80, 0x89, 0xe2, 0xb5, 0x68, 0xda, 0x40, // IID230 - 0x62, 0xbc, 0x24, 0x1c, 0x80, 0x8c, 0xb8, 0x9f, 0x32, 0xa0, 0x66, 0x04, // IID231 - 0x62, 0xb4, 0x70, 0x18, 0xd1, 0xa4, 0x19, 0x5e, 0x48, 0xc6, 0x38, // IID232 - 0x62, 0x94, 0x34, 0x14, 0xc1, 0xa4, 0x10, 0x34, 0x1c, 0x13, 0x79, 0x08, // IID233 - 0x62, 0x94, 0x10, 0x18, 0xc1, 0xbc, 0xb9, 0xa9, 0x8b, 0x71, 0x12, 0x02, // IID234 - 0x62, 0xdc, 0x04, 0x1c, 0xc1, 0xb9, 0x0d, 0xc9, 0xa7, 0xaf, 0x10, // IID235 - 0x62, 0xf4, 0x00, 0x18, 0xd1, 0xac, 0x19, 0x10, 0x15, 0x5c, 0x0c, // IID236 - 0x62, 0xdc, 0x10, 0x1c, 0xc1, 0xac, 0xad, 0x64, 0xcf, 0x98, 0x93, 0x08, // IID237 - 0x62, 0x94, 0x64, 0x18, 0x81, 0xac, 0x44, 0x81, 0xf7, 0x8a, 0xca, 0x00, 0x10, 0x00, 0x00, // IID238 - 0x62, 0xf4, 0x18, 0x14, 0x81, 0xac, 0xeb, 0x48, 0xc2, 0x07, 0xaa, 0x00, 0x00, 0x01, 0x00, // IID239 - 0x62, 0xbc, 0x08, 0x10, 0x83, 0xb4, 0x15, 0xe1, 0x14, 0x4d, 0x3b, 0x01, // IID240 - 0x62, 0xfc, 0x1c, 0x14, 0x81, 0xb2, 0x5f, 0xb7, 0xdc, 0xba, 0x00, 0x00, 0x00, 0x01, // IID241 - 0x62, 0xa4, 0x6c, 0x10, 0x01, 0x84, 0x92, 0xb9, 0xe2, 0xe1, 0xe9, // IID242 - 0x62, 0xdc, 0x20, 0x14, 0x01, 0x94, 0xd1, 0xdd, 0x47, 0x64, 0x98, // IID243 - 0x62, 0x1c, 0x20, 0x10, 0x09, 0x8c, 0xef, 0x34, 0x79, 0xed, 0x19, // IID244 - 0x62, 0xc4, 0x48, 0x14, 0x09, 0x8c, 0x80, 0x88, 0xe0, 0x08, 0xe4, // IID245 - 0x62, 0x84, 0x70, 0x18, 0x08, 0x84, 0xe7, 0xcc, 0xc6, 0xb5, 0x95, // IID246 - 0x62, 0xac, 0x1c, 0x14, 0x08, 0x84, 0xa7, 0xf7, 0x49, 0x24, 0x3c, // IID247 - 0x62, 0x1c, 0x4c, 0x10, 0x29, 0x8c, 0x53, 0x91, 0xc6, 0xd6, 0xc3, // IID248 - 0x62, 0xec, 0x2c, 0x1c, 0x29, 0x88, 0x01, 0x9b, 0xaf, 0xe9, // IID249 - 0x62, 0x8c, 0x1c, 0x10, 0x31, 0xa4, 0x1e, 0x3a, 0x1e, 0x28, 0x17, // IID250 - 0x62, 0xa4, 0x68, 0x1c, 0x31, 0x8c, 0xfb, 0xdc, 0xd0, 0x53, 0x77, // IID251 - 0x62, 0x4c, 0x34, 0x18, 0x30, 0xb7, 0x8e, 0xf5, 0xa4, 0x72, // IID252 - 0x62, 0x8c, 0x3c, 0x14, 0x30, 0x84, 0x39, 0x0a, 0x1a, 0xfc, 0x20, // IID253 - 0x62, 0xf4, 0x1c, 0x18, 0x81, 0xc3, 0x00, 0x00, 0x01, 0x00, // IID254 - 0x62, 0xd4, 0x7c, 0x18, 0x81, 0xc3, 0x00, 0x00, 0x01, 0x00, // IID255 - 0x62, 0xfc, 0x3c, 0x14, 0x81, 0xc0, 0x00, 0x00, 0x00, 0x10, // IID256 - 0x62, 0xfc, 0x7c, 0x1c, 0x81, 0xc2, 0x00, 0x00, 0x00, 0x10, // IID257 - 0x62, 0xd4, 0x14, 0x10, 0x83, 0xe5, 0x01, // IID258 - 0x62, 0xd4, 0x7c, 0x18, 0x83, 0xe5, 0x01, // IID259 - 0x62, 0xfc, 0x04, 0x14, 0x83, 0xe6, 0x01, // IID260 - 0x62, 0xdc, 0x7c, 0x1c, 0x83, 0xe5, 0x01, // IID261 - 0x62, 0xcc, 0x7c, 0x08, 0x69, 0xfd, 0x00, 0x00, 0x01, 0x00, // IID262 - 0x62, 0xd4, 0x7c, 0x08, 0x69, 0xc7, 0x00, 0x00, 0x01, 0x00, // IID263 - 0x62, 0xc4, 0x7c, 0x0c, 0x69, 0xe9, 0x00, 0x00, 0x00, 0x10, // IID264 - 0x62, 0xd4, 0x7c, 0x0c, 0x69, 0xc7, 0x00, 0x00, 0x00, 0x10, // IID265 - 0x62, 0xfc, 0x6c, 0x18, 0x81, 0xca, 0x00, 0x00, 0x01, 0x00, // IID266 - 0x62, 0xd4, 0x7c, 0x18, 0x81, 0xcf, 0x00, 0x00, 0x01, 0x00, // IID267 - 0x62, 0xd4, 0x3c, 0x1c, 0x81, 0xc9, 0x00, 0x01, 0x00, 0x00, // IID268 - 0x62, 0xdc, 0x7c, 0x1c, 0x81, 0xcb, 0x00, 0x01, 0x00, 0x00, // IID269 - 0x62, 0xd4, 0x34, 0x18, 0xc1, 0xd7, 0x08, // IID270 - 0x62, 0xfc, 0x7c, 0x18, 0xc1, 0xd2, 0x08, // IID271 - 0x62, 0xf4, 0x1c, 0x18, 0xc1, 0xc3, 0x10, // IID272 - 0x62, 0xfc, 0x7c, 0x18, 0xc1, 0xc3, 0x10, // IID273 - 0x62, 0xd4, 0x2c, 0x1c, 0xc1, 0xc3, 0x10, // IID274 - 0x62, 0xfc, 0x7c, 0x1c, 0xc1, 0xc2, 0x10, // IID275 - 0x62, 0xd4, 0x6c, 0x18, 0xd1, 0xce, // IID276 - 0x62, 0xfc, 0x7c, 0x18, 0xd1, 0xce, // IID277 - 0x62, 0xdc, 0x34, 0x14, 0xc1, 0xcf, 0x10, // IID278 - 0x62, 0xfc, 0x7c, 0x1c, 0xc1, 0xcb, 0x10, // IID279 - 0x62, 0xd4, 0x34, 0x18, 0xc1, 0xe7, 0x02, // IID280 - 0x62, 0xd4, 0x7c, 0x18, 0xc1, 0xe5, 0x02, // IID281 - 0x62, 0xfc, 0x54, 0x14, 0xd1, 0xe0, // IID282 - 0x62, 0xfc, 0x7c, 0x1c, 0xd1, 0xe5, // IID283 - 0x62, 0xfc, 0x2c, 0x10, 0xc1, 0xff, 0x08, // IID284 - 0x62, 0xdc, 0x7c, 0x18, 0xc1, 0xfc, 0x08, // IID285 - 0x62, 0xd4, 0x2c, 0x14, 0xc1, 0xfe, 0x04, // IID286 - 0x62, 0xd4, 0x7c, 0x1c, 0xc1, 0xfa, 0x04, // IID287 - 0x62, 0xd4, 0x4c, 0x10, 0xd1, 0xe1, // IID288 - 0x62, 0xfc, 0x7c, 0x18, 0xd1, 0xe2, // IID289 - 0x62, 0xdc, 0x0c, 0x14, 0xc1, 0xe0, 0x10, // IID290 - 0x62, 0xfc, 0x7c, 0x1c, 0xc1, 0xe7, 0x10, // IID291 - 0x62, 0xd4, 0x24, 0x18, 0xc1, 0xe8, 0x10, // IID292 - 0x62, 0xfc, 0x7c, 0x18, 0xc1, 0xe8, 0x10, // IID293 - 0x62, 0xd4, 0x24, 0x1c, 0xc1, 0xec, 0x08, // IID294 - 0x62, 0xdc, 0x7c, 0x1c, 0xc1, 0xed, 0x08, // IID295 - 0x62, 0xfc, 0x7c, 0x10, 0x81, 0xed, 0x00, 0x00, 0x10, 0x00, // IID296 - 0x62, 0xd4, 0x7c, 0x18, 0x81, 0xef, 0x00, 0x00, 0x10, 0x00, // IID297 - 0x62, 0xfc, 0x34, 0x1c, 0x81, 0xea, 0x00, 0x00, 0x00, 0x01, // IID298 + 0x62, 0xec, 0x7c, 0x08, 0xf5, 0xff, // IID180 + 0x62, 0x44, 0x7c, 0x0c, 0xf5, 0xe0, // IID181 + 0x62, 0x4c, 0x7c, 0x0c, 0xf5, 0xf6, // IID182 + 0x62, 0xd4, 0x44, 0x10, 0xf7, 0xdb, // IID183 + 0x41, 0xf7, 0xdd, // IID184 + 0x62, 0xd4, 0x7c, 0x14, 0xf7, 0xdb, // IID185 + 0x62, 0xd4, 0x24, 0x1c, 0xf7, 0xdb, // IID186 + 0x62, 0x64, 0x7c, 0x08, 0x88, 0xd1, // IID187 #endif // _LP64 - 0x62, 0xf4, 0x7c, 0x1c, 0x81, 0xeb, 0x00, 0x00, 0x00, 0x01, // IID299 + 0x62, 0xf4, 0x7c, 0x08, 0x88, 0xdb, // IID188 #ifdef _LP64 - 0x62, 0xfc, 0x64, 0x10, 0x81, 0xf7, 0x00, 0x00, 0x01, 0x00, // IID300 - 0x62, 0xfc, 0x7c, 0x18, 0x81, 0xf1, 0x00, 0x00, 0x01, 0x00, // IID301 - 0x62, 0xfc, 0x14, 0x14, 0x81, 0xf2, 0x00, 0x00, 0x10, 0x00, // IID302 - 0x62, 0xd4, 0x7c, 0x1c, 0x81, 0xf6, 0x00, 0x00, 0x10, 0x00, // IID303 - 0x62, 0xd4, 0x64, 0x10, 0x81, 0xef, 0x00, 0x00, 0x00, 0x01, // IID304 - 0x62, 0xdc, 0x7c, 0x18, 0x81, 0xeb, 0x00, 0x00, 0x00, 0x01, // IID305 - 0x62, 0xdc, 0x44, 0x14, 0x81, 0xeb, 0x00, 0x00, 0x00, 0x40, // IID306 - 0x62, 0xfc, 0x7c, 0x1c, 0x81, 0xef, 0x00, 0x00, 0x00, 0x40, // IID307 - 0x62, 0x1c, 0x38, 0x18, 0x03, 0xa4, 0xc4, 0x98, 0x81, 0x92, 0x92, // IID308 - 0x62, 0x1c, 0x38, 0x14, 0x03, 0xac, 0xc8, 0xfd, 0x73, 0x46, 0x78, // IID309 - 0x62, 0x84, 0x3c, 0x10, 0x23, 0xac, 0xa8, 0x77, 0xc7, 0x99, 0x9c, // IID310 - 0x62, 0x4c, 0x1c, 0x1c, 0x23, 0x86, 0xaa, 0x9a, 0xad, 0x98, // IID311 - 0x62, 0x34, 0x10, 0x18, 0xaf, 0xac, 0x8b, 0x27, 0xb2, 0xc6, 0xa0, // IID312 - 0x62, 0x4c, 0x2c, 0x14, 0xaf, 0x8c, 0xd1, 0x66, 0x08, 0xc6, 0xd1, // IID313 - 0x62, 0x34, 0x18, 0x10, 0x0b, 0x84, 0xc2, 0xac, 0x65, 0x26, 0xf1, // IID314 - 0x62, 0xcc, 0x00, 0x14, 0x0b, 0xb4, 0xe6, 0xbd, 0x1c, 0xc4, 0x3a, // IID315 - 0x62, 0x44, 0x38, 0x10, 0x2b, 0xb4, 0x4d, 0xe3, 0xc2, 0xfd, 0x1e, // IID316 - 0x62, 0x84, 0x7c, 0x14, 0x2b, 0x84, 0x79, 0x34, 0xeb, 0x9f, 0x76, // IID317 - 0x62, 0x44, 0x64, 0x10, 0x33, 0x8a, 0x29, 0xb4, 0x39, 0x22, // IID318 - 0x62, 0xac, 0x30, 0x14, 0x33, 0x9c, 0x40, 0xea, 0xfa, 0x71, 0x1c, // IID319 - 0x62, 0x5c, 0x64, 0x10, 0x32, 0x94, 0x24, 0x03, 0xf3, 0x65, 0xd6, // IID320 - 0x62, 0x2c, 0x60, 0x1c, 0x32, 0xa4, 0x47, 0x27, 0x22, 0x87, 0xa2, // IID321 - 0x62, 0x14, 0x29, 0x18, 0x33, 0x8c, 0xb5, 0x88, 0x11, 0x15, 0x11, // IID322 - 0x62, 0xa4, 0x79, 0x14, 0x33, 0x8c, 0x3a, 0xe7, 0x6c, 0x93, 0x61, // IID323 - 0x62, 0xdc, 0x14, 0x18, 0x03, 0xdc, // IID324 - 0x62, 0x6c, 0x64, 0x1c, 0x03, 0xee, // IID325 - 0x62, 0x54, 0x64, 0x18, 0x23, 0xc0, // IID326 - 0x62, 0xc4, 0x24, 0x1c, 0x23, 0xc5, // IID327 - 0x62, 0x7c, 0x1c, 0x18, 0xaf, 0xf9, // IID328 - 0x62, 0x6c, 0x44, 0x14, 0xaf, 0xfc, // IID329 - 0x62, 0x44, 0x4d, 0x10, 0x0b, 0xd2, // IID330 - 0x62, 0xc4, 0x35, 0x14, 0x0b, 0xdb, // IID331 - 0x62, 0x44, 0x64, 0x10, 0x0b, 0xf0, // IID332 - 0x62, 0x74, 0x1c, 0x1c, 0x0b, 0xd2, // IID333 - 0x62, 0x6c, 0x4c, 0x10, 0xa5, 0xf4, // IID334 - 0x62, 0xec, 0x6c, 0x14, 0xa5, 0xd3, // IID335 - 0x62, 0xfc, 0x34, 0x10, 0xad, 0xca, // IID336 - 0x62, 0x6c, 0x64, 0x14, 0xad, 0xc8, // IID337 - 0x62, 0x4c, 0x24, 0x18, 0x2b, 0xf8, // IID338 - 0x62, 0x6c, 0x0c, 0x1c, 0x2b, 0xf0, // IID339 - 0x62, 0x5c, 0x34, 0x18, 0x33, 0xda, // IID340 - 0x62, 0xdc, 0x24, 0x14, 0x33, 0xd7, // IID341 - 0x62, 0xd4, 0x14, 0x10, 0x24, 0xca, 0x10, // IID342 - 0x62, 0xec, 0x04, 0x1c, 0x24, 0xcf, 0x10, // IID343 - 0x62, 0x54, 0x24, 0x10, 0x2c, 0xfd, 0x08, // IID344 - 0x62, 0x4c, 0x04, 0x1c, 0x2c, 0xd5, 0x10, // IID345 - 0x62, 0x54, 0x6c, 0x10, 0x40, 0xc9, // IID346 - 0x62, 0x6c, 0x4c, 0x10, 0x41, 0xf7, // IID347 - 0x62, 0xc4, 0x24, 0x18, 0x42, 0xe3, // IID348 - 0x62, 0x6c, 0x64, 0x18, 0x43, 0xe0, // IID349 - 0x62, 0xcc, 0x5c, 0x10, 0x44, 0xc8, // IID350 - 0x62, 0xc4, 0x4c, 0x10, 0x45, 0xc7, // IID351 - 0x62, 0x4c, 0x04, 0x18, 0x46, 0xe5, // IID352 - 0x62, 0x4c, 0x7c, 0x10, 0x47, 0xc9, // IID353 - 0x62, 0x7c, 0x74, 0x10, 0x48, 0xe9, // IID354 - 0x62, 0xdc, 0x44, 0x10, 0x49, 0xde, // IID355 - 0x62, 0xc4, 0x04, 0x18, 0x4a, 0xf3, // IID356 - 0x62, 0xfc, 0x24, 0x10, 0x4b, 0xd6, // IID357 - 0x62, 0xcc, 0x34, 0x18, 0x4c, 0xcc, // IID358 - 0x62, 0x5c, 0x3c, 0x10, 0x4d, 0xda, // IID359 - 0x62, 0xf4, 0x1c, 0x18, 0x4e, 0xcb, // IID360 - 0x62, 0xec, 0x1c, 0x10, 0x4f, 0xf6, // IID361 - 0x62, 0x74, 0x28, 0x18, 0x40, 0xb4, 0xc9, 0xc3, 0x4d, 0xa8, 0x87, // IID362 - 0x62, 0x1c, 0x70, 0x10, 0x41, 0xa4, 0xc2, 0x23, 0x22, 0x64, 0x10, // IID363 - 0x62, 0x5c, 0x2c, 0x10, 0x42, 0x87, 0x1c, 0xd4, 0xd2, 0xf4, // IID364 - 0x62, 0xc4, 0x18, 0x18, 0x43, 0xa4, 0xb4, 0xd5, 0x08, 0x80, 0x99, // IID365 - 0x62, 0x5c, 0x48, 0x10, 0x44, 0x8c, 0xbb, 0x22, 0x4d, 0xce, 0x66, // IID366 - 0x62, 0x1c, 0x18, 0x18, 0x45, 0x84, 0xde, 0x1f, 0x89, 0x69, 0xd4, // IID367 - 0x62, 0x84, 0x70, 0x10, 0x46, 0xa4, 0xf1, 0x21, 0xdd, 0xef, 0xca, // IID368 - 0x62, 0x54, 0x6c, 0x18, 0x47, 0x86, 0x59, 0x7a, 0x6b, 0x3d, // IID369 - 0x62, 0x04, 0x74, 0x18, 0x48, 0xbc, 0xb3, 0xf2, 0x85, 0xd5, 0x2c, // IID370 - 0x62, 0x8c, 0x34, 0x10, 0x49, 0x94, 0x98, 0xcc, 0x63, 0x96, 0xc0, // IID371 - 0x62, 0x7c, 0x68, 0x10, 0x4a, 0x84, 0x8b, 0x3b, 0x5b, 0xf2, 0xc6, // IID372 - 0x62, 0x4c, 0x24, 0x18, 0x4b, 0xac, 0x95, 0x3f, 0xa9, 0x94, 0x3a, // IID373 - 0x62, 0x44, 0x10, 0x18, 0x4c, 0xac, 0x7f, 0x32, 0x35, 0xd4, 0x76, // IID374 - 0x62, 0x14, 0x04, 0x18, 0x4d, 0xa4, 0x4d, 0x5b, 0x7a, 0x6f, 0x01, // IID375 - 0x62, 0xfc, 0x30, 0x18, 0x4e, 0x94, 0x79, 0xe1, 0xbf, 0xb6, 0x43, // IID376 - 0x62, 0x8c, 0x1c, 0x10, 0x4f, 0xa4, 0x10, 0xd1, 0x7f, 0x91, 0xcd, // IID377 - 0xd5, 0x4c, 0x13, 0xd9, // IID378 - 0xd5, 0x49, 0x3b, 0xf7, // IID379 - 0xd5, 0xdd, 0xaf, 0xfe, // IID380 - 0xf3, 0xd5, 0xd8, 0xb8, 0xdb, // IID381 - 0xd5, 0x5c, 0x1b, 0xd5, // IID382 - 0xd5, 0x1d, 0x2b, 0xf2, // IID383 - 0xf3, 0xd5, 0xc9, 0xbc, 0xe7, // IID384 - 0xf3, 0x4d, 0x0f, 0xbd, 0xe5, // IID385 - 0xd5, 0x59, 0x03, 0xfc, // IID386 - 0xd5, 0x58, 0x23, 0xe4, // IID387 - 0xd5, 0x4d, 0x0b, 0xc3, // IID388 - 0x4d, 0x33, 0xd7, // IID389 - 0xd5, 0x58, 0x8b, 0xdc, // IID390 - 0xd5, 0xc9, 0xbc, 0xff, // IID391 - 0xd5, 0xdc, 0xbd, 0xd3, // IID392 - 0xd5, 0xd9, 0xa3, 0xf8, // IID393 - 0xd5, 0x4d, 0x87, 0xe3, // IID394 - 0x4d, 0x85, 0xed, // IID395 - 0xd5, 0x39, 0x01, 0x94, 0xff, 0x37, 0x04, 0xda, 0x59, // IID396 - 0xd5, 0x7c, 0x21, 0x9c, 0xe5, 0x57, 0xd5, 0xd0, 0x6f, // IID397 - 0xd5, 0x1c, 0x39, 0x9d, 0x44, 0x67, 0xef, 0x23, // IID398 - 0x49, 0x09, 0x8c, 0xca, 0xab, 0x44, 0x85, 0x7e, // IID399 - 0xd5, 0x2a, 0x31, 0x9c, 0xc1, 0x77, 0xb7, 0x35, 0x86, // IID400 - 0xd5, 0x7f, 0x29, 0x9c, 0x3b, 0x9a, 0x5f, 0xf8, 0x11, // IID401 - 0xd5, 0x78, 0x89, 0x8c, 0xc4, 0xda, 0x8d, 0x15, 0x72, // IID402 - 0xd5, 0x9f, 0xc1, 0xa4, 0x8d, 0xd1, 0xeb, 0x8f, 0x6e, // IID403 - 0x49, 0x81, 0xa7, 0x33, 0xb1, 0x36, 0xb8, 0x00, 0x00, 0x00, 0x10, // IID404 - 0xd5, 0x38, 0x81, 0x84, 0x5f, 0x3f, 0xde, 0xbf, 0x32, 0x00, 0x01, 0x00, 0x00, // IID405 - 0x4b, 0x81, 0xbc, 0xdf, 0x60, 0x75, 0x8e, 0x54, 0x00, 0x10, 0x00, 0x00, // IID406 - 0xd5, 0x1a, 0xc1, 0xbc, 0x74, 0x34, 0xfc, 0x43, 0x1b, 0x02, // IID407 - 0xd5, 0x39, 0xc1, 0xa4, 0x2a, 0x3d, 0xaf, 0x51, 0xc4, 0x08, // IID408 - 0xd5, 0x1a, 0x81, 0x9c, 0xd6, 0x03, 0x14, 0x7e, 0x04, 0x00, 0x00, 0x01, 0x00, // IID409 - 0x48, 0xc1, 0xac, 0x91, 0x4d, 0x92, 0xa3, 0x7e, 0x10, // IID410 - 0xd5, 0x2a, 0x83, 0xac, 0xd1, 0xc2, 0x5a, 0x91, 0xca, 0x10, // IID411 - 0xd5, 0x3b, 0x83, 0xb4, 0x96, 0x5c, 0x2f, 0xa1, 0x78, 0x10, // IID412 - 0x4b, 0x81, 0x8c, 0x53, 0xb5, 0xb5, 0x13, 0x37, 0x00, 0x00, 0x00, 0x10, // IID413 - 0xd5, 0x3b, 0xc7, 0x84, 0xf6, 0x10, 0x1a, 0x54, 0x02, 0x00, 0x00, 0x01, 0x00, // IID414 - 0xd5, 0x1a, 0xf7, 0x84, 0xf8, 0x51, 0x32, 0x8e, 0x55, 0xf0, 0xff, 0xff, 0xff, // IID415 - 0xd5, 0x4f, 0x03, 0x9c, 0x90, 0x2d, 0x73, 0x5f, 0x63, // IID416 - 0xd5, 0x6b, 0x23, 0xac, 0x3c, 0x60, 0x3b, 0x17, 0x8a, // IID417 - 0xd5, 0x78, 0x3b, 0x94, 0x83, 0xe2, 0x17, 0xf5, 0xed, // IID418 - 0xf3, 0xd5, 0xbb, 0xbd, 0x9c, 0x37, 0x5d, 0x26, 0xc3, 0x1e, // IID419 - 0xd5, 0x6a, 0x0b, 0x84, 0x12, 0x1b, 0x83, 0x86, 0x35, // IID420 - 0xd5, 0x1c, 0x13, 0xa2, 0x86, 0x60, 0xc1, 0xc3, // IID421 - 0xd5, 0xa9, 0xaf, 0x8c, 0xe8, 0xab, 0x15, 0x15, 0x6b, // IID422 - 0xf3, 0xd5, 0xec, 0xb8, 0xac, 0xb9, 0x4d, 0x6c, 0xf0, 0x4f, // IID423 - 0xd5, 0x5f, 0x1b, 0x94, 0x50, 0x77, 0x5e, 0x26, 0x8a, // IID424 - 0xd5, 0x48, 0x2b, 0x8c, 0x1b, 0x9c, 0xd5, 0x33, 0x40, // IID425 - 0xf3, 0xd5, 0xda, 0xbc, 0x94, 0xe6, 0x83, 0xcb, 0x6c, 0xc7, // IID426 - 0xd5, 0x3c, 0x33, 0xa4, 0xfc, 0x60, 0x15, 0x31, 0x4b, // IID427 - 0xd5, 0x6f, 0x8b, 0xac, 0xa2, 0x57, 0x26, 0x3a, 0x5c, // IID428 - 0xd5, 0x6b, 0x8d, 0xb4, 0xcd, 0x3f, 0x6f, 0x3d, 0x1a, // IID429 - 0xf2, 0xd5, 0xfe, 0x2c, 0x8c, 0xc1, 0x28, 0x24, 0x52, 0xca, // IID430 - 0xd5, 0x59, 0x87, 0x91, 0xc3, 0x84, 0x21, 0x63, // IID431 - 0xd5, 0x5e, 0x85, 0xac, 0x6a, 0x76, 0x02, 0xc6, 0xaf, // IID432 - 0xd5, 0x18, 0x81, 0xc4, 0x00, 0x10, 0x00, 0x00, // IID433 - 0x49, 0x83, 0xe1, 0x10, // IID434 - 0x48, 0x81, 0xd2, 0x00, 0x01, 0x00, 0x00, // IID435 - 0xd5, 0x18, 0x81, 0xfe, 0x00, 0x00, 0x00, 0x01, // IID436 - 0xd5, 0x18, 0xd1, 0xd1, // IID437 - 0xd5, 0x19, 0xd1, 0xdf, // IID438 - 0xd5, 0x19, 0xc1, 0xc3, 0x04, // IID439 - 0xd5, 0x19, 0xc1, 0xcc, 0x02, // IID440 - 0x48, 0xc1, 0xf9, 0x10, // IID441 - 0xd5, 0x19, 0xc1, 0xe7, 0x08, // IID442 - 0xd5, 0x19, 0x81, 0xdb, 0x00, 0x00, 0x10, 0x00, // IID443 - 0xd5, 0x18, 0xc1, 0xe4, 0x10, // IID444 - 0xd5, 0x19, 0xc1, 0xef, 0x08, // IID445 - 0xd5, 0x19, 0x81, 0xeb, 0x00, 0x00, 0x10, 0x00, // IID446 - 0xd5, 0x18, 0x81, 0xf6, 0x00, 0x10, 0x00, 0x00, // IID447 - 0x49, 0xc7, 0xc0, 0x00, 0x10, 0x00, 0x00, // IID448 - 0xd5, 0x19, 0xbc, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, // IID449 - 0x49, 0x0f, 0xba, 0xe5, 0x01, // IID450 - 0xd5, 0x18, 0xf7, 0xc0, 0x00, 0x00, 0xf0, 0xff, // IID451 - 0xd5, 0x18, 0x81, 0xcc, 0x00, 0x00, 0x04, 0x00, // IID452 - 0xd5, 0x18, 0x81, 0xea, 0x00, 0x00, 0x10, 0x00, // IID453 - 0xd5, 0x9b, 0x40, 0x9c, 0x05, 0x15, 0x26, 0x02, 0x1d, // IID454 - 0xd5, 0xab, 0x41, 0x94, 0x64, 0x1e, 0x67, 0x37, 0xcb, // IID455 - 0xd5, 0xcd, 0x42, 0x9c, 0xca, 0x0f, 0x54, 0x08, 0xe1, // IID456 - 0xd5, 0xaf, 0x43, 0xb4, 0xad, 0x97, 0x7c, 0xb3, 0x83, // IID457 - 0xd5, 0x9c, 0x44, 0xbc, 0x8f, 0x31, 0xd3, 0x2d, 0x94, // IID458 - 0xd5, 0xcf, 0x45, 0x84, 0x57, 0xf7, 0xc2, 0x04, 0x80, // IID459 - 0xd5, 0xc9, 0x46, 0xbb, 0x3b, 0x86, 0x6a, 0x27, // IID460 - 0xd5, 0xdd, 0x47, 0xa5, 0x6e, 0x39, 0xb4, 0x3f, // IID461 - 0xd5, 0xdd, 0x48, 0x94, 0xcb, 0x1c, 0xa6, 0xde, 0x4d, // IID462 - 0xd5, 0xbc, 0x49, 0x94, 0x5e, 0x66, 0x69, 0x12, 0x2a, // IID463 - 0x4d, 0x0f, 0x4a, 0xa2, 0x9f, 0xc5, 0xd7, 0x03, // IID464 - 0x4f, 0x0f, 0x4b, 0x94, 0xc0, 0xd3, 0x79, 0x9e, 0xf1, // IID465 - 0xd5, 0xd9, 0x4c, 0xbd, 0x93, 0x26, 0x81, 0x88, // IID466 - 0xd5, 0xa8, 0x4d, 0x8c, 0x5b, 0xcb, 0x01, 0xc6, 0x53, // IID467 - 0xd5, 0x9c, 0x4e, 0xb4, 0x19, 0x8d, 0x0f, 0x74, 0x89, // IID468 - 0xd5, 0xed, 0x4f, 0xac, 0x5a, 0x3c, 0x8d, 0xc9, 0x30, // IID469 - 0x41, 0xff, 0xd2, // IID470 - 0xd5, 0x18, 0xf7, 0xf0, // IID471 - 0xd5, 0x19, 0xf7, 0xfb, // IID472 - 0x49, 0xf7, 0xe9, // IID473 - 0x49, 0xf7, 0xe5, // IID474 - 0x49, 0xf7, 0xde, // IID475 - 0xd5, 0x18, 0xf7, 0xd2, // IID476 - 0xd5, 0x19, 0xd3, 0xc4, // IID477 - 0xd5, 0x19, 0xd3, 0xcc, // IID478 - 0xd5, 0x18, 0xd3, 0xfe, // IID479 - 0x49, 0xd3, 0xe0, // IID480 - 0x49, 0xd3, 0xe4, // IID481 - 0x48, 0xd3, 0xeb, // IID482 - 0x48, 0xff, 0xc1, // IID483 - 0xd5, 0x18, 0xff, 0xcf, // IID484 - 0xd5, 0x08, 0x51, // IID485 - 0xd5, 0x19, 0x5a, // IID486 - 0xd5, 0x13, 0xff, 0x94, 0x15, 0x9f, 0xbc, 0x55, 0x56, // IID487 - 0xd5, 0x28, 0xf7, 0xa4, 0xea, 0xd0, 0x59, 0x67, 0x98, // IID488 - 0xd5, 0x3b, 0xf7, 0x9c, 0x07, 0xfe, 0xe7, 0xf8, 0xdf, // IID489 - 0xd5, 0x18, 0xd3, 0xbc, 0x95, 0x1b, 0x46, 0xc3, 0xcb, // IID490 - 0xd5, 0x3a, 0xd3, 0xa4, 0xc4, 0x74, 0x75, 0x66, 0x0a, // IID491 - 0xd5, 0x19, 0xd3, 0xab, 0x74, 0x79, 0xb7, 0x76, // IID492 - 0xd5, 0x19, 0xff, 0x81, 0xcf, 0x72, 0xb1, 0xac, // IID493 - 0xd5, 0x18, 0xff, 0x8c, 0x24, 0x5f, 0xc1, 0xf2, 0xe7, // IID494 - 0xd5, 0x58, 0x69, 0x88, 0xa8, 0x02, 0x0d, 0xd5, 0x00, 0x10, 0x00, 0x00, // IID495 - 0xd5, 0x5d, 0x6b, 0xe1, 0x10, // IID496 - 0xd5, 0x9d, 0xa4, 0xeb, 0x10, // IID497 - 0x4d, 0x0f, 0xac, 0xd0, 0x10, // IID498 - 0x62, 0xd4, 0x3c, 0x18, 0x8f, 0xc6, // IID499 - 0x62, 0xfc, 0xe4, 0x18, 0x8f, 0xc2, // IID500 - 0x62, 0xfc, 0x64, 0x10, 0xff, 0xf7, // IID501 - 0x62, 0xd4, 0xe4, 0x18, 0xff, 0xf4, // IID502 - 0xd5, 0xad, 0xb6, 0x8c, 0xfe, 0xba, 0xd9, 0x72, 0xbd, // IID503 - 0xd5, 0xcd, 0xb7, 0xa4, 0x89, 0x9f, 0xe9, 0x9e, 0x8d, // IID504 - 0xd5, 0xb9, 0xbe, 0x9c, 0xa8, 0x90, 0xe9, 0x6b, 0x3a, // IID505 - 0xd5, 0xda, 0xbf, 0x84, 0x16, 0xdd, 0x8b, 0xef, 0x07, // IID506 - 0xd5, 0xcd, 0xb6, 0xe6, // IID507 - 0xd5, 0x9d, 0xb7, 0xec, // IID508 - 0x4c, 0x0f, 0xbe, 0xda, // IID509 - 0xd5, 0x9d, 0xbf, 0xe2, // IID510 - 0xd5, 0xc9, 0xb1, 0xa2, 0x26, 0x57, 0x2d, 0xf4, // IID511 - 0x62, 0xd4, 0xfc, 0x08, 0xf7, 0xff, // IID512 - 0x62, 0xfc, 0xfc, 0x0c, 0xf7, 0xff, // IID513 - 0x62, 0xd4, 0xfc, 0x08, 0xf7, 0xf6, // IID514 - 0x62, 0xd4, 0xfc, 0x0c, 0xf7, 0xf6, // IID515 - 0x62, 0xd4, 0xfc, 0x08, 0xf7, 0xef, // IID516 - 0x62, 0xfc, 0xfc, 0x0c, 0xf7, 0xec, // IID517 - 0x62, 0xf4, 0xfc, 0x08, 0xf7, 0xe1, // IID518 - 0x62, 0xfc, 0xfc, 0x0c, 0xf7, 0xe5, // IID519 - 0x62, 0xbc, 0xfc, 0x08, 0xf7, 0xa4, 0xd0, 0x1e, 0xac, 0x66, 0x5f, // IID520 - 0x62, 0xfc, 0xf8, 0x0c, 0xf7, 0xa4, 0xf5, 0x83, 0x7f, 0x43, 0xf4, // IID521 - 0x62, 0xcc, 0xfc, 0x08, 0xaf, 0xf2, // IID522 - 0x62, 0x6c, 0xfc, 0x0c, 0xaf, 0xcd, // IID523 - 0x62, 0xc4, 0xfc, 0x08, 0xf5, 0xe5, // IID524 - 0x62, 0x6c, 0xfc, 0x0c, 0xf5, 0xcb, // IID525 - 0x62, 0xdc, 0xd4, 0x10, 0xf7, 0xde, // IID526 - 0x62, 0xd4, 0x94, 0x14, 0xf7, 0xdb, // IID527 - 0x62, 0xd4, 0xcc, 0x10, 0xf7, 0xd0, // IID528 - 0x62, 0x7c, 0xfc, 0x08, 0x88, 0xe3, // IID529 - 0x62, 0x6c, 0xfc, 0x0c, 0x88, 0xef, // IID530 - 0x62, 0xdc, 0x9c, 0x10, 0xd3, 0xc0, // IID531 - 0x62, 0xfc, 0xec, 0x1c, 0xd3, 0xc4, // IID532 - 0x62, 0xdc, 0xe4, 0x18, 0xd3, 0xce, // IID533 - 0x62, 0xd4, 0xac, 0x1c, 0xd3, 0xcf, // IID534 - 0x62, 0xd4, 0xf4, 0x10, 0xd3, 0xe5, // IID535 - 0x62, 0xdc, 0xd4, 0x14, 0xd3, 0xe0, // IID536 - 0x62, 0xd4, 0x84, 0x10, 0xd3, 0xfc, // IID537 - 0x62, 0xdc, 0xec, 0x1c, 0xd3, 0xf8, // IID538 - 0x62, 0xdc, 0xd4, 0x10, 0xff, 0xc8, // IID539 - 0x62, 0xdc, 0x84, 0x1c, 0xff, 0xcf, // IID540 - 0x62, 0xf4, 0xac, 0x18, 0xff, 0xc3, // IID541 - 0x62, 0xd4, 0xec, 0x14, 0xff, 0xc0, // IID542 - 0x62, 0xdc, 0xac, 0x18, 0xd3, 0xe2, // IID543 - 0x62, 0xd4, 0x9c, 0x14, 0xd3, 0xe6, // IID544 - 0x62, 0xfc, 0xac, 0x18, 0xd3, 0xeb, // IID545 - 0x62, 0xfc, 0x9c, 0x14, 0xd3, 0xed, // IID546 - 0x62, 0xec, 0xfc, 0x08, 0xf4, 0xee, // IID547 - 0x62, 0xec, 0xfc, 0x0c, 0xf4, 0xc7, // IID548 - 0x62, 0x3c, 0xfc, 0x08, 0xaf, 0x9c, 0x8a, 0x5f, 0x7a, 0xdd, 0xec, // IID549 - 0x62, 0x1c, 0xfc, 0x0c, 0xaf, 0xac, 0xf8, 0xa0, 0x0c, 0xf5, 0x48, // IID550 - 0x62, 0x54, 0xfc, 0x08, 0xf5, 0x8d, 0x0e, 0xcf, 0x15, 0x21, // IID551 - 0x62, 0x4c, 0xfc, 0x0c, 0xf5, 0x9e, 0xbb, 0xab, 0x9c, 0x04, // IID552 - 0x62, 0x94, 0xd0, 0x10, 0xf7, 0x9c, 0xbd, 0xd2, 0xf4, 0xa8, 0x50, // IID553 - 0x62, 0xfc, 0xc8, 0x14, 0xf7, 0x9c, 0x62, 0xb4, 0xa7, 0x5f, 0xa2, // IID554 - 0x62, 0x74, 0xf8, 0x08, 0x88, 0xb4, 0xb3, 0x2f, 0xb6, 0x9c, 0x9f, // IID555 - 0x62, 0x6c, 0xf8, 0x0c, 0x88, 0x94, 0xf7, 0xdd, 0x93, 0x39, 0x8d, // IID556 - 0x62, 0xd4, 0xac, 0x10, 0xd3, 0xa1, 0x09, 0xba, 0x4a, 0x33, // IID557 - 0x62, 0x94, 0xb0, 0x1c, 0xd3, 0xa4, 0xf1, 0xfe, 0x9e, 0x65, 0xde, // IID558 - 0x62, 0xfc, 0xb4, 0x10, 0xd3, 0xbc, 0x24, 0x4f, 0x45, 0xce, 0xde, // IID559 - 0x62, 0xdc, 0xf8, 0x14, 0xd3, 0xbc, 0x44, 0xb9, 0x83, 0xc4, 0x48, // IID560 - 0x62, 0xd4, 0x88, 0x10, 0xff, 0x8c, 0x01, 0xb1, 0x17, 0x73, 0xf7, // IID561 - 0x62, 0x9c, 0xa0, 0x1c, 0xff, 0x8c, 0xae, 0xd0, 0x8f, 0xeb, 0x3e, // IID562 - 0x62, 0x9c, 0xac, 0x10, 0xff, 0x84, 0xd5, 0x2e, 0x82, 0xf4, 0x3e, // IID563 - 0x62, 0xfc, 0x90, 0x14, 0xff, 0x84, 0xa3, 0x47, 0xc2, 0xf0, 0xc0, // IID564 - 0x62, 0xdc, 0xb8, 0x18, 0xd3, 0xac, 0x26, 0x17, 0x6a, 0xb5, 0x15, // IID565 - 0x62, 0xd4, 0xac, 0x14, 0xd3, 0xab, 0x9f, 0x9a, 0x17, 0xd2, // IID566 - 0x62, 0x34, 0xf8, 0x08, 0xf4, 0x9c, 0x71, 0x3e, 0x4e, 0x00, 0xcd, // IID567 - 0x62, 0x84, 0xfc, 0x0c, 0xf4, 0xbc, 0x61, 0x97, 0xc1, 0x7d, 0xab, // IID568 - 0x62, 0x54, 0xdc, 0x10, 0x01, 0xbc, 0xcd, 0xf3, 0x93, 0xee, 0xb9, // IID569 - 0x62, 0xc4, 0x90, 0x1c, 0x01, 0x84, 0x79, 0xfb, 0x89, 0x93, 0xd7, // IID570 - 0x62, 0x4c, 0xd0, 0x10, 0x21, 0xac, 0x0e, 0xb2, 0x30, 0x4e, 0x0f, // IID571 - 0x62, 0xac, 0x88, 0x14, 0x21, 0x8c, 0x39, 0xc4, 0xde, 0xb9, 0x3a, // IID572 - 0x62, 0x0c, 0xa8, 0x18, 0x09, 0xa4, 0x73, 0x9a, 0xed, 0x80, 0xe6, // IID573 - 0x62, 0x1c, 0xb0, 0x1c, 0x09, 0x9c, 0x35, 0xf8, 0x64, 0x15, 0xdb, // IID574 - 0x62, 0xc4, 0x84, 0x18, 0x29, 0x86, 0x70, 0x40, 0xbb, 0xb0, // IID575 - 0x62, 0x6c, 0xf0, 0x1c, 0x29, 0xa4, 0x55, 0x71, 0x53, 0x2f, 0xee, // IID576 - 0x62, 0x7c, 0xe0, 0x10, 0x31, 0x84, 0x13, 0x14, 0xaa, 0xa1, 0xf5, // IID577 - 0x62, 0xac, 0x98, 0x14, 0x31, 0x84, 0x61, 0x20, 0xd0, 0x4b, 0x91, // IID578 - 0x62, 0xfc, 0xf4, 0x10, 0x81, 0x82, 0xfb, 0xee, 0x54, 0x9f, 0x00, 0x00, 0x00, 0x01, // IID579 - 0x62, 0xbc, 0xb0, 0x14, 0x81, 0x84, 0x0b, 0xd9, 0x44, 0x24, 0x12, 0x00, 0x00, 0x01, 0x00, // IID580 - 0x62, 0x94, 0x88, 0x10, 0x81, 0xa4, 0x61, 0x0d, 0xf3, 0x4f, 0xda, 0x00, 0x10, 0x00, 0x00, // IID581 - 0x62, 0xfc, 0xb4, 0x1c, 0x81, 0xa4, 0x5e, 0xda, 0xaf, 0xb9, 0x81, 0x00, 0x00, 0x00, 0x10, // IID582 - 0x62, 0x1c, 0xf8, 0x08, 0x6b, 0xa4, 0x49, 0x34, 0x97, 0xd2, 0xbc, 0x01, // IID583 - 0x62, 0x3c, 0xf8, 0x0c, 0x6b, 0xbc, 0xf9, 0xa2, 0xa9, 0x68, 0xd4, 0x10, // IID584 - 0x62, 0xb4, 0x98, 0x10, 0x81, 0x8c, 0x3a, 0xb1, 0x63, 0x13, 0x3f, 0x00, 0x01, 0x00, 0x00, // IID585 - 0x62, 0xd4, 0xf8, 0x14, 0x81, 0x8c, 0xfc, 0xc4, 0x79, 0x7a, 0xe8, 0x00, 0x00, 0x00, 0x01, // IID586 - 0x62, 0x94, 0xb8, 0x18, 0xc1, 0xa4, 0x86, 0x5b, 0x6f, 0xbd, 0x8e, 0x02, // IID587 - 0x62, 0x94, 0xbc, 0x1c, 0xc1, 0xa4, 0xb7, 0x43, 0x32, 0xf1, 0x21, 0x10, // IID588 - 0x62, 0x94, 0xa8, 0x18, 0xc1, 0xbc, 0x2d, 0x72, 0xcb, 0x04, 0x7d, 0x02, // IID589 - 0x62, 0xbc, 0xa0, 0x1c, 0xc1, 0xbc, 0xfd, 0x24, 0x4b, 0x89, 0xde, 0x08, // IID590 - 0x62, 0xbc, 0xf4, 0x18, 0xc1, 0xac, 0x60, 0x38, 0x9a, 0x0c, 0x26, 0x04, // IID591 - 0x62, 0x9c, 0xcc, 0x14, 0xc1, 0xac, 0x0a, 0x9e, 0x44, 0xa9, 0xa1, 0x08, // IID592 - 0x62, 0xb4, 0x80, 0x10, 0x83, 0xac, 0x63, 0x10, 0xbb, 0x00, 0x2b, 0x01, // IID593 - 0x62, 0xdc, 0xd4, 0x14, 0x81, 0xaf, 0x53, 0x0b, 0xef, 0x93, 0x00, 0x10, 0x00, 0x00, // IID594 - 0x62, 0xbc, 0xa0, 0x18, 0x81, 0xb4, 0x77, 0x6b, 0x02, 0xa6, 0x51, 0x00, 0x00, 0x01, 0x00, // IID595 - 0x62, 0x9c, 0x8c, 0x1c, 0x83, 0xb4, 0x93, 0x55, 0x64, 0x52, 0xcb, 0x10, // IID596 - 0x62, 0xfc, 0xdc, 0x10, 0x81, 0xc7, 0x00, 0x00, 0x00, 0x01, // IID597 - 0x62, 0xdc, 0xfc, 0x18, 0x81, 0xc6, 0x00, 0x00, 0x00, 0x01, // IID598 - 0x62, 0xfc, 0xb4, 0x1c, 0x81, 0xc5, 0x00, 0x10, 0x00, 0x00, // IID599 - 0x62, 0xf4, 0xfc, 0x1c, 0x81, 0xc3, 0x00, 0x10, 0x00, 0x00, // IID600 - 0x62, 0xfc, 0xec, 0x18, 0x81, 0xe5, 0x00, 0x00, 0x00, 0x10, // IID601 - 0x62, 0xd4, 0xfc, 0x18, 0x81, 0xe0, 0x00, 0x00, 0x00, 0x10, // IID602 - 0x62, 0xdc, 0xe4, 0x14, 0x81, 0xe7, 0x00, 0x00, 0x01, 0x00, // IID603 - 0x62, 0xf4, 0xfc, 0x1c, 0x81, 0xe3, 0x00, 0x00, 0x01, 0x00, // IID604 - 0x62, 0xc4, 0xfc, 0x08, 0x69, 0xe9, 0x00, 0x00, 0x00, 0x01, // IID605 - 0x62, 0xdc, 0xfc, 0x08, 0x69, 0xc6, 0x00, 0x00, 0x00, 0x01, // IID606 - 0x62, 0x6c, 0xfc, 0x0c, 0x69, 0xf2, 0x00, 0x00, 0x01, 0x00, // IID607 - 0x62, 0xfc, 0xfc, 0x0c, 0x69, 0xc3, 0x00, 0x00, 0x01, 0x00, // IID608 - 0x62, 0xfc, 0xdc, 0x10, 0x81, 0xc8, 0x00, 0x00, 0x10, 0x00, // IID609 - 0x62, 0xdc, 0xfc, 0x18, 0x81, 0xcc, 0x00, 0x00, 0x10, 0x00, // IID610 - 0x62, 0xdc, 0xe4, 0x1c, 0x81, 0xc8, 0x00, 0x10, 0x00, 0x00, // IID611 - 0x62, 0xfc, 0xfc, 0x1c, 0x81, 0xce, 0x00, 0x10, 0x00, 0x00, // IID612 - 0x62, 0xdc, 0xdc, 0x10, 0xc1, 0xd6, 0x04, // IID613 - 0x62, 0xfc, 0xfc, 0x18, 0xc1, 0xd6, 0x04, // IID614 - 0x62, 0xdc, 0xf4, 0x18, 0xc1, 0xc4, 0x02, // IID615 - 0x62, 0xfc, 0xfc, 0x18, 0xc1, 0xc5, 0x02, // IID616 - 0x62, 0xd4, 0xac, 0x14, 0xc1, 0xc7, 0x04, // IID617 - 0x62, 0xfc, 0xfc, 0x1c, 0xc1, 0xc3, 0x04, // IID618 - 0x62, 0xfc, 0xbc, 0x10, 0xc1, 0xcb, 0x08, // IID619 - 0x62, 0xdc, 0xfc, 0x18, 0xc1, 0xcc, 0x08, // IID620 - 0x62, 0xfc, 0xb4, 0x14, 0xc1, 0xca, 0x04, // IID621 - 0x62, 0xd4, 0xfc, 0x1c, 0xc1, 0xcd, 0x04, // IID622 - 0x62, 0xfc, 0xa4, 0x10, 0xc1, 0xe1, 0x02, // IID623 - 0x62, 0xf4, 0xfc, 0x18, 0xc1, 0xe2, 0x02, // IID624 - 0x62, 0xdc, 0xe4, 0x1c, 0xc1, 0xe4, 0x10, // IID625 - 0x62, 0xd4, 0xfc, 0x1c, 0xc1, 0xe7, 0x10, // IID626 - 0x62, 0xd4, 0xe4, 0x18, 0xc1, 0xfc, 0x04, // IID627 - 0x62, 0xf4, 0xfc, 0x18, 0xc1, 0xfb, 0x04, // IID628 - 0x62, 0xf4, 0xf4, 0x14, 0xc1, 0xfa, 0x02, // IID629 - 0x62, 0xdc, 0xfc, 0x1c, 0xc1, 0xff, 0x02, // IID630 - 0x62, 0xf4, 0xd4, 0x10, 0xc1, 0xe3, 0x04, // IID631 - 0x62, 0xdc, 0xfc, 0x18, 0xc1, 0xe0, 0x04, // IID632 - 0x62, 0xd4, 0xa4, 0x14, 0xc1, 0xe5, 0x10, // IID633 - 0x62, 0xdc, 0xfc, 0x1c, 0xc1, 0xe1, 0x10, // IID634 - 0x62, 0xfc, 0xf4, 0x18, 0xc1, 0xee, 0x10, // IID635 - 0x62, 0xd4, 0xfc, 0x18, 0xc1, 0xee, 0x10, // IID636 - 0x62, 0xdc, 0xa4, 0x1c, 0xc1, 0xee, 0x04, // IID637 - 0x62, 0xdc, 0xfc, 0x1c, 0xc1, 0xe8, 0x04, // IID638 - 0x62, 0xfc, 0xdc, 0x10, 0x81, 0xeb, 0x00, 0x01, 0x00, 0x00, // IID639 - 0x62, 0xfc, 0xfc, 0x18, 0x81, 0xe9, 0x00, 0x01, 0x00, 0x00, // IID640 - 0x62, 0xdc, 0x84, 0x14, 0x81, 0xee, 0x00, 0x00, 0x01, 0x00, // IID641 - 0x62, 0xfc, 0xfc, 0x1c, 0x81, 0xea, 0x00, 0x00, 0x01, 0x00, // IID642 - 0x62, 0xd4, 0xec, 0x10, 0x81, 0xf3, 0x00, 0x10, 0x00, 0x00, // IID643 - 0x62, 0xd4, 0xfc, 0x18, 0x81, 0xf2, 0x00, 0x10, 0x00, 0x00, // IID644 - 0x62, 0xfc, 0xbc, 0x14, 0x81, 0xf2, 0x00, 0x00, 0x00, 0x10, // IID645 - 0x62, 0xf4, 0xfc, 0x1c, 0x81, 0xf3, 0x00, 0x00, 0x00, 0x10, // IID646 - 0x62, 0xfc, 0xac, 0x10, 0x81, 0xcd, 0x00, 0x00, 0x40, 0x00, // IID647 - 0x62, 0xd4, 0xfc, 0x18, 0x81, 0xc8, 0x00, 0x00, 0x40, 0x00, // IID648 - 0x62, 0xfc, 0xcc, 0x10, 0x81, 0xcd, 0x00, 0x00, 0x04, 0x00, // IID649 - 0x62, 0xdc, 0xfc, 0x18, 0x81, 0xcb, 0x00, 0x00, 0x04, 0x00, // IID650 - 0x62, 0xd4, 0xfc, 0x10, 0x81, 0xe8, 0x00, 0x00, 0x40, 0x00, // IID651 - 0x62, 0xf4, 0xfc, 0x18, 0x81, 0xea, 0x00, 0x00, 0x40, 0x00, // IID652 - 0x62, 0xdc, 0xdc, 0x14, 0x81, 0xef, 0x00, 0x00, 0x10, 0x00, // IID653 - 0x62, 0xfc, 0xfc, 0x1c, 0x81, 0xed, 0x00, 0x00, 0x10, 0x00, // IID654 - 0x62, 0x74, 0xd8, 0x10, 0x03, 0xb4, 0x01, 0xd9, 0x54, 0x66, 0x7c, // IID655 - 0x62, 0xd4, 0x90, 0x14, 0x03, 0x8c, 0x3f, 0x2d, 0xf7, 0xb7, 0x45, // IID656 - 0x62, 0xc4, 0xe0, 0x10, 0x23, 0x8c, 0x75, 0x6a, 0xe6, 0xf3, 0x8a, // IID657 - 0x62, 0x5c, 0x90, 0x1c, 0x23, 0x84, 0x7f, 0x4e, 0x49, 0xee, 0xdd, // IID658 - 0x62, 0x04, 0xa4, 0x18, 0x0b, 0xa4, 0xdd, 0xab, 0x13, 0x00, 0x5c, // IID659 - 0x62, 0xec, 0xec, 0x1c, 0x0b, 0x94, 0x0a, 0x71, 0x7e, 0x55, 0x59, // IID660 - 0x62, 0x7c, 0xa4, 0x10, 0xaf, 0x9e, 0xb7, 0x69, 0xb9, 0xd7, // IID661 - 0x62, 0x5c, 0xac, 0x1c, 0xaf, 0x88, 0x54, 0x1d, 0x69, 0x49, // IID662 - 0x62, 0x7c, 0xbc, 0x10, 0x2b, 0xa3, 0xaa, 0x29, 0xd5, 0x22, // IID663 - 0x62, 0x84, 0xdc, 0x14, 0x2b, 0x94, 0x91, 0xb8, 0x85, 0xb5, 0xd9, // IID664 - 0x62, 0x14, 0xe0, 0x18, 0x33, 0x8c, 0x1e, 0x2f, 0xc0, 0x71, 0x0f, // IID665 - 0x62, 0x14, 0xb4, 0x14, 0x33, 0xbc, 0x62, 0xbd, 0x67, 0x23, 0x73, // IID666 - 0x62, 0x54, 0xa4, 0x18, 0x03, 0xca, // IID667 - 0x62, 0x7c, 0xb4, 0x14, 0x03, 0xe8, // IID668 - 0x62, 0xcc, 0xa5, 0x18, 0x66, 0xe9, // IID669 - 0x62, 0xe4, 0xee, 0x18, 0x66, 0xe3, // IID670 - 0x62, 0xcc, 0xb4, 0x10, 0x23, 0xea, // IID671 - 0x62, 0x6c, 0xc4, 0x14, 0x23, 0xdd, // IID672 - 0x62, 0x54, 0xac, 0x18, 0xaf, 0xd4, // IID673 - 0x62, 0x7c, 0x84, 0x14, 0xaf, 0xe7, // IID674 - 0x62, 0x44, 0xfc, 0x10, 0x0b, 0xee, // IID675 - 0x62, 0x6c, 0xe4, 0x14, 0x0b, 0xc7, // IID676 - 0x62, 0xc4, 0x8c, 0x18, 0x2b, 0xef, // IID677 - 0x62, 0x5c, 0xb4, 0x14, 0x2b, 0xcd, // IID678 - 0x62, 0x5c, 0xec, 0x18, 0x33, 0xd9, // IID679 - 0x62, 0x7c, 0xe4, 0x14, 0x33, 0xd0, // IID680 - 0x62, 0x6c, 0xbc, 0x18, 0x24, 0xff, 0x08, // IID681 - 0x62, 0xe4, 0x84, 0x14, 0x24, 0xc3, 0x02, // IID682 - 0x62, 0x54, 0xbc, 0x10, 0x2c, 0xca, 0x02, // IID683 - 0x62, 0xcc, 0x9c, 0x14, 0x2c, 0xd2, 0x10, // IID684 - 0x62, 0xec, 0xb4, 0x10, 0x40, 0xe0, // IID685 - 0x62, 0xdc, 0xd4, 0x10, 0x41, 0xdc, // IID686 - 0x62, 0xc4, 0xcc, 0x10, 0x42, 0xdd, // IID687 - 0x62, 0xd4, 0x84, 0x18, 0x43, 0xd0, // IID688 - 0x62, 0x54, 0xcc, 0x10, 0x44, 0xf4, // IID689 - 0x62, 0x5c, 0xbc, 0x10, 0x45, 0xf0, // IID690 - 0x62, 0xe4, 0x94, 0x18, 0x46, 0xeb, // IID691 - 0x62, 0x44, 0xe4, 0x18, 0x47, 0xde, // IID692 - 0x62, 0x6c, 0xbc, 0x10, 0x48, 0xd9, // IID693 - 0x62, 0x4c, 0xd4, 0x10, 0x49, 0xdb, // IID694 - 0x62, 0x5c, 0xa4, 0x10, 0x4a, 0xf0, // IID695 - 0x62, 0x6c, 0x9c, 0x10, 0x4b, 0xee, // IID696 - 0x62, 0x5c, 0x84, 0x18, 0x4c, 0xef, // IID697 - 0x62, 0x5c, 0xd4, 0x10, 0x4d, 0xfe, // IID698 - 0x62, 0x54, 0xdc, 0x10, 0x4e, 0xc5, // IID699 - 0x62, 0x4c, 0x84, 0x10, 0x4f, 0xcb, // IID700 - 0x62, 0x14, 0x84, 0x10, 0x40, 0xbc, 0x6e, 0xaa, 0x7a, 0x19, 0xf9, // IID701 - 0x62, 0x0c, 0x9c, 0x18, 0x41, 0xa4, 0xfe, 0x9e, 0x3f, 0xa3, 0x3b, // IID702 - 0x62, 0x04, 0xfc, 0x10, 0x42, 0x8c, 0x0c, 0xcd, 0xc4, 0x1f, 0xd7, // IID703 - 0x62, 0x04, 0xb8, 0x18, 0x43, 0x9c, 0xc8, 0x6b, 0x42, 0xbd, 0xe1, // IID704 - 0x62, 0xcc, 0xf4, 0x18, 0x44, 0xa4, 0x9b, 0x58, 0x3c, 0x82, 0x46, // IID705 - 0x62, 0x7c, 0xe4, 0x18, 0x45, 0xa5, 0x38, 0x47, 0xca, 0xf9, // IID706 - 0x62, 0x9c, 0xc0, 0x10, 0x46, 0x9c, 0xd3, 0xc0, 0xbc, 0x22, 0x09, // IID707 - 0x62, 0x7c, 0xb4, 0x10, 0x47, 0x8f, 0xec, 0x14, 0x2a, 0x0d, // IID708 - 0x62, 0xc4, 0xa4, 0x18, 0x48, 0x9b, 0x63, 0xa5, 0x46, 0xf0, // IID709 - 0x62, 0xcc, 0x90, 0x18, 0x49, 0x94, 0x1c, 0x7e, 0x9b, 0x6b, 0x71, // IID710 - 0x62, 0xa4, 0xd0, 0x10, 0x4a, 0x84, 0x29, 0xe2, 0xbb, 0x0f, 0xa5, // IID711 - 0x62, 0x2c, 0x98, 0x18, 0x4b, 0xbc, 0x14, 0xb1, 0x7f, 0x0b, 0x0e, // IID712 - 0x62, 0x4c, 0x84, 0x18, 0x4c, 0x86, 0x4f, 0x7b, 0x3b, 0x2d, // IID713 - 0x62, 0x54, 0x98, 0x18, 0x4d, 0xbc, 0xae, 0x18, 0x51, 0xdd, 0xed, // IID714 - 0x62, 0x6c, 0xe0, 0x18, 0x4e, 0xbc, 0x27, 0x96, 0xb2, 0x91, 0xf6, // IID715 - 0x62, 0xd4, 0xec, 0x18, 0x4f, 0x94, 0xd2, 0x7c, 0xf1, 0x75, 0x38, // IID716 + 0x62, 0x54, 0x7c, 0x0c, 0x88, 0xd6, // IID189 + 0x62, 0x4c, 0x7c, 0x0c, 0x88, 0xed, // IID190 + 0x62, 0xfc, 0x04, 0x18, 0xf7, 0xd4, // IID191 + 0xd5, 0x10, 0xf7, 0xd1, // IID192 + 0x41, 0xd3, 0xc4, // IID193 +#endif // _LP64 + 0xd3, 0xc3, // IID194 +#ifdef _LP64 + 0x62, 0xdc, 0x44, 0x14, 0xd3, 0xc3, // IID195 + 0x62, 0xdc, 0x14, 0x14, 0xd3, 0xc5, // IID196 + 0x62, 0xdc, 0x5c, 0x10, 0xd3, 0xcc, // IID197 +#endif // _LP64 + 0xd3, 0xca, // IID198 +#ifdef _LP64 + 0x62, 0xdc, 0x3c, 0x1c, 0xd3, 0xcb, // IID199 +#endif // _LP64 + 0x62, 0xf4, 0x64, 0x1c, 0xd3, 0xcb, // IID200 +#ifdef _LP64 + 0x62, 0xd4, 0x04, 0x18, 0xd3, 0xe3, // IID201 + 0xd5, 0x11, 0xd3, 0xe3, // IID202 + 0x62, 0xdc, 0x14, 0x14, 0xd3, 0xe1, // IID203 + 0x62, 0xd4, 0x1c, 0x1c, 0xd3, 0xe4, // IID204 + 0x62, 0xd4, 0x3c, 0x18, 0xd3, 0xfb, // IID205 + 0xd5, 0x10, 0xd3, 0xfa, // IID206 + 0x62, 0xd4, 0x6c, 0x1c, 0xd3, 0xfd, // IID207 + 0x62, 0xfc, 0x44, 0x14, 0xd3, 0xff, // IID208 + 0x62, 0xd4, 0x3c, 0x10, 0xff, 0xcf, // IID209 + 0x41, 0xff, 0xcf, // IID210 + 0x62, 0xdc, 0x2c, 0x14, 0xff, 0xcc, // IID211 +#endif // _LP64 + 0x62, 0xf4, 0x64, 0x1c, 0xff, 0xcb, // IID212 +#ifdef _LP64 + 0x62, 0xd4, 0x34, 0x10, 0xff, 0xc6, // IID213 + 0x41, 0xff, 0xc4, // IID214 + 0x62, 0xfc, 0x74, 0x1c, 0xff, 0xc7, // IID215 + 0x62, 0xdc, 0x14, 0x14, 0xff, 0xc5, // IID216 + 0x62, 0xdc, 0x4c, 0x10, 0xd3, 0xe0, // IID217 + 0x41, 0xd3, 0xe7, // IID218 + 0x62, 0xdc, 0x34, 0x1c, 0xd3, 0xe7, // IID219 + 0x62, 0xdc, 0x1c, 0x14, 0xd3, 0xe4, // IID220 + 0x62, 0xfc, 0x54, 0x10, 0xd3, 0xea, // IID221 + 0xd5, 0x11, 0xd3, 0xe8, // IID222 + 0x62, 0xfc, 0x0c, 0x1c, 0xd3, 0xeb, // IID223 + 0x62, 0xd4, 0x3c, 0x1c, 0xd3, 0xe8, // IID224 + 0x62, 0x44, 0x7c, 0x08, 0xf4, 0xc9, // IID225 + 0x62, 0x4c, 0x7c, 0x08, 0xf4, 0xd2, // IID226 + 0x62, 0x5c, 0x7c, 0x0c, 0xf4, 0xc6, // IID227 + 0x62, 0x4c, 0x7c, 0x0c, 0xf4, 0xd2, // IID228 + 0x62, 0x4c, 0x78, 0x08, 0xf5, 0xac, 0xe1, 0x1e, 0xf0, 0x37, 0xf6, // IID229 + 0x62, 0xcc, 0x78, 0x0c, 0xf5, 0xb4, 0x9b, 0x09, 0x7c, 0xf2, 0x38, // IID230 + 0x62, 0x94, 0x50, 0x10, 0xf7, 0x9c, 0xb6, 0x7b, 0x2c, 0xf9, 0x39, // IID231 + 0x62, 0xbc, 0x2c, 0x14, 0xf7, 0x9c, 0xf7, 0xc3, 0xe4, 0xd1, 0x9f, // IID232 + 0x62, 0x4c, 0x78, 0x08, 0x88, 0x8c, 0x7c, 0xef, 0x20, 0xf1, 0x4f, // IID233 + 0x62, 0x4c, 0x78, 0x0c, 0x88, 0xac, 0xc0, 0xbd, 0x44, 0xde, 0x97, // IID234 + 0x62, 0x94, 0x40, 0x10, 0xd3, 0xa4, 0xbb, 0xbb, 0x24, 0x42, 0x7f, // IID235 + 0x62, 0xbc, 0x18, 0x1c, 0xd3, 0xa4, 0x7f, 0x58, 0x78, 0x70, 0xfd, // IID236 + 0x62, 0xbc, 0x60, 0x10, 0xd3, 0xbc, 0x70, 0xf3, 0x61, 0x47, 0xd8, // IID237 + 0x62, 0xdc, 0x2c, 0x14, 0xd3, 0xb9, 0x48, 0x5d, 0x14, 0x3d, // IID238 + 0x62, 0x9c, 0x10, 0x18, 0xff, 0x8c, 0x43, 0x62, 0x38, 0x5f, 0x62, // IID239 + 0x62, 0xfc, 0x24, 0x1c, 0xff, 0x8e, 0xa6, 0x04, 0x59, 0x76, // IID240 + 0x62, 0xf4, 0x30, 0x10, 0xff, 0x84, 0x4a, 0x91, 0xc8, 0xaf, 0x82, // IID241 + 0x62, 0xd4, 0x4c, 0x14, 0xff, 0x84, 0x24, 0x57, 0xa2, 0xcd, 0xaf, // IID242 + 0x62, 0xd4, 0x10, 0x18, 0xd3, 0xac, 0x25, 0x94, 0x17, 0x0c, 0xf4, // IID243 + 0x62, 0xd4, 0x28, 0x14, 0xd3, 0xac, 0x5e, 0x47, 0x63, 0x3a, 0xdb, // IID244 + 0x62, 0xac, 0x78, 0x08, 0xf4, 0x84, 0x9e, 0xd1, 0x6f, 0x7f, 0x80, // IID245 + 0x62, 0xcc, 0x7c, 0x0c, 0xf4, 0xa4, 0xd7, 0x18, 0x48, 0x25, 0x12, // IID246 + 0x62, 0x94, 0x54, 0x10, 0x81, 0x84, 0xd4, 0x06, 0xcf, 0x17, 0x64, 0x00, 0x00, 0x10, 0x00, // IID247 + 0x62, 0xd4, 0x34, 0x1c, 0x81, 0x85, 0xfd, 0xa5, 0xf1, 0x14, 0x00, 0x10, 0x00, 0x00, // IID248 + 0x62, 0x9c, 0x24, 0x10, 0x83, 0xa4, 0x05, 0x99, 0x87, 0x98, 0x37, 0x01, // IID249 + 0x62, 0xd4, 0x24, 0x14, 0x81, 0xa1, 0x3f, 0xd2, 0x92, 0xbb, 0x00, 0x01, 0x00, 0x00, // IID250 + 0x62, 0xac, 0x78, 0x08, 0x6b, 0x8c, 0x0c, 0xdb, 0xb5, 0x57, 0x49, 0x10, // IID251 + 0x62, 0x0c, 0x78, 0x0c, 0x6b, 0x8c, 0x7d, 0x3e, 0xa5, 0x26, 0x3c, 0x01, // IID252 + 0x62, 0xd4, 0x04, 0x18, 0x81, 0x89, 0xe2, 0xb5, 0x68, 0xda, 0x00, 0x00, 0x00, 0x10, // IID253 + 0x62, 0xbc, 0x24, 0x1c, 0x81, 0x8c, 0xb8, 0x9f, 0x32, 0xa0, 0x66, 0x00, 0x10, 0x00, 0x00, // IID254 + 0x62, 0xb4, 0x70, 0x18, 0x80, 0x8c, 0x19, 0x5e, 0x48, 0xc6, 0x38, 0x01, // IID255 + 0x62, 0x94, 0x34, 0x14, 0x80, 0x8c, 0x10, 0x34, 0x1c, 0x13, 0x79, 0x40, // IID256 + 0x62, 0x94, 0x10, 0x18, 0xc1, 0xa4, 0xb9, 0xa9, 0x8b, 0x71, 0x12, 0x02, // IID257 + 0x62, 0xdc, 0x04, 0x1c, 0xc1, 0xa1, 0x0d, 0xc9, 0xa7, 0xaf, 0x10, // IID258 + 0x62, 0xf4, 0x00, 0x18, 0xd1, 0xbc, 0x19, 0x10, 0x15, 0x5c, 0x0c, // IID259 + 0x62, 0xdc, 0x10, 0x1c, 0xc1, 0xbc, 0xad, 0x64, 0xcf, 0x98, 0x93, 0x08, // IID260 + 0x62, 0xf4, 0x24, 0x18, 0xc1, 0xab, 0xd0, 0x67, 0x9f, 0x74, 0x10, // IID261 + 0x62, 0xd4, 0x0c, 0x1c, 0xc1, 0xae, 0x48, 0xc2, 0x07, 0xaa, 0x04, // IID262 + 0x62, 0xbc, 0x08, 0x10, 0x83, 0xac, 0x15, 0xe1, 0x14, 0x4d, 0x3b, 0x01, // IID263 + 0x62, 0xfc, 0x1c, 0x14, 0x81, 0xaa, 0x5f, 0xb7, 0xdc, 0xba, 0x00, 0x00, 0x00, 0x01, // IID264 + 0x62, 0xd4, 0x68, 0x18, 0x81, 0xb4, 0x82, 0xb9, 0xe2, 0xe1, 0xe9, 0x00, 0x00, 0x00, 0x01, // IID265 + 0x62, 0xdc, 0x68, 0x1c, 0x81, 0xb4, 0x7d, 0xf8, 0xe2, 0x34, 0x1b, 0x00, 0x00, 0x00, 0x01, // IID266 + 0x62, 0x0c, 0x60, 0x10, 0x01, 0xac, 0x3b, 0xd8, 0xe7, 0x3c, 0x1f, // IID267 + 0x62, 0x4c, 0x1c, 0x10, 0x01, 0xa4, 0xc8, 0x3e, 0x12, 0xac, 0x9f, // IID268 + 0x62, 0x2c, 0x70, 0x14, 0x01, 0xac, 0xc2, 0x88, 0xe0, 0x08, 0xe4, // IID269 + 0x62, 0x94, 0x70, 0x1c, 0x01, 0x8c, 0x67, 0x16, 0x82, 0x5b, 0x01, // IID270 + 0x62, 0x64, 0x0c, 0x10, 0x09, 0xa4, 0xd3, 0x4c, 0xbf, 0xca, 0xb9, // IID271 + 0x62, 0x8c, 0x6c, 0x10, 0x09, 0x94, 0xd4, 0x3b, 0xa7, 0x23, 0x35, // IID272 + 0x62, 0x84, 0x34, 0x1c, 0x09, 0xac, 0x7f, 0xaa, 0x22, 0xf4, 0xd5, // IID273 + 0x62, 0xec, 0x7c, 0x14, 0x09, 0x87, 0x01, 0x9b, 0xaf, 0xe9, // IID274 + 0x62, 0x8c, 0x1c, 0x10, 0x08, 0xa4, 0x1e, 0x3a, 0x1e, 0x28, 0x17, // IID275 + 0x62, 0xb4, 0x68, 0x18, 0x08, 0x94, 0xbb, 0xbb, 0xb5, 0x77, 0x24, // IID276 + 0x62, 0x44, 0x7c, 0x14, 0x08, 0x84, 0x4b, 0x51, 0x2e, 0x8a, 0xce, // IID277 + 0x62, 0xd4, 0x60, 0x1c, 0x08, 0x9c, 0xe3, 0x2d, 0x84, 0x29, 0xdd, // IID278 + 0x62, 0x9c, 0x28, 0x10, 0x29, 0x94, 0x73, 0xd2, 0x31, 0x64, 0xc2, // IID279 + 0x62, 0x2c, 0x00, 0x10, 0x29, 0xbc, 0x6e, 0x19, 0x85, 0x21, 0x14, // IID280 + 0x62, 0x54, 0x54, 0x14, 0x29, 0xa9, 0x86, 0xed, 0xaf, 0xef, // IID281 + 0x62, 0x04, 0x04, 0x14, 0x29, 0xbc, 0x01, 0x9f, 0x76, 0x1e, 0xf5, // IID282 + 0x62, 0x7c, 0x04, 0x18, 0x31, 0xa2, 0xe5, 0xbc, 0x2b, 0x5c, // IID283 + 0x62, 0x4c, 0x20, 0x10, 0x31, 0x9c, 0x39, 0xb3, 0x78, 0x60, 0x5c, // IID284 + 0x62, 0x54, 0x6c, 0x14, 0x31, 0xb4, 0xd0, 0x7f, 0xc7, 0x12, 0xf6, // IID285 + 0x62, 0x54, 0x34, 0x1c, 0x31, 0x8f, 0xad, 0xcd, 0x5a, 0x77, // IID286 + 0x62, 0xac, 0x50, 0x10, 0x30, 0xbc, 0x52, 0xd5, 0x1f, 0xe3, 0x2f, // IID287 + 0x62, 0x5c, 0x2c, 0x18, 0x30, 0x93, 0xde, 0x50, 0x31, 0x0a, // IID288 + 0x62, 0x2c, 0x68, 0x14, 0x30, 0x84, 0xf6, 0x97, 0xe8, 0xd4, 0x1a, // IID289 + 0x62, 0x7c, 0x38, 0x1c, 0x30, 0x84, 0x20, 0x82, 0xae, 0x6e, 0x62, // IID290 + 0x62, 0xd4, 0x54, 0x10, 0x81, 0xc7, 0x00, 0x00, 0x10, 0x00, // IID291 + 0x62, 0xfc, 0x7c, 0x18, 0x81, 0xc2, 0x00, 0x00, 0x10, 0x00, // IID292 + 0xd5, 0x10, 0x81, 0xc2, 0x00, 0x01, 0x00, 0x00, // IID293 + 0x62, 0xfc, 0x14, 0x1c, 0x83, 0xc3, 0x10, // IID294 + 0x62, 0xfc, 0x7c, 0x1c, 0x83, 0xc7, 0x10, // IID295 + 0x62, 0xdc, 0x34, 0x14, 0x81, 0xc1, 0x00, 0x00, 0x00, 0x01, // IID296 + 0x62, 0xfc, 0x14, 0x10, 0x81, 0xe2, 0x00, 0x00, 0x10, 0x00, // IID297 + 0x62, 0xd4, 0x7c, 0x18, 0x81, 0xe6, 0x00, 0x00, 0x10, 0x00, // IID298 + 0xd5, 0x10, 0x81, 0xe3, 0x00, 0x00, 0x01, 0x00, // IID299 + 0x62, 0xdc, 0x24, 0x14, 0x81, 0xe1, 0x00, 0x00, 0x10, 0x00, // IID300 + 0x62, 0xfc, 0x7c, 0x1c, 0x81, 0xe4, 0x00, 0x00, 0x10, 0x00, // IID301 + 0x62, 0xdc, 0x1c, 0x14, 0x83, 0xe4, 0x10, // IID302 + 0x62, 0x6c, 0x7c, 0x08, 0x69, 0xfe, 0x00, 0x10, 0x00, 0x00, // IID303 +#endif // _LP64 + 0x62, 0xf4, 0x7c, 0x08, 0x69, 0xc3, 0x00, 0x10, 0x00, 0x00, // IID304 +#ifdef _LP64 + 0x62, 0x4c, 0x7c, 0x08, 0x69, 0xc0, 0x00, 0x00, 0x10, 0x00, // IID305 + 0x62, 0xec, 0x7c, 0x0c, 0x69, 0xe8, 0x00, 0x00, 0x01, 0x00, // IID306 + 0x62, 0xdc, 0x7c, 0x0c, 0x69, 0xc0, 0x00, 0x00, 0x01, 0x00, // IID307 + 0x62, 0x54, 0x7c, 0x0c, 0x6b, 0xed, 0x10, // IID308 + 0x62, 0xd4, 0x14, 0x10, 0x81, 0xc8, 0x00, 0x00, 0x00, 0x01, // IID309 + 0x62, 0xd4, 0x7c, 0x18, 0x81, 0xcc, 0x00, 0x00, 0x00, 0x01, // IID310 + 0xd5, 0x11, 0x81, 0xce, 0x00, 0x10, 0x00, 0x00, // IID311 + 0x62, 0xf4, 0x3c, 0x14, 0x83, 0xca, 0x10, // IID312 + 0x62, 0xd4, 0x7c, 0x1c, 0x83, 0xc8, 0x10, // IID313 + 0x62, 0xd4, 0x14, 0x1c, 0x81, 0xcd, 0x00, 0x10, 0x00, 0x00, // IID314 + 0x62, 0xd4, 0x34, 0x10, 0xd1, 0xd5, // IID315 + 0x62, 0xfc, 0x7c, 0x18, 0xd1, 0xd2, // IID316 + 0x41, 0xc1, 0xd1, 0x10, // IID317 + 0x62, 0xdc, 0x2c, 0x10, 0xc1, 0xc1, 0x08, // IID318 +#endif // _LP64 + 0x62, 0xf4, 0x7c, 0x18, 0xc1, 0xc2, 0x08, // IID319 +#ifdef _LP64 + 0xd5, 0x11, 0xc1, 0xc0, 0x10, // IID320 + 0x62, 0xf4, 0x3c, 0x14, 0xc1, 0xc1, 0x08, // IID321 + 0x62, 0xdc, 0x7c, 0x1c, 0xc1, 0xc6, 0x08, // IID322 + 0x62, 0xdc, 0x1c, 0x14, 0xc1, 0xc4, 0x10, // IID323 + 0x62, 0xdc, 0x74, 0x10, 0xc1, 0xcc, 0x04, // IID324 +#endif // _LP64 + 0x62, 0xf4, 0x7c, 0x18, 0xc1, 0xca, 0x04, // IID325 +#ifdef _LP64 + 0x41, 0xc1, 0xc8, 0x10, // IID326 + 0x62, 0xf4, 0x64, 0x14, 0xc1, 0xca, 0x10, // IID327 + 0x62, 0xdc, 0x7c, 0x1c, 0xc1, 0xcf, 0x10, // IID328 + 0x62, 0xfc, 0x4c, 0x14, 0xc1, 0xce, 0x08, // IID329 + 0x62, 0xdc, 0x44, 0x10, 0xc1, 0xe1, 0x10, // IID330 + 0x62, 0xd4, 0x7c, 0x18, 0xc1, 0xe6, 0x10, // IID331 + 0xd5, 0x11, 0xc1, 0xe7, 0x08, // IID332 + 0x62, 0xdc, 0x0c, 0x14, 0xc1, 0xe0, 0x02, // IID333 + 0x62, 0xdc, 0x7c, 0x1c, 0xc1, 0xe5, 0x02, // IID334 + 0x62, 0xd4, 0x3c, 0x1c, 0xc1, 0xe0, 0x02, // IID335 + 0x62, 0xdc, 0x6c, 0x10, 0xc1, 0xf8, 0x10, // IID336 + 0x62, 0xd4, 0x7c, 0x18, 0xc1, 0xfd, 0x10, // IID337 + 0xd5, 0x11, 0xd1, 0xf8, // IID338 + 0x62, 0xfc, 0x1c, 0x14, 0xc1, 0xf9, 0x10, // IID339 + 0x62, 0xdc, 0x7c, 0x1c, 0xc1, 0xf8, 0x10, // IID340 + 0x62, 0xfc, 0x74, 0x14, 0xc1, 0xf9, 0x04, // IID341 + 0x62, 0xf4, 0x3c, 0x10, 0xc1, 0xe1, 0x04, // IID342 + 0x62, 0xfc, 0x7c, 0x18, 0xc1, 0xe0, 0x04, // IID343 + 0x41, 0xc1, 0xe7, 0x02, // IID344 + 0x62, 0xdc, 0x0c, 0x1c, 0xc1, 0xe3, 0x04, // IID345 + 0x62, 0xfc, 0x7c, 0x1c, 0xc1, 0xe7, 0x04, // IID346 + 0x62, 0xdc, 0x0c, 0x14, 0xc1, 0xe6, 0x04, // IID347 + 0x62, 0xf4, 0x24, 0x10, 0xc1, 0xea, 0x02, // IID348 + 0x62, 0xfc, 0x7c, 0x18, 0xc1, 0xeb, 0x02, // IID349 + 0xd5, 0x10, 0xc1, 0xec, 0x02, // IID350 + 0x62, 0xfc, 0x54, 0x14, 0xd1, 0xef, // IID351 + 0x62, 0xdc, 0x7c, 0x1c, 0xd1, 0xee, // IID352 + 0x62, 0xdc, 0x34, 0x14, 0xc1, 0xe9, 0x02, // IID353 + 0x62, 0xfc, 0x3c, 0x10, 0x81, 0xeb, 0x00, 0x00, 0x10, 0x00, // IID354 + 0x62, 0xd4, 0x7c, 0x18, 0x81, 0xee, 0x00, 0x00, 0x10, 0x00, // IID355 + 0xd5, 0x10, 0x81, 0xee, 0x00, 0x00, 0x00, 0x10, // IID356 + 0x62, 0xdc, 0x3c, 0x14, 0x81, 0xe8, 0x00, 0x00, 0x01, 0x00, // IID357 + 0x62, 0xd4, 0x7c, 0x1c, 0x81, 0xee, 0x00, 0x00, 0x01, 0x00, // IID358 + 0x62, 0xdc, 0x1c, 0x14, 0x81, 0xec, 0x00, 0x00, 0x00, 0x10, // IID359 + 0x62, 0xfc, 0x64, 0x18, 0x81, 0xf4, 0x00, 0x01, 0x00, 0x00, // IID360 + 0x62, 0xd4, 0x7c, 0x18, 0x81, 0xf7, 0x00, 0x01, 0x00, 0x00, // IID361 +#endif // _LP64 + 0x81, 0xf3, 0x00, 0x10, 0x00, 0x00, // IID362 +#ifdef _LP64 + 0x62, 0xdc, 0x3c, 0x14, 0x81, 0xf6, 0x00, 0x00, 0x01, 0x00, // IID363 + 0x62, 0xdc, 0x7c, 0x1c, 0x81, 0xf7, 0x00, 0x00, 0x01, 0x00, // IID364 + 0x62, 0xdc, 0x04, 0x14, 0x81, 0xf7, 0x00, 0x10, 0x00, 0x00, // IID365 + 0x62, 0xd4, 0x5c, 0x10, 0x81, 0xea, 0x00, 0x00, 0x10, 0x00, // IID366 + 0x62, 0xd4, 0x7c, 0x18, 0x81, 0xed, 0x00, 0x00, 0x10, 0x00, // IID367 + 0xd5, 0x11, 0x81, 0xe9, 0x00, 0x00, 0x10, 0x00, // IID368 + 0x62, 0xd4, 0x44, 0x14, 0x81, 0xec, 0x00, 0x00, 0x00, 0x40, // IID369 + 0x62, 0xfc, 0x7c, 0x1c, 0x81, 0xe8, 0x00, 0x00, 0x00, 0x40, // IID370 + 0x62, 0xdc, 0x04, 0x14, 0x81, 0xef, 0x00, 0x00, 0x01, 0x00, // IID371 + 0x62, 0x54, 0x74, 0x10, 0x03, 0xa9, 0x98, 0x2f, 0xef, 0x7f, // IID372 + 0x62, 0x7c, 0x14, 0x14, 0x03, 0x86, 0x54, 0xf5, 0x08, 0xb2, // IID373 + 0x62, 0x84, 0x14, 0x18, 0x23, 0x8c, 0xfc, 0x02, 0xa9, 0xa8, 0x50, // IID374 + 0x62, 0x0c, 0x4c, 0x14, 0x23, 0x8c, 0x92, 0x54, 0x27, 0xea, 0x70, // IID375 + 0x62, 0x1c, 0x64, 0x10, 0xaf, 0xa4, 0x06, 0x73, 0x0a, 0x1a, 0x6a, // IID376 + 0x62, 0xec, 0x08, 0x14, 0xaf, 0x94, 0x9a, 0x39, 0xd7, 0x32, 0x80, // IID377 + 0x62, 0x0c, 0x7c, 0x10, 0x0b, 0xbc, 0xd9, 0xbc, 0x5d, 0x2d, 0x48, // IID378 + 0x62, 0x44, 0x34, 0x1c, 0x0b, 0x9b, 0x01, 0xee, 0xd5, 0x43, // IID379 + 0x62, 0xac, 0x74, 0x18, 0x2b, 0xbc, 0xbd, 0xbc, 0xc2, 0x25, 0x28, // IID380 + 0x62, 0x84, 0x24, 0x14, 0x2b, 0xb4, 0x7d, 0xa7, 0x0d, 0x1f, 0x77, // IID381 + 0x62, 0x44, 0x30, 0x18, 0x33, 0xb4, 0xf1, 0x72, 0x37, 0x29, 0xb5, // IID382 + 0x62, 0xa4, 0x20, 0x1c, 0x33, 0x84, 0xa3, 0xee, 0x23, 0x02, 0x0b, // IID383 + 0x62, 0x04, 0x00, 0x18, 0x32, 0xac, 0x67, 0x97, 0x85, 0xd6, 0xe0, // IID384 + 0x62, 0x6c, 0x74, 0x14, 0x32, 0xb4, 0x5f, 0x45, 0x75, 0xdc, 0x0a, // IID385 + 0x62, 0x74, 0x21, 0x10, 0x33, 0x8c, 0xb2, 0x9f, 0xf0, 0x26, 0xbc, // IID386 + 0x62, 0xcc, 0x61, 0x1c, 0x33, 0xb4, 0x34, 0x4f, 0x5f, 0xcf, 0x82, // IID387 + 0x62, 0x64, 0x0c, 0x18, 0x03, 0xc1, // IID388 + 0xd5, 0x14, 0x03, 0xc1, // IID389 + 0x62, 0x44, 0x2c, 0x14, 0x03, 0xc4, // IID390 + 0x62, 0x6c, 0x3c, 0x14, 0x03, 0xc7, // IID391 + 0x62, 0x4c, 0x14, 0x18, 0x23, 0xd7, // IID392 + 0x45, 0x23, 0xd8, // IID393 + 0x62, 0xc4, 0x74, 0x1c, 0x23, 0xdf, // IID394 + 0x62, 0x54, 0x1c, 0x1c, 0x23, 0xe4, // IID395 + 0x62, 0xec, 0x4c, 0x10, 0xaf, 0xe3, // IID396 + 0x44, 0x0f, 0xaf, 0xc2, // IID397 + 0x62, 0x6c, 0x4c, 0x14, 0xaf, 0xdf, // IID398 + 0x62, 0x7c, 0x34, 0x1c, 0xaf, 0xca, // IID399 + 0x62, 0x44, 0x75, 0x18, 0x0b, 0xf5, // IID400 + 0x66, 0xd5, 0x54, 0x0b, 0xe3, // IID401 + 0x62, 0x4c, 0x1d, 0x1c, 0x0b, 0xf3, // IID402 + 0x62, 0x7c, 0x3d, 0x1c, 0x0b, 0xc6, // IID403 + 0x62, 0xdc, 0x7c, 0x10, 0x0b, 0xce, // IID404 + 0xd5, 0x15, 0x0b, 0xd1, // IID405 + 0x62, 0xec, 0x04, 0x1c, 0x0b, 0xc9, // IID406 + 0x62, 0x5c, 0x34, 0x1c, 0x0b, 0xce, // IID407 + 0x62, 0x7c, 0x5c, 0x10, 0xa5, 0xc5, // IID408 + 0xd5, 0x95, 0xa5, 0xf2, // IID409 + 0x62, 0x74, 0x7c, 0x14, 0xa5, 0xf2, // IID410 + 0x62, 0x7c, 0x64, 0x14, 0xa5, 0xc3, // IID411 + 0x62, 0x64, 0x24, 0x10, 0xad, 0xd3, // IID412 + 0xd5, 0xd1, 0xad, 0xdc, // IID413 + 0x62, 0x54, 0x74, 0x1c, 0xad, 0xf3, // IID414 + 0x62, 0xcc, 0x04, 0x14, 0xad, 0xdf, // IID415 + 0x62, 0x5c, 0x2c, 0x10, 0x2b, 0xe9, // IID416 + 0xd5, 0x45, 0x2b, 0xc3, // IID417 + 0x62, 0xc4, 0x6c, 0x14, 0x2b, 0xe5, // IID418 + 0x62, 0xec, 0x7c, 0x14, 0x2b, 0xc2, // IID419 + 0x62, 0xc4, 0x64, 0x10, 0x33, 0xc8, // IID420 + 0xd5, 0x41, 0x33, 0xdd, // IID421 + 0x62, 0x54, 0x44, 0x14, 0x33, 0xef, // IID422 + 0x62, 0x5c, 0x24, 0x1c, 0x33, 0xdd, // IID423 + 0x62, 0xec, 0x14, 0x10, 0x24, 0xc9, 0x01, // IID424 + 0xd5, 0xd4, 0xa4, 0xc6, 0x04, // IID425 + 0x62, 0x5c, 0x3c, 0x1c, 0x24, 0xdc, 0x10, // IID426 + 0x62, 0xc4, 0x04, 0x1c, 0x24, 0xff, 0x04, // IID427 + 0x62, 0xec, 0x14, 0x10, 0x2c, 0xc6, 0x04, // IID428 + 0x45, 0x0f, 0xac, 0xcd, 0x04, // IID429 + 0x62, 0x7c, 0x04, 0x1c, 0x2c, 0xe5, 0x02, // IID430 + 0x62, 0xec, 0x74, 0x14, 0x2c, 0xf9, 0x02, // IID431 + 0x62, 0xcc, 0x6c, 0x18, 0x40, 0xc5, // IID432 + 0xd5, 0x94, 0x40, 0xd5, // IID433 + 0x62, 0x6c, 0x74, 0x10, 0x41, 0xea, // IID434 + 0xd5, 0xd5, 0x41, 0xe0, // IID435 + 0x62, 0xcc, 0x2c, 0x18, 0x42, 0xe3, // IID436 + 0x45, 0x0f, 0x42, 0xd6, // IID437 + 0x62, 0x64, 0x24, 0x18, 0x43, 0xd9, // IID438 + 0xd5, 0xc1, 0x43, 0xf7, // IID439 + 0x62, 0x6c, 0x04, 0x10, 0x44, 0xf3, // IID440 + 0xd5, 0xd1, 0x44, 0xda, // IID441 + 0x62, 0x5c, 0x54, 0x10, 0x45, 0xf2, // IID442 + 0xd5, 0xc1, 0x45, 0xe7, // IID443 + 0x62, 0x7c, 0x1c, 0x18, 0x46, 0xef, // IID444 + 0xd5, 0xd4, 0x46, 0xe4, // IID445 + 0x62, 0x44, 0x5c, 0x10, 0x47, 0xc3, // IID446 + 0x45, 0x0f, 0x47, 0xd7, // IID447 + 0x62, 0xec, 0x64, 0x10, 0x48, 0xe7, // IID448 + 0xd5, 0x95, 0x48, 0xfa, // IID449 + 0x62, 0x6c, 0x64, 0x10, 0x49, 0xc7, // IID450 + 0xd5, 0xc5, 0x49, 0xe3, // IID451 + 0x44, 0x0f, 0x4a, 0xea, // IID452 + 0xd5, 0xd4, 0x4a, 0xff, // IID453 + 0x62, 0x5c, 0x44, 0x10, 0x4b, 0xcb, // IID454 + 0xd5, 0xd0, 0x4b, 0xec, // IID455 + 0x62, 0xcc, 0x3c, 0x10, 0x4c, 0xed, // IID456 + 0x41, 0x0f, 0x4c, 0xdb, // IID457 + 0x62, 0xf4, 0x54, 0x10, 0x4d, 0xd9, // IID458 + 0xd5, 0xd4, 0x4d, 0xfd, // IID459 + 0x62, 0x4c, 0x04, 0x18, 0x4e, 0xce, // IID460 + 0xd5, 0xd1, 0x4e, 0xf9, // IID461 + 0x62, 0xd4, 0x6c, 0x10, 0x4f, 0xca, // IID462 + 0xd5, 0x91, 0x4f, 0xcf, // IID463 + 0x62, 0xcc, 0x54, 0x10, 0x40, 0x9a, 0x8d, 0xf7, 0xd6, 0x91, // IID464 + 0x62, 0xec, 0x3c, 0x10, 0x41, 0x9c, 0x0e, 0x9a, 0x5f, 0xf8, 0x11, // IID465 + 0x62, 0x6c, 0x74, 0x10, 0x42, 0x84, 0x24, 0x5e, 0x77, 0x4d, 0x53, // IID466 + 0x62, 0xec, 0x5c, 0x10, 0x43, 0x94, 0x24, 0x33, 0xb1, 0x36, 0xb8, // IID467 + 0x62, 0x7c, 0x34, 0x18, 0x44, 0xaf, 0x9d, 0x3a, 0x7c, 0xb4, // IID468 + 0x62, 0x0c, 0x24, 0x18, 0x45, 0x8c, 0x70, 0x51, 0xf8, 0x9a, 0xbb, // IID469 + 0x62, 0x0c, 0x0c, 0x18, 0x46, 0x84, 0xae, 0x1d, 0x66, 0xd0, 0x00, // IID470 + 0x62, 0x04, 0x10, 0x18, 0x47, 0x8c, 0xde, 0x03, 0x14, 0x7e, 0x04, // IID471 + 0x62, 0xe4, 0x3c, 0x10, 0x48, 0x9c, 0xd1, 0xe8, 0xac, 0xb5, 0x9b, // IID472 + 0x62, 0x6c, 0x28, 0x10, 0x49, 0x84, 0x36, 0x46, 0x24, 0x35, 0x70, // IID473 + 0x62, 0x04, 0x60, 0x10, 0x4a, 0x94, 0xb0, 0x5c, 0x2f, 0xa1, 0x78, // IID474 + 0x62, 0x5c, 0x10, 0x10, 0x4b, 0x9c, 0x21, 0x3a, 0x30, 0xa8, 0x27, // IID475 + 0x62, 0x4c, 0x48, 0x10, 0x4c, 0x84, 0x43, 0x10, 0x1a, 0x54, 0x02, // IID476 + 0x62, 0x54, 0x00, 0x10, 0x4d, 0xbc, 0xc0, 0x51, 0x32, 0x8e, 0x55, // IID477 + 0x62, 0x84, 0x24, 0x10, 0x4e, 0x94, 0x10, 0x49, 0x78, 0xe6, 0xb8, // IID478 + 0x62, 0xec, 0x68, 0x10, 0x4f, 0x84, 0x9a, 0xe2, 0x17, 0xf5, 0xed, // IID479 + 0xd5, 0x19, 0x13, 0xdf, // IID480 + 0xd5, 0x5d, 0x3b, 0xf7, // IID481 + 0xd5, 0xdd, 0xaf, 0xec, // IID482 + 0xf3, 0xd5, 0xcd, 0xb8, 0xca, // IID483 + 0xd5, 0x5c, 0x1b, 0xc4, // IID484 + 0xd5, 0x48, 0x2b, 0xc2, // IID485 + 0xf3, 0xd5, 0xdd, 0xbc, 0xd4, // IID486 + 0xf3, 0xd5, 0xcd, 0xbd, 0xe1, // IID487 + 0xd5, 0x59, 0x03, 0xe0, // IID488 + 0xd5, 0x5d, 0x23, 0xc5, // IID489 + 0xd5, 0x59, 0x0b, 0xfb, // IID490 + 0x4d, 0x33, 0xfc, // IID491 + 0xd5, 0x58, 0x8b, 0xd3, // IID492 + 0xd5, 0xcc, 0xbc, 0xf9, // IID493 + 0x4d, 0x0f, 0xbd, 0xcd, // IID494 + 0xd5, 0x98, 0xa3, 0xcc, // IID495 + 0xd5, 0x1c, 0x87, 0xc5, // IID496 + 0xd5, 0x4d, 0x85, 0xc6, // IID497 + 0xd5, 0x6c, 0x01, 0xac, 0xb9, 0x4d, 0x6c, 0xf0, 0x4f, // IID498 + 0xd5, 0x5f, 0x21, 0x94, 0x50, 0x77, 0x5e, 0x26, 0x8a, // IID499 + 0xd5, 0x48, 0x39, 0x8c, 0x1b, 0x9c, 0xd5, 0x33, 0x40, // IID500 + 0xd5, 0x5a, 0x09, 0x94, 0xe6, 0x83, 0xcb, 0x6c, 0xc7, // IID501 + 0xd5, 0x3c, 0x31, 0xa4, 0xfc, 0x60, 0x15, 0x31, 0x4b, // IID502 + 0xd5, 0x6f, 0x29, 0xac, 0xa2, 0x57, 0x26, 0x3a, 0x5c, // IID503 + 0xd5, 0x6b, 0x89, 0xb4, 0xcd, 0x3f, 0x6f, 0x3d, 0x1a, // IID504 + 0xd5, 0xfe, 0xc1, 0x8c, 0xc1, 0x28, 0x24, 0x52, 0xca, // IID505 + 0xd5, 0x19, 0x81, 0xa1, 0xc3, 0x84, 0x21, 0x63, 0x00, 0x00, 0x00, 0x01, // IID506 + 0x4b, 0x81, 0x84, 0x2d, 0x3a, 0x15, 0x8d, 0xc6, 0x00, 0x00, 0x00, 0x01, // IID507 + 0x49, 0x81, 0xb9, 0xfa, 0x37, 0x4b, 0xec, 0x00, 0x10, 0x00, 0x00, // IID508 + 0xd5, 0x19, 0xd1, 0xbf, 0x51, 0xf5, 0xa7, 0x4f, // IID509 + 0xd5, 0x3a, 0xd1, 0xa4, 0xbd, 0x32, 0x82, 0xaa, 0x31, // IID510 + 0xd5, 0x3b, 0x81, 0x9c, 0xb8, 0x49, 0xc7, 0x9a, 0xb9, 0x00, 0x00, 0x00, 0x10, // IID511 + 0xd5, 0x39, 0xc1, 0xac, 0x34, 0x4f, 0x7a, 0x01, 0xc1, 0x02, // IID512 + 0xd5, 0x18, 0x81, 0xa8, 0x15, 0x5c, 0x76, 0xec, 0x00, 0x00, 0x10, 0x00, // IID513 + 0xd5, 0x1b, 0x83, 0xb4, 0x05, 0x15, 0x26, 0x02, 0x1d, 0x10, // IID514 + 0xd5, 0x2b, 0x83, 0x8c, 0x64, 0x1e, 0x67, 0x37, 0xcb, 0x01, // IID515 + 0xd5, 0x2a, 0xc7, 0x84, 0x81, 0xf8, 0x14, 0xbb, 0xe9, 0x00, 0x01, 0x00, 0x00, // IID516 + 0xd5, 0x19, 0xf7, 0x85, 0xf5, 0x76, 0xdc, 0x82, 0x00, 0x00, 0xff, 0xff, // IID517 + 0xd5, 0x68, 0x03, 0xbc, 0x99, 0x54, 0xc6, 0xea, 0x70, // IID518 + 0xd5, 0x1b, 0x23, 0x94, 0x38, 0x57, 0x25, 0xb2, 0xdf, // IID519 + 0xd5, 0x1a, 0x3b, 0x94, 0xdf, 0xbd, 0x30, 0xc9, 0x32, // IID520 + 0xf3, 0xd5, 0xcc, 0xbd, 0xa2, 0x71, 0x3d, 0xcc, 0xab, // IID521 + 0xd5, 0x5a, 0x0b, 0xb4, 0x73, 0xc8, 0x82, 0x39, 0xd3, // IID522 + 0x4d, 0x13, 0x92, 0x9f, 0xc5, 0xd7, 0x03, // IID523 + 0x4f, 0x0f, 0xaf, 0x94, 0xc0, 0xd3, 0x79, 0x9e, 0xf1, // IID524 + 0xf3, 0xd5, 0xd9, 0xb8, 0xbd, 0x93, 0x26, 0x81, 0x88, // IID525 + 0xd5, 0x28, 0x1b, 0x8c, 0x5b, 0xcb, 0x01, 0xc6, 0x53, // IID526 + 0xd5, 0x1c, 0x2b, 0xb4, 0x19, 0x8d, 0x0f, 0x74, 0x89, // IID527 + 0xf3, 0xd5, 0xed, 0xbc, 0xac, 0x5a, 0x3c, 0x8d, 0xc9, 0x30, // IID528 + 0xd5, 0x3e, 0x33, 0x94, 0x18, 0xfe, 0x29, 0xf7, 0xc2, // IID529 + 0xd5, 0x7b, 0x8b, 0x94, 0xe4, 0x6f, 0x53, 0x04, 0x9d, // IID530 + 0x48, 0x8d, 0x99, 0xa5, 0x02, 0x06, 0x45, // IID531 + 0xf2, 0xd5, 0xbf, 0x2c, 0xa4, 0x3e, 0xd0, 0x59, 0x67, 0x98, // IID532 + 0xd5, 0x5f, 0x87, 0xbc, 0x50, 0x13, 0xed, 0x98, 0x8f, // IID533 + 0xd5, 0x2d, 0x85, 0xb4, 0xe5, 0xf2, 0x81, 0x10, 0x17, // IID534 + 0xd5, 0x19, 0x83, 0xc7, 0x10, // IID535 + 0xd5, 0x19, 0x83, 0xe1, 0x10, // IID536 + 0xd5, 0x18, 0x81, 0xd7, 0x00, 0x01, 0x00, 0x00, // IID537 + 0xd5, 0x18, 0x81, 0xfb, 0x00, 0x00, 0x00, 0x10, // IID538 + 0xd5, 0x19, 0xd1, 0xd7, // IID539 + 0xd5, 0x18, 0xd1, 0xd9, // IID540 + 0xd5, 0x19, 0xc1, 0xc1, 0x02, // IID541 + 0xd5, 0x18, 0xc1, 0xc9, 0x04, // IID542 + 0xd5, 0x19, 0xd1, 0xfc, // IID543 + 0x49, 0xc1, 0xe7, 0x04, // IID544 + 0x48, 0x81, 0xdb, 0x00, 0x00, 0x01, 0x00, // IID545 + 0xd5, 0x18, 0xd1, 0xe5, // IID546 + 0x49, 0xd1, 0xea, // IID547 + 0x49, 0x83, 0xee, 0x10, // IID548 + 0xd5, 0x18, 0x81, 0xf2, 0x00, 0x00, 0x00, 0x10, // IID549 + 0xd5, 0x18, 0xc7, 0xc7, 0x10, 0x00, 0x00, 0x00, // IID550 + 0x49, 0xbc, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, // IID551 + 0x49, 0x0f, 0xba, 0xe6, 0x04, // IID552 + 0xd5, 0x19, 0xf7, 0xc0, 0x00, 0xf0, 0xff, 0xff, // IID553 + 0xd5, 0x18, 0x81, 0xcb, 0x00, 0x00, 0x10, 0x00, // IID554 + 0x48, 0x81, 0xe9, 0x00, 0x00, 0x00, 0x10, // IID555 + 0xd5, 0x98, 0x40, 0x94, 0xdb, 0xc4, 0xc8, 0x11, 0x02, // IID556 + 0xd5, 0x98, 0x41, 0x9d, 0x43, 0x77, 0x26, 0x49, // IID557 + 0xd5, 0xeb, 0x42, 0xac, 0x60, 0xba, 0xd6, 0x73, 0xb3, // IID558 + 0xd5, 0xbd, 0x43, 0xa4, 0x22, 0x64, 0x07, 0xb2, 0xd9, // IID559 + 0xd5, 0xdb, 0x44, 0x8c, 0x8c, 0x6b, 0x19, 0x97, 0x34, // IID560 + 0xd5, 0xad, 0x45, 0xac, 0x7f, 0x67, 0xf6, 0x5c, 0xd8, // IID561 + 0xd5, 0xd8, 0x46, 0xb6, 0x05, 0xab, 0x39, 0x0f, // IID562 + 0xd5, 0xba, 0x47, 0x8c, 0xd6, 0xb4, 0x6a, 0x73, 0xfb, // IID563 + 0xd5, 0xfc, 0x48, 0x8c, 0x2b, 0x0b, 0x5b, 0x40, 0x0e, // IID564 + 0xd5, 0xbe, 0x49, 0xa4, 0xeb, 0xb5, 0xfb, 0x9d, 0x88, // IID565 + 0xd5, 0x9b, 0x4a, 0x9c, 0x56, 0xdd, 0x7c, 0x86, 0xe6, // IID566 + 0xd5, 0xfb, 0x4b, 0xac, 0x38, 0xd5, 0x9a, 0xce, 0xa8, // IID567 + 0xd5, 0xcb, 0x4c, 0x94, 0x50, 0x77, 0x41, 0xec, 0xa9, // IID568 + 0xd5, 0xfc, 0x4d, 0xa4, 0xed, 0xc4, 0xfd, 0xa0, 0x65, // IID569 + 0xd5, 0xe9, 0x4e, 0xbc, 0x13, 0xf4, 0x0e, 0xe5, 0xe2, // IID570 + 0xd5, 0xda, 0x4f, 0xb4, 0x62, 0x38, 0x1c, 0x5f, 0x1a, // IID571 + 0xd5, 0x10, 0xff, 0xd7, // IID572 + 0xd5, 0x19, 0xf7, 0xf6, // IID573 + 0xd5, 0x18, 0xf7, 0xfb, // IID574 + 0x49, 0xf7, 0xe9, // IID575 + 0x49, 0xf7, 0xe5, // IID576 + 0xd5, 0x18, 0xf7, 0xd8, // IID577 + 0xd5, 0x19, 0xf7, 0xd5, // IID578 + 0x48, 0xd3, 0xc1, // IID579 + 0xd5, 0x19, 0xd3, 0xc9, // IID580 + 0x49, 0xd3, 0xf8, // IID581 + 0xd5, 0x19, 0xd3, 0xe3, // IID582 + 0xd5, 0x19, 0xd3, 0xe6, // IID583 + 0xd5, 0x18, 0xd3, 0xef, // IID584 + 0x48, 0xff, 0xc3, // IID585 + 0x49, 0xff, 0xce, // IID586 + 0xd5, 0x18, 0x55, // IID587 + 0xd5, 0x18, 0x5d, // IID588 + 0xd5, 0x30, 0xff, 0x94, 0x6c, 0x2f, 0xaf, 0xc6, 0x56, // IID589 + 0xd5, 0x39, 0xf7, 0xa4, 0xdf, 0xdd, 0x14, 0x4b, 0xfe, // IID590 + 0xd5, 0x3b, 0xf7, 0x9c, 0x1b, 0xe1, 0x03, 0x24, 0xa7, // IID591 + 0xd5, 0x28, 0xd3, 0xbc, 0xb3, 0x2f, 0xb6, 0x9c, 0x9f, // IID592 + 0xd5, 0x39, 0xd3, 0xa4, 0xfa, 0x79, 0xa0, 0x95, 0x0b, // IID593 + 0xd5, 0x2b, 0xd3, 0xac, 0x16, 0x09, 0x4e, 0x54, 0x03, // IID594 + 0xd5, 0x19, 0xff, 0x84, 0x13, 0x50, 0x32, 0x0b, 0x12, // IID595 + 0xd5, 0x2b, 0xff, 0x8c, 0x89, 0x35, 0x13, 0x55, 0xcb, // IID596 + 0xd5, 0x7a, 0x69, 0xa4, 0x60, 0x5b, 0xfa, 0x21, 0xa6, 0x00, 0x00, 0x10, 0x00, // IID597 + 0xd5, 0x58, 0x69, 0xcf, 0x00, 0x01, 0x00, 0x00, // IID598 + 0xd5, 0x9c, 0xa4, 0xdb, 0x08, // IID599 + 0xd5, 0x9d, 0xac, 0xd4, 0x08, // IID600 + 0x62, 0xdc, 0x2c, 0x10, 0x8f, 0xc5, // IID601 + 0x62, 0xfc, 0xac, 0x18, 0x8f, 0xc6, // IID602 + 0x62, 0xdc, 0x0c, 0x10, 0xff, 0xf1, // IID603 + 0x62, 0xdc, 0x84, 0x18, 0xff, 0xf4, // IID604 + 0xd5, 0xbd, 0xb6, 0x9c, 0x9d, 0xcc, 0x72, 0xc9, 0xed, // IID605 + 0xd5, 0xaf, 0xb7, 0xb4, 0xb0, 0x22, 0x6d, 0x6c, 0xb5, // IID606 + 0xd5, 0xde, 0xbe, 0xa4, 0x3f, 0x54, 0xcb, 0x89, 0x61, // IID607 + 0xd5, 0xec, 0xbf, 0xa4, 0xfb, 0x9f, 0x9a, 0x17, 0xd2, // IID608 + 0x4c, 0x0f, 0xb6, 0xd9, // IID609 + 0xd5, 0xcd, 0xb7, 0xf7, // IID610 + 0x4c, 0x0f, 0xbe, 0xf1, // IID611 + 0xd5, 0xc9, 0xbf, 0xf9, // IID612 + 0x4f, 0x0f, 0xb1, 0xa4, 0x55, 0xc6, 0xd3, 0x39, 0xf8, // IID613 + 0x62, 0xf4, 0xfc, 0x08, 0xf7, 0xf9, // IID614 + 0x62, 0xd4, 0xfc, 0x0c, 0xf7, 0xff, // IID615 + 0x62, 0xfc, 0xfc, 0x08, 0xf7, 0xf7, // IID616 + 0x62, 0xdc, 0xfc, 0x0c, 0xf7, 0xf0, // IID617 + 0x62, 0xdc, 0xfc, 0x08, 0xf7, 0xeb, // IID618 + 0x62, 0xdc, 0xfc, 0x0c, 0xf7, 0xee, // IID619 + 0x62, 0xd4, 0xfc, 0x08, 0xf7, 0xe4, // IID620 + 0x62, 0xf4, 0xfc, 0x0c, 0xf7, 0xe1, // IID621 + 0x62, 0x94, 0xfc, 0x08, 0xf7, 0xa4, 0xcd, 0x6c, 0x54, 0x95, 0xdd, // IID622 + 0x62, 0x94, 0xf8, 0x0c, 0xf7, 0xa4, 0xc5, 0xfb, 0x89, 0x93, 0xd7, // IID623 + 0x62, 0xcc, 0xfc, 0x08, 0xaf, 0xee, // IID624 + 0xd5, 0x18, 0xf7, 0xe9, // IID625 + 0x62, 0x44, 0xfc, 0x0c, 0xaf, 0xec, // IID626 + 0x62, 0x4c, 0xfc, 0x0c, 0xaf, 0xf6, // IID627 + 0x62, 0x44, 0xfc, 0x08, 0xf5, 0xc7, // IID628 + 0x62, 0x4c, 0xfc, 0x08, 0xf5, 0xc9, // IID629 + 0x62, 0x6c, 0xfc, 0x0c, 0xf5, 0xcd, // IID630 + 0x62, 0xec, 0xfc, 0x0c, 0xf5, 0xf6, // IID631 + 0x62, 0xdc, 0xf4, 0x10, 0xf7, 0xde, // IID632 + 0xd5, 0x18, 0xf7, 0xd9, // IID633 + 0x62, 0xfc, 0x84, 0x14, 0xf7, 0xd9, // IID634 + 0x62, 0xdc, 0x94, 0x14, 0xf7, 0xdd, // IID635 + 0x62, 0xd4, 0xac, 0x18, 0xf7, 0xd1, // IID636 + 0xd5, 0x19, 0xf7, 0xd0, // IID637 + 0x62, 0x44, 0xfc, 0x08, 0x88, 0xe7, // IID638 + 0x62, 0x54, 0xfc, 0x08, 0x88, 0xd2, // IID639 + 0x62, 0x4c, 0xfc, 0x0c, 0x88, 0xde, // IID640 + 0x62, 0x4c, 0xfc, 0x0c, 0x88, 0xe4, // IID641 + 0x62, 0xd4, 0x9c, 0x10, 0xd3, 0xc6, // IID642 + 0xd5, 0x18, 0xd3, 0xc7, // IID643 + 0x62, 0xdc, 0xc4, 0x14, 0xd3, 0xc0, // IID644 + 0x62, 0xfc, 0xd4, 0x14, 0xd3, 0xc5, // IID645 + 0x62, 0xfc, 0x84, 0x10, 0xd3, 0xce, // IID646 + 0xd5, 0x19, 0xd3, 0xcc, // IID647 + 0x62, 0xd4, 0xf4, 0x14, 0xd3, 0xca, // IID648 + 0x62, 0xd4, 0xb4, 0x1c, 0xd3, 0xc9, // IID649 + 0x62, 0xdc, 0x94, 0x10, 0xd3, 0xe6, // IID650 + 0x49, 0xd3, 0xe3, // IID651 + 0x62, 0xd4, 0xac, 0x14, 0xd3, 0xe3, // IID652 + 0x62, 0xfc, 0xfc, 0x14, 0xd3, 0xe0, // IID653 + 0x62, 0xd4, 0xe4, 0x18, 0xd3, 0xff, // IID654 + 0x49, 0xd3, 0xfe, // IID655 + 0x62, 0xfc, 0xb4, 0x14, 0xd3, 0xf8, // IID656 + 0x62, 0xd4, 0xbc, 0x1c, 0xd3, 0xf8, // IID657 + 0x62, 0xd4, 0xa4, 0x18, 0xff, 0xcd, // IID658 + 0x48, 0xff, 0xc9, // IID659 + 0x62, 0xfc, 0xd4, 0x14, 0xff, 0xca, // IID660 + 0x62, 0xdc, 0x9c, 0x14, 0xff, 0xcc, // IID661 + 0xd5, 0x18, 0xff, 0xc0, // IID662 + 0xd5, 0x19, 0xff, 0xc5, // IID663 + 0x62, 0xd4, 0xec, 0x14, 0xff, 0xc1, // IID664 + 0x62, 0xfc, 0xe4, 0x14, 0xff, 0xc3, // IID665 + 0x62, 0xfc, 0xe4, 0x10, 0xd3, 0xe2, // IID666 + 0x49, 0xd3, 0xe0, // IID667 + 0x62, 0xd4, 0x9c, 0x1c, 0xd3, 0xe7, // IID668 + 0x62, 0xdc, 0x94, 0x14, 0xd3, 0xe5, // IID669 + 0x62, 0xdc, 0x9c, 0x10, 0xd3, 0xe8, // IID670 + 0xd5, 0x18, 0xd3, 0xeb, // IID671 + 0x62, 0xdc, 0xbc, 0x1c, 0xd3, 0xec, // IID672 + 0x62, 0xfc, 0xf4, 0x14, 0xd3, 0xe9, // IID673 + 0x62, 0x6c, 0xfc, 0x08, 0xf4, 0xe0, // IID674 + 0x62, 0x54, 0xfc, 0x08, 0xf4, 0xf6, // IID675 + 0x62, 0x5c, 0xfc, 0x0c, 0xf4, 0xe7, // IID676 + 0x62, 0x54, 0xfc, 0x0c, 0xf4, 0xf6, // IID677 + 0x62, 0x44, 0xfc, 0x08, 0xaf, 0xbd, 0xae, 0x4c, 0x3b, 0x96, // IID678 + 0x62, 0xec, 0xfc, 0x0c, 0xaf, 0x8a, 0xfb, 0xee, 0x54, 0x9f, // IID679 + 0x62, 0x04, 0xf8, 0x08, 0xf5, 0x9c, 0x8e, 0x83, 0xbf, 0x98, 0x27, // IID680 + 0x62, 0x84, 0xfc, 0x0c, 0xf5, 0xbc, 0x1a, 0xa3, 0x9c, 0x71, 0xc8, // IID681 + 0x62, 0xbc, 0xf4, 0x18, 0xf7, 0x9c, 0xcb, 0xc0, 0x2b, 0xb8, 0x97, // IID682 + 0x62, 0xf4, 0xf4, 0x1c, 0xf7, 0x9c, 0x0b, 0x8d, 0xd3, 0x92, 0x6f, // IID683 + 0x62, 0xc4, 0xfc, 0x08, 0x88, 0xa4, 0x24, 0x2a, 0xd8, 0x74, 0xd5, // IID684 + 0x62, 0x4c, 0xfc, 0x0c, 0x88, 0xbe, 0xd0, 0xf6, 0x03, 0x46, // IID685 + 0x62, 0xdc, 0xe4, 0x18, 0xd3, 0xa0, 0xf9, 0x06, 0x7d, 0x56, // IID686 + 0x62, 0x9c, 0x98, 0x1c, 0xd3, 0xa4, 0x20, 0xb2, 0xa7, 0xb3, 0xe3, // IID687 + 0x62, 0xbc, 0x98, 0x18, 0xd3, 0xbc, 0x87, 0x46, 0x43, 0xa8, 0xce, // IID688 + 0x62, 0x94, 0xb8, 0x1c, 0xd3, 0xbc, 0x86, 0x5b, 0x6f, 0xbd, 0x8e, // IID689 + 0x62, 0x94, 0xc4, 0x10, 0xff, 0x8c, 0x78, 0x23, 0x8d, 0x1d, 0xa5, // IID690 + 0x62, 0x9c, 0x94, 0x1c, 0xff, 0x8c, 0xcd, 0x57, 0x8b, 0xae, 0xa4, // IID691 + 0x62, 0xbc, 0xa0, 0x18, 0xff, 0x84, 0xfd, 0x24, 0x4b, 0x89, 0xde, // IID692 + 0x62, 0xf4, 0x90, 0x1c, 0xff, 0x84, 0x01, 0x37, 0xb7, 0x4b, 0xc9, // IID693 + 0x62, 0xdc, 0xac, 0x10, 0xd3, 0xac, 0x89, 0x6d, 0xb6, 0x76, 0xa0, // IID694 + 0x62, 0xd4, 0xb4, 0x14, 0xd3, 0xa9, 0x21, 0x8d, 0x79, 0x51, // IID695 + 0x62, 0x04, 0xf8, 0x08, 0xf4, 0xa4, 0x95, 0xf6, 0x96, 0x71, 0x20, // IID696 + 0x62, 0xbc, 0xfc, 0x0c, 0xf4, 0x9c, 0x2b, 0x2b, 0xc8, 0x26, 0xdb, // IID697 + 0x62, 0x4c, 0xf4, 0x10, 0x01, 0xbe, 0xff, 0xcc, 0x35, 0x39, // IID698 + 0x62, 0x1c, 0x8c, 0x18, 0x01, 0xb4, 0x93, 0x55, 0x64, 0x52, 0xcb, // IID699 + 0x62, 0x6c, 0xe8, 0x14, 0x01, 0xb4, 0x3c, 0x4b, 0xed, 0xd3, 0x5a, // IID700 + 0x62, 0xe4, 0xdc, 0x14, 0x01, 0xa2, 0x1b, 0x66, 0xd5, 0xcd, // IID701 + 0x62, 0xa4, 0x80, 0x10, 0x21, 0x8c, 0xdb, 0xd2, 0x47, 0xe2, 0x4c, // IID702 + 0x62, 0x6c, 0x88, 0x10, 0x21, 0xb4, 0x5a, 0xec, 0xc2, 0x11, 0xfb, // IID703 + 0x62, 0x44, 0x9c, 0x14, 0x21, 0x84, 0xdb, 0x41, 0xb4, 0x66, 0xd7, // IID704 + 0x62, 0x6c, 0x8c, 0x14, 0x21, 0xb6, 0x24, 0x1c, 0xd2, 0x07, // IID705 + 0x62, 0xc4, 0xa8, 0x10, 0x09, 0xa4, 0xdf, 0x92, 0x17, 0xc2, 0x58, // IID706 + 0x62, 0x14, 0x90, 0x18, 0x09, 0xac, 0x9a, 0xcd, 0x2c, 0x8f, 0xd3, // IID707 + 0x62, 0x44, 0xe4, 0x1c, 0x09, 0x94, 0x1c, 0x44, 0x0e, 0x4f, 0xe0, // IID708 + 0x62, 0x0c, 0x80, 0x14, 0x09, 0xbc, 0x7b, 0x56, 0x17, 0x8d, 0x02, // IID709 + 0x62, 0x4c, 0xb8, 0x10, 0x29, 0x9c, 0x7c, 0x10, 0xf6, 0x80, 0x69, // IID710 + 0x62, 0x14, 0x80, 0x18, 0x29, 0xbc, 0xf3, 0x19, 0x88, 0x68, 0xfb, // IID711 + 0x62, 0x0c, 0xf4, 0x14, 0x29, 0xbc, 0xa9, 0x46, 0x9e, 0x61, 0x31, // IID712 + 0x62, 0x84, 0xec, 0x14, 0x29, 0x94, 0x93, 0x1a, 0x86, 0x22, 0x19, // IID713 + 0x62, 0xc4, 0xe4, 0x18, 0x31, 0xab, 0xe0, 0x2b, 0xe9, 0xb8, // IID714 + 0x62, 0x34, 0xbc, 0x18, 0x31, 0x84, 0x8a, 0x64, 0x1c, 0x30, 0xfb, // IID715 + 0x62, 0x04, 0xf8, 0x14, 0x31, 0x8c, 0x1e, 0xd9, 0x54, 0x66, 0x7c, // IID716 + 0x62, 0x44, 0x94, 0x14, 0x31, 0xaf, 0x87, 0x4b, 0x05, 0xa1, // IID717 + 0x62, 0xd4, 0xe0, 0x10, 0x81, 0x84, 0xb5, 0x59, 0x45, 0xb6, 0x68, 0x00, 0x00, 0x00, 0x01, // IID718 + 0x62, 0x94, 0xf8, 0x14, 0x83, 0x84, 0xfd, 0x0b, 0xc5, 0xeb, 0x9a, 0x01, // IID719 + 0x62, 0x9c, 0x84, 0x10, 0x83, 0xa4, 0x68, 0xf2, 0x95, 0x4e, 0xda, 0x01, // IID720 + 0x62, 0xdc, 0xa4, 0x1c, 0x81, 0xa4, 0x24, 0xda, 0xb4, 0x92, 0xf0, 0x00, 0x00, 0x01, 0x00, // IID721 + 0x62, 0xbc, 0xfc, 0x08, 0x69, 0x8c, 0x12, 0xa1, 0x6d, 0xec, 0x46, 0x00, 0x00, 0x00, 0x01, // IID722 + 0x62, 0x14, 0xfc, 0x0c, 0x6b, 0xbc, 0xd1, 0x0d, 0x95, 0x3c, 0x80, 0x10, // IID723 + 0x62, 0x9c, 0xf0, 0x10, 0x83, 0x8c, 0x33, 0x2c, 0xda, 0x4c, 0x1b, 0x01, // IID724 + 0x62, 0x9c, 0xec, 0x1c, 0x81, 0x8c, 0xb1, 0x7b, 0x94, 0x55, 0xa6, 0x00, 0x10, 0x00, 0x00, // IID725 + 0x62, 0xdc, 0xf0, 0x10, 0xc1, 0xa4, 0x6a, 0xa1, 0x0e, 0x4e, 0x95, 0x08, // IID726 + 0x62, 0xfc, 0x98, 0x1c, 0xc1, 0xa4, 0x0e, 0x55, 0xeb, 0x53, 0xbc, 0x02, // IID727 + 0x62, 0xfc, 0x90, 0x10, 0xc1, 0xbc, 0x02, 0x9f, 0xf3, 0x23, 0xa6, 0x04, // IID728 + 0x62, 0xd4, 0xfc, 0x14, 0xc1, 0xbb, 0xec, 0x2c, 0x42, 0xf8, 0x04, // IID729 + 0x62, 0xbc, 0xa8, 0x10, 0xc1, 0xac, 0xdf, 0xec, 0xdc, 0x46, 0xaa, 0x10, // IID730 + 0x62, 0xbc, 0xc0, 0x14, 0xc1, 0xac, 0x68, 0x1d, 0x1a, 0x31, 0x71, 0x02, // IID731 + 0x62, 0xd4, 0xb4, 0x10, 0x81, 0xa9, 0x54, 0xd4, 0xac, 0xf6, 0x00, 0x00, 0x10, 0x00, // IID732 + 0x62, 0xd4, 0xf0, 0x14, 0x81, 0xac, 0x38, 0xa2, 0x6c, 0xd0, 0x55, 0x00, 0x00, 0x10, 0x00, // IID733 + 0x62, 0x94, 0x90, 0x10, 0x81, 0xb4, 0x01, 0x3f, 0xbe, 0x3e, 0xfd, 0x00, 0x00, 0x10, 0x00, // IID734 + 0x62, 0xfc, 0x98, 0x14, 0x83, 0xb4, 0x5e, 0x43, 0x65, 0x62, 0xd2, 0x10, // IID735 + 0x62, 0xd4, 0xcc, 0x10, 0x83, 0xc6, 0x10, // IID736 + 0x62, 0xd4, 0xfc, 0x18, 0x83, 0xc4, 0x10, // IID737 + 0xd5, 0x19, 0x81, 0xc0, 0x00, 0x00, 0x01, 0x00, // IID738 + 0x62, 0xf4, 0xd4, 0x14, 0x81, 0xc3, 0x00, 0x00, 0x01, 0x00, // IID739 + 0x62, 0xf4, 0xfc, 0x1c, 0x81, 0xc3, 0x00, 0x00, 0x01, 0x00, // IID740 + 0x62, 0xdc, 0xbc, 0x14, 0x81, 0xc0, 0x00, 0x00, 0x01, 0x00, // IID741 + 0x62, 0xdc, 0xd4, 0x10, 0x81, 0xe3, 0x00, 0x00, 0x00, 0x01, // IID742 + 0x62, 0xdc, 0xfc, 0x18, 0x81, 0xe3, 0x00, 0x00, 0x00, 0x01, // IID743 + 0xd5, 0x19, 0x81, 0xe0, 0x00, 0x00, 0x01, 0x00, // IID744 + 0x62, 0xdc, 0x94, 0x1c, 0x81, 0xe7, 0x00, 0x00, 0x10, 0x00, // IID745 + 0x62, 0xfc, 0xfc, 0x1c, 0x81, 0xe5, 0x00, 0x00, 0x10, 0x00, // IID746 + 0x62, 0xdc, 0x8c, 0x14, 0x81, 0xe6, 0x00, 0x00, 0x10, 0x00, // IID747 + 0x62, 0x54, 0xfc, 0x08, 0x69, 0xc5, 0x00, 0x00, 0x00, 0x10, // IID748 + 0x62, 0xdc, 0xfc, 0x08, 0x69, 0xc7, 0x00, 0x00, 0x00, 0x10, // IID749 + 0x62, 0x54, 0xfc, 0x08, 0x69, 0xed, 0x00, 0x00, 0x01, 0x00, // IID750 + 0x62, 0x5c, 0xfc, 0x0c, 0x69, 0xf5, 0x00, 0x00, 0x10, 0x00, // IID751 + 0x62, 0xfc, 0xfc, 0x0c, 0x69, 0xc6, 0x00, 0x00, 0x10, 0x00, // IID752 + 0x62, 0x54, 0xfc, 0x0c, 0x69, 0xc0, 0x00, 0x00, 0x00, 0x10, // IID753 + 0x62, 0xd4, 0x8c, 0x10, 0x81, 0xcf, 0x00, 0x10, 0x00, 0x00, // IID754 + 0x62, 0xdc, 0xfc, 0x18, 0x81, 0xcc, 0x00, 0x10, 0x00, 0x00, // IID755 + 0xd5, 0x19, 0x81, 0xca, 0x00, 0x00, 0x10, 0x00, // IID756 + 0x62, 0xd4, 0xfc, 0x14, 0x81, 0xcc, 0x00, 0x00, 0x00, 0x10, // IID757 + 0x62, 0xd4, 0xfc, 0x1c, 0x81, 0xc9, 0x00, 0x00, 0x00, 0x10, // IID758 + 0x62, 0xfc, 0xc4, 0x14, 0x81, 0xcf, 0x00, 0x01, 0x00, 0x00, // IID759 + 0x62, 0xd4, 0x84, 0x18, 0xc1, 0xd1, 0x10, // IID760 + 0x62, 0xd4, 0xfc, 0x18, 0xc1, 0xd0, 0x10, // IID761 + 0xd5, 0x19, 0xd1, 0xd1, // IID762 + 0x62, 0xfc, 0xb4, 0x18, 0xc1, 0xc1, 0x10, // IID763 + 0x62, 0xfc, 0xfc, 0x18, 0xc1, 0xc4, 0x10, // IID764 + 0xd5, 0x19, 0xd1, 0xc3, // IID765 + 0x62, 0xdc, 0xdc, 0x14, 0xd1, 0xc7, // IID766 + 0x62, 0xfc, 0xfc, 0x1c, 0xd1, 0xc2, // IID767 + 0x62, 0xdc, 0x9c, 0x14, 0xc1, 0xc4, 0x10, // IID768 + 0x62, 0xfc, 0xac, 0x10, 0xc1, 0xca, 0x10, // IID769 + 0x62, 0xdc, 0xfc, 0x18, 0xc1, 0xc8, 0x10, // IID770 + 0xd5, 0x18, 0xc1, 0xce, 0x10, // IID771 + 0x62, 0xdc, 0xa4, 0x14, 0xd1, 0xcd, // IID772 + 0x62, 0xfc, 0xfc, 0x1c, 0xd1, 0xca, // IID773 + 0x62, 0xfc, 0xd4, 0x14, 0xd1, 0xcd, // IID774 + 0x62, 0xf4, 0x9c, 0x18, 0xc1, 0xe1, 0x02, // IID775 + 0x62, 0xdc, 0xfc, 0x18, 0xc1, 0xe0, 0x02, // IID776 + 0xd5, 0x18, 0xc1, 0xe6, 0x08, // IID777 + 0x62, 0xfc, 0xf4, 0x14, 0xc1, 0xe7, 0x08, // IID778 + 0x62, 0xdc, 0xfc, 0x1c, 0xc1, 0xe3, 0x08, // IID779 + 0x62, 0xfc, 0xc4, 0x14, 0xd1, 0xe7, // IID780 + 0x62, 0xdc, 0xbc, 0x18, 0xc1, 0xf9, 0x10, // IID781 + 0x62, 0xfc, 0xfc, 0x18, 0xc1, 0xff, 0x10, // IID782 + 0x49, 0xc1, 0xf9, 0x04, // IID783 + 0x62, 0xd4, 0xcc, 0x14, 0xd1, 0xfd, // IID784 + 0x62, 0xd4, 0xfc, 0x1c, 0xd1, 0xfb, // IID785 + 0x62, 0xd4, 0x9c, 0x1c, 0xc1, 0xfc, 0x02, // IID786 + 0x62, 0xdc, 0xf4, 0x18, 0xc1, 0xe6, 0x08, // IID787 + 0x62, 0xfc, 0xfc, 0x18, 0xc1, 0xe3, 0x08, // IID788 + 0x49, 0xc1, 0xe5, 0x02, // IID789 + 0x62, 0xd4, 0xec, 0x14, 0xc1, 0xe3, 0x08, // IID790 + 0x62, 0xd4, 0xfc, 0x1c, 0xc1, 0xe1, 0x08, // IID791 + 0x62, 0xf4, 0xf4, 0x1c, 0xc1, 0xe1, 0x10, // IID792 + 0x62, 0xfc, 0xac, 0x18, 0xc1, 0xee, 0x04, // IID793 + 0x62, 0xd4, 0xfc, 0x18, 0xc1, 0xe9, 0x04, // IID794 + 0x49, 0xc1, 0xec, 0x02, // IID795 + 0x62, 0xdc, 0xac, 0x14, 0xc1, 0xef, 0x08, // IID796 + 0x62, 0xd4, 0xfc, 0x1c, 0xc1, 0xec, 0x08, // IID797 + 0x62, 0xdc, 0x9c, 0x14, 0xd1, 0xec, // IID798 + 0x62, 0xdc, 0x84, 0x18, 0x81, 0xee, 0x00, 0x00, 0x01, 0x00, // IID799 + 0x62, 0xf4, 0xfc, 0x18, 0x81, 0xe9, 0x00, 0x00, 0x01, 0x00, // IID800 + 0xd5, 0x19, 0x83, 0xea, 0x10, // IID801 + 0x62, 0xd4, 0x9c, 0x1c, 0x83, 0xee, 0x01, // IID802 + 0x62, 0xfc, 0xfc, 0x1c, 0x83, 0xed, 0x01, // IID803 + 0x62, 0xfc, 0xdc, 0x14, 0x81, 0xec, 0x00, 0x00, 0x10, 0x00, // IID804 + 0x62, 0xf4, 0xa4, 0x18, 0x81, 0xf3, 0x00, 0x00, 0x00, 0x01, // IID805 + 0x62, 0xfc, 0xfc, 0x18, 0x81, 0xf7, 0x00, 0x00, 0x00, 0x01, // IID806 + 0xd5, 0x19, 0x81, 0xf7, 0x00, 0x00, 0x00, 0x10, // IID807 + 0x62, 0xdc, 0x94, 0x14, 0x81, 0xf4, 0x00, 0x10, 0x00, 0x00, // IID808 + 0x62, 0xfc, 0xfc, 0x1c, 0x81, 0xf3, 0x00, 0x10, 0x00, 0x00, // IID809 + 0x62, 0xf4, 0xec, 0x1c, 0x81, 0xf2, 0x00, 0x00, 0x00, 0x10, // IID810 + 0x48, 0x81, 0xca, 0x00, 0x00, 0x10, 0x00, // IID811 + 0x62, 0xfc, 0xfc, 0x18, 0x81, 0xce, 0x00, 0x00, 0x10, 0x00, // IID812 + 0xd5, 0x19, 0x81, 0xcd, 0x00, 0x00, 0x10, 0x00, // IID813 + 0x62, 0xf4, 0xf4, 0x10, 0x81, 0xc9, 0x00, 0x00, 0x40, 0x00, // IID814 + 0x62, 0xdc, 0xfc, 0x18, 0x81, 0xc9, 0x00, 0x00, 0x40, 0x00, // IID815 + 0xd5, 0x19, 0x81, 0xcb, 0x00, 0x00, 0x00, 0x40, // IID816 + 0x62, 0xfc, 0xfc, 0x10, 0x81, 0xeb, 0x00, 0x00, 0x40, 0x00, // IID817 + 0x62, 0xdc, 0xfc, 0x18, 0x81, 0xef, 0x00, 0x00, 0x40, 0x00, // IID818 + 0xd5, 0x19, 0x81, 0xea, 0x00, 0x00, 0x04, 0x00, // IID819 + 0x62, 0xfc, 0xf4, 0x14, 0x81, 0xee, 0x00, 0x00, 0x00, 0x40, // IID820 + 0x62, 0xfc, 0xfc, 0x1c, 0x81, 0xea, 0x00, 0x00, 0x00, 0x40, // IID821 + 0x62, 0xfc, 0xc4, 0x14, 0x81, 0xef, 0x00, 0x00, 0x00, 0x10, // IID822 + 0x62, 0x4c, 0x90, 0x18, 0x03, 0xb4, 0x58, 0x3b, 0x3a, 0xea, 0x56, // IID823 + 0x62, 0x1c, 0x90, 0x14, 0x03, 0xbc, 0xda, 0xa8, 0xc6, 0xee, 0xb4, // IID824 + 0x62, 0x4c, 0x9c, 0x18, 0x23, 0xb7, 0x8c, 0xc3, 0xef, 0xb9, // IID825 + 0x62, 0x3c, 0xa0, 0x14, 0x23, 0x94, 0x4e, 0xe5, 0xbe, 0x1e, 0x6a, // IID826 + 0x62, 0x44, 0x88, 0x10, 0x0b, 0x94, 0x93, 0xd7, 0x00, 0x60, 0xd4, // IID827 + 0x62, 0x7c, 0xb0, 0x1c, 0x0b, 0xa4, 0x0a, 0xf6, 0x59, 0x48, 0x0b, // IID828 + 0x62, 0xcc, 0xec, 0x18, 0xaf, 0x8c, 0x90, 0xd8, 0x4c, 0x28, 0x3d, // IID829 + 0x62, 0x0c, 0x94, 0x14, 0xaf, 0x94, 0x66, 0x24, 0x31, 0x81, 0x6e, // IID830 + 0x62, 0x7c, 0xe4, 0x18, 0x2b, 0xae, 0x62, 0xd7, 0xd5, 0x8f, // IID831 + 0x62, 0x4c, 0xc4, 0x14, 0x2b, 0xac, 0x11, 0x13, 0x58, 0xad, 0x9d, // IID832 + 0x62, 0xac, 0xbc, 0x18, 0x33, 0x94, 0xb3, 0x69, 0x59, 0x40, 0xf1, // IID833 + 0x62, 0x4c, 0xac, 0x1c, 0x33, 0xa2, 0xca, 0x81, 0x83, 0x16, // IID834 + 0x62, 0xc4, 0xf4, 0x18, 0x03, 0xd0, // IID835 + 0x49, 0x03, 0xce, // IID836 + 0x62, 0x7c, 0xc4, 0x14, 0x03, 0xd0, // IID837 + 0x62, 0x5c, 0xa4, 0x1c, 0x03, 0xd8, // IID838 + 0x62, 0xe4, 0xb5, 0x18, 0x66, 0xd2, // IID839 + 0x66, 0x4d, 0x0f, 0x38, 0xf6, 0xc7, // IID840 + 0x62, 0xcc, 0x86, 0x18, 0x66, 0xf2, // IID841 + 0xf3, 0x4c, 0x0f, 0x38, 0xf6, 0xda, // IID842 + 0x62, 0xfc, 0xe4, 0x10, 0x23, 0xd6, // IID843 + 0xd5, 0x5c, 0x23, 0xe9, // IID844 + 0x62, 0x44, 0xc4, 0x14, 0x23, 0xdf, // IID845 + 0x62, 0x54, 0xb4, 0x1c, 0x23, 0xcd, // IID846 + 0x62, 0x7c, 0xec, 0x10, 0xaf, 0xf8, // IID847 + 0xd5, 0x98, 0xaf, 0xc9, // IID848 + 0x62, 0x7c, 0xc4, 0x14, 0xaf, 0xe4, // IID849 + 0x62, 0x54, 0xac, 0x1c, 0xaf, 0xd1, // IID850 + 0x62, 0xc4, 0xec, 0x18, 0x0b, 0xde, // IID851 + 0x49, 0x0b, 0xcd, // IID852 + 0x62, 0x4c, 0xb4, 0x1c, 0x0b, 0xcd, // IID853 + 0x62, 0xdc, 0xec, 0x1c, 0x0b, 0xd1, // IID854 + 0x62, 0x7c, 0xc4, 0x10, 0x2b, 0xc0, // IID855 + 0x4d, 0x2b, 0xed, // IID856 + 0x62, 0x54, 0xe4, 0x14, 0x2b, 0xe7, // IID857 + 0x62, 0x74, 0xb4, 0x1c, 0x2b, 0xca, // IID858 + 0x62, 0xcc, 0x94, 0x18, 0x33, 0xc7, // IID859 + 0xd5, 0x59, 0x33, 0xce, // IID860 + 0x62, 0x6c, 0xe4, 0x14, 0x33, 0xf4, // IID861 + 0x62, 0x44, 0x84, 0x14, 0x33, 0xfd, // IID862 + 0x62, 0x54, 0xcc, 0x10, 0x24, 0xea, 0x04, // IID863 + 0xd5, 0xd9, 0xa4, 0xe8, 0x10, // IID864 + 0x62, 0x44, 0xdc, 0x14, 0x24, 0xdd, 0x10, // IID865 + 0x62, 0xcc, 0x84, 0x14, 0x24, 0xdf, 0x02, // IID866 + 0x62, 0x7c, 0x8c, 0x10, 0x2c, 0xdc, 0x08, // IID867 + 0x4c, 0x0f, 0xac, 0xfa, 0x01, // IID868 + 0x62, 0x5c, 0x9c, 0x14, 0x2c, 0xf6, 0x02, // IID869 + 0x62, 0xec, 0xdc, 0x14, 0x2c, 0xc4, 0x01, // IID870 + 0x62, 0xcc, 0xd4, 0x10, 0x40, 0xcc, // IID871 + 0xd5, 0x9d, 0x40, 0xfe, // IID872 + 0x62, 0x54, 0xf4, 0x18, 0x41, 0xff, // IID873 + 0x49, 0x0f, 0x41, 0xcd, // IID874 + 0x62, 0x4c, 0xec, 0x18, 0x42, 0xd2, // IID875 + 0xd5, 0xcd, 0x42, 0xe7, // IID876 + 0x62, 0xf4, 0xbc, 0x18, 0x43, 0xd1, // IID877 + 0x48, 0x0f, 0x43, 0xc9, // IID878 + 0x62, 0x54, 0xac, 0x18, 0x44, 0xe9, // IID879 + 0xd5, 0x9d, 0x44, 0xf3, // IID880 + 0x62, 0xc4, 0xa4, 0x18, 0x45, 0xf9, // IID881 + 0x4c, 0x0f, 0x45, 0xda, // IID882 + 0x62, 0x5c, 0x84, 0x10, 0x46, 0xf1, // IID883 + 0xd5, 0xc9, 0x46, 0xe4, // IID884 + 0x62, 0x5c, 0xec, 0x18, 0x47, 0xd4, // IID885 + 0xd5, 0x9c, 0x47, 0xc1, // IID886 + 0x62, 0x6c, 0xf4, 0x18, 0x48, 0xf7, // IID887 + 0xd5, 0xdc, 0x48, 0xd2, // IID888 + 0x62, 0xfc, 0xec, 0x18, 0x49, 0xda, // IID889 + 0xd5, 0xc9, 0x49, 0xed, // IID890 + 0x62, 0x4c, 0xa4, 0x10, 0x4a, 0xe3, // IID891 + 0xd5, 0x9d, 0x4a, 0xde, // IID892 + 0x62, 0xec, 0xf4, 0x18, 0x4b, 0xea, // IID893 + 0xd5, 0x99, 0x4b, 0xcd, // IID894 + 0x62, 0xc4, 0xec, 0x18, 0x4c, 0xec, // IID895 + 0xd5, 0x99, 0x4c, 0xd2, // IID896 + 0x62, 0xfc, 0xf4, 0x10, 0x4d, 0xde, // IID897 + 0x49, 0x0f, 0x4d, 0xd3, // IID898 + 0x62, 0x54, 0xec, 0x18, 0x4e, 0xf0, // IID899 + 0x4d, 0x0f, 0x4e, 0xf0, // IID900 + 0x62, 0x6c, 0xb4, 0x10, 0x4f, 0xed, // IID901 + 0xd5, 0xdd, 0x4f, 0xd6, // IID902 + 0x62, 0x84, 0xbc, 0x10, 0x40, 0xac, 0x5d, 0x1e, 0x52, 0x9c, 0x43, // IID903 + 0x62, 0xcc, 0xa0, 0x18, 0x41, 0x94, 0x05, 0x7f, 0x12, 0x32, 0x06, // IID904 + 0x62, 0x14, 0xf8, 0x10, 0x42, 0x84, 0x50, 0xef, 0x3d, 0x63, 0x10, // IID905 + 0x62, 0x7c, 0x94, 0x18, 0x43, 0xb2, 0xc8, 0x61, 0x09, 0xab, // IID906 + 0x62, 0x1c, 0x98, 0x18, 0x44, 0x84, 0x57, 0x86, 0xbb, 0xe1, 0x85, // IID907 + 0xd5, 0xde, 0x45, 0xac, 0x9b, 0x2e, 0xd2, 0x27, 0xca, // IID908 + 0x62, 0x8c, 0xf0, 0x18, 0x46, 0x94, 0x21, 0xa0, 0x64, 0xbe, 0x30, // IID909 + 0x62, 0x54, 0x98, 0x10, 0x47, 0xa4, 0x42, 0x06, 0x01, 0x47, 0xdd, // IID910 + 0x62, 0x34, 0xa4, 0x18, 0x48, 0x84, 0xdb, 0x96, 0x9e, 0xcc, 0x25, // IID911 + 0x62, 0x44, 0x9c, 0x18, 0x49, 0x9b, 0x02, 0x8f, 0xd2, 0xf3, // IID912 + 0x62, 0x6c, 0xbc, 0x18, 0x4a, 0x94, 0x5b, 0x16, 0x48, 0x92, 0xb7, // IID913 + 0x62, 0x54, 0x88, 0x10, 0x4b, 0x94, 0xd6, 0x84, 0x48, 0x88, 0x14, // IID914 + 0x62, 0x1c, 0xa4, 0x10, 0x4c, 0x84, 0xb5, 0xa8, 0xb7, 0x92, 0x00, // IID915 + 0x62, 0x6c, 0x8c, 0x18, 0x4d, 0xa4, 0x13, 0x45, 0x2d, 0x9c, 0x00, // IID916 + 0x62, 0x74, 0xb0, 0x10, 0x4e, 0x84, 0x91, 0x6b, 0xc8, 0x55, 0x66, // IID917 + 0x62, 0x84, 0xe0, 0x10, 0x4f, 0xac, 0x0a, 0xf5, 0xbc, 0xfa, 0xef, // IID918 #endif // _LP64 }; @@ -1666,541 +2102,759 @@ 6, // IID181 6, // IID182 6, // IID183 - 6, // IID184 + 3, // IID184 6, // IID185 6, // IID186 6, // IID187 +#endif // _LP64 6, // IID188 +#ifdef _LP64 6, // IID189 6, // IID190 6, // IID191 - 6, // IID192 - 6, // IID193 - 6, // IID194 + 4, // IID192 + 3, // IID193 +#endif // _LP64 + 2, // IID194 +#ifdef _LP64 6, // IID195 6, // IID196 6, // IID197 - 6, // IID198 +#endif // _LP64 + 2, // IID198 +#ifdef _LP64 6, // IID199 +#endif // _LP64 6, // IID200 +#ifdef _LP64 6, // IID201 - 6, // IID202 + 4, // IID202 6, // IID203 - 11, // IID204 - 11, // IID205 - 10, // IID206 - 11, // IID207 - 11, // IID208 - 11, // IID209 - 11, // IID210 - 11, // IID211 - 11, // IID212 - 11, // IID213 - 11, // IID214 - 10, // IID215 - 11, // IID216 - 10, // IID217 - 11, // IID218 - 11, // IID219 - 11, // IID220 - 11, // IID221 - 15, // IID222 - 15, // IID223 - 14, // IID224 - 14, // IID225 - 12, // IID226 - 14, // IID227 - 12, // IID228 - 12, // IID229 + 6, // IID204 + 6, // IID205 + 4, // IID206 + 6, // IID207 + 6, // IID208 + 6, // IID209 + 3, // IID210 + 6, // IID211 +#endif // _LP64 + 6, // IID212 +#ifdef _LP64 + 6, // IID213 + 3, // IID214 + 6, // IID215 + 6, // IID216 + 6, // IID217 + 3, // IID218 + 6, // IID219 + 6, // IID220 + 6, // IID221 + 4, // IID222 + 6, // IID223 + 6, // IID224 + 6, // IID225 + 6, // IID226 + 6, // IID227 + 6, // IID228 + 11, // IID229 11, // IID230 - 12, // IID231 + 11, // IID231 11, // IID232 - 12, // IID233 - 12, // IID234 + 11, // IID233 + 11, // IID234 11, // IID235 11, // IID236 - 12, // IID237 - 15, // IID238 - 15, // IID239 - 12, // IID240 - 14, // IID241 + 11, // IID237 + 10, // IID238 + 11, // IID239 + 10, // IID240 + 11, // IID241 11, // IID242 11, // IID243 11, // IID244 11, // IID245 11, // IID246 - 11, // IID247 - 11, // IID248 - 10, // IID249 - 11, // IID250 - 11, // IID251 - 10, // IID252 - 11, // IID253 - 10, // IID254 - 10, // IID255 - 10, // IID256 - 10, // IID257 - 7, // IID258 - 7, // IID259 - 7, // IID260 - 7, // IID261 - 10, // IID262 - 10, // IID263 - 10, // IID264 - 10, // IID265 - 10, // IID266 - 10, // IID267 - 10, // IID268 - 10, // IID269 - 7, // IID270 - 7, // IID271 - 7, // IID272 - 7, // IID273 - 7, // IID274 - 7, // IID275 - 6, // IID276 - 6, // IID277 - 7, // IID278 - 7, // IID279 - 7, // IID280 - 7, // IID281 - 6, // IID282 - 6, // IID283 - 7, // IID284 - 7, // IID285 - 7, // IID286 - 7, // IID287 - 6, // IID288 - 6, // IID289 - 7, // IID290 - 7, // IID291 - 7, // IID292 - 7, // IID293 + 15, // IID247 + 14, // IID248 + 12, // IID249 + 14, // IID250 + 12, // IID251 + 12, // IID252 + 14, // IID253 + 15, // IID254 + 12, // IID255 + 12, // IID256 + 12, // IID257 + 11, // IID258 + 11, // IID259 + 12, // IID260 + 11, // IID261 + 11, // IID262 + 12, // IID263 + 14, // IID264 + 15, // IID265 + 15, // IID266 + 11, // IID267 + 11, // IID268 + 11, // IID269 + 11, // IID270 + 11, // IID271 + 11, // IID272 + 11, // IID273 + 10, // IID274 + 11, // IID275 + 11, // IID276 + 11, // IID277 + 11, // IID278 + 11, // IID279 + 11, // IID280 + 10, // IID281 + 11, // IID282 + 10, // IID283 + 11, // IID284 + 11, // IID285 + 10, // IID286 + 11, // IID287 + 10, // IID288 + 11, // IID289 + 11, // IID290 + 10, // IID291 + 10, // IID292 + 8, // IID293 7, // IID294 7, // IID295 10, // IID296 10, // IID297 10, // IID298 -#endif // _LP64 - 10, // IID299 -#ifdef _LP64 + 8, // IID299 10, // IID300 10, // IID301 - 10, // IID302 + 7, // IID302 10, // IID303 +#endif // _LP64 10, // IID304 +#ifdef _LP64 10, // IID305 10, // IID306 10, // IID307 - 11, // IID308 - 11, // IID309 - 11, // IID310 - 10, // IID311 - 11, // IID312 - 11, // IID313 - 11, // IID314 - 11, // IID315 - 11, // IID316 - 11, // IID317 - 10, // IID318 - 11, // IID319 - 11, // IID320 - 11, // IID321 - 11, // IID322 - 11, // IID323 - 6, // IID324 - 6, // IID325 - 6, // IID326 - 6, // IID327 - 6, // IID328 - 6, // IID329 - 6, // IID330 - 6, // IID331 - 6, // IID332 - 6, // IID333 - 6, // IID334 - 6, // IID335 - 6, // IID336 - 6, // IID337 - 6, // IID338 - 6, // IID339 - 6, // IID340 - 6, // IID341 + 7, // IID308 + 10, // IID309 + 10, // IID310 + 8, // IID311 + 7, // IID312 + 7, // IID313 + 10, // IID314 + 6, // IID315 + 6, // IID316 + 4, // IID317 + 7, // IID318 +#endif // _LP64 + 7, // IID319 +#ifdef _LP64 + 5, // IID320 + 7, // IID321 + 7, // IID322 + 7, // IID323 + 7, // IID324 +#endif // _LP64 + 7, // IID325 +#ifdef _LP64 + 4, // IID326 + 7, // IID327 + 7, // IID328 + 7, // IID329 + 7, // IID330 + 7, // IID331 + 5, // IID332 + 7, // IID333 + 7, // IID334 + 7, // IID335 + 7, // IID336 + 7, // IID337 + 4, // IID338 + 7, // IID339 + 7, // IID340 + 7, // IID341 7, // IID342 7, // IID343 - 7, // IID344 + 4, // IID344 7, // IID345 - 6, // IID346 - 6, // IID347 - 6, // IID348 - 6, // IID349 - 6, // IID350 + 7, // IID346 + 7, // IID347 + 7, // IID348 + 7, // IID349 + 5, // IID350 6, // IID351 6, // IID352 - 6, // IID353 - 6, // IID354 - 6, // IID355 - 6, // IID356 - 6, // IID357 - 6, // IID358 - 6, // IID359 - 6, // IID360 - 6, // IID361 - 11, // IID362 - 11, // IID363 + 7, // IID353 + 10, // IID354 + 10, // IID355 + 8, // IID356 + 10, // IID357 + 10, // IID358 + 10, // IID359 + 10, // IID360 + 10, // IID361 +#endif // _LP64 + 6, // IID362 +#ifdef _LP64 + 10, // IID363 10, // IID364 - 11, // IID365 - 11, // IID366 - 11, // IID367 - 11, // IID368 + 10, // IID365 + 10, // IID366 + 10, // IID367 + 8, // IID368 10, // IID369 - 11, // IID370 - 11, // IID371 - 11, // IID372 - 11, // IID373 + 10, // IID370 + 10, // IID371 + 10, // IID372 + 10, // IID373 11, // IID374 11, // IID375 11, // IID376 11, // IID377 - 4, // IID378 - 4, // IID379 - 4, // IID380 - 5, // IID381 - 4, // IID382 - 4, // IID383 - 5, // IID384 - 5, // IID385 - 4, // IID386 - 4, // IID387 - 4, // IID388 - 3, // IID389 - 4, // IID390 - 4, // IID391 - 4, // IID392 - 4, // IID393 - 4, // IID394 - 3, // IID395 - 9, // IID396 - 9, // IID397 - 8, // IID398 - 8, // IID399 - 9, // IID400 - 9, // IID401 - 9, // IID402 - 9, // IID403 - 11, // IID404 - 13, // IID405 - 12, // IID406 - 10, // IID407 - 10, // IID408 - 13, // IID409 - 9, // IID410 - 10, // IID411 - 10, // IID412 - 12, // IID413 - 13, // IID414 - 13, // IID415 - 9, // IID416 - 9, // IID417 - 9, // IID418 - 10, // IID419 - 9, // IID420 - 8, // IID421 - 9, // IID422 - 10, // IID423 - 9, // IID424 - 9, // IID425 - 10, // IID426 - 9, // IID427 - 9, // IID428 - 9, // IID429 - 10, // IID430 - 8, // IID431 - 9, // IID432 - 8, // IID433 - 4, // IID434 - 7, // IID435 - 8, // IID436 + 11, // IID378 + 10, // IID379 + 11, // IID380 + 11, // IID381 + 11, // IID382 + 11, // IID383 + 11, // IID384 + 11, // IID385 + 11, // IID386 + 11, // IID387 + 6, // IID388 + 4, // IID389 + 6, // IID390 + 6, // IID391 + 6, // IID392 + 3, // IID393 + 6, // IID394 + 6, // IID395 + 6, // IID396 + 4, // IID397 + 6, // IID398 + 6, // IID399 + 6, // IID400 + 5, // IID401 + 6, // IID402 + 6, // IID403 + 6, // IID404 + 4, // IID405 + 6, // IID406 + 6, // IID407 + 6, // IID408 + 4, // IID409 + 6, // IID410 + 6, // IID411 + 6, // IID412 + 4, // IID413 + 6, // IID414 + 6, // IID415 + 6, // IID416 + 4, // IID417 + 6, // IID418 + 6, // IID419 + 6, // IID420 + 4, // IID421 + 6, // IID422 + 6, // IID423 + 7, // IID424 + 5, // IID425 + 7, // IID426 + 7, // IID427 + 7, // IID428 + 5, // IID429 + 7, // IID430 + 7, // IID431 + 6, // IID432 + 4, // IID433 + 6, // IID434 + 4, // IID435 + 6, // IID436 4, // IID437 - 4, // IID438 - 5, // IID439 - 5, // IID440 + 6, // IID438 + 4, // IID439 + 6, // IID440 4, // IID441 - 5, // IID442 - 8, // IID443 - 5, // IID444 - 5, // IID445 - 8, // IID446 - 8, // IID447 - 7, // IID448 - 11, // IID449 - 5, // IID450 - 8, // IID451 - 8, // IID452 - 8, // IID453 - 9, // IID454 - 9, // IID455 - 9, // IID456 - 9, // IID457 - 9, // IID458 - 9, // IID459 - 8, // IID460 - 8, // IID461 - 9, // IID462 - 9, // IID463 - 8, // IID464 - 9, // IID465 - 8, // IID466 - 9, // IID467 - 9, // IID468 - 9, // IID469 - 3, // IID470 - 4, // IID471 - 4, // IID472 - 3, // IID473 - 3, // IID474 - 3, // IID475 - 4, // IID476 - 4, // IID477 - 4, // IID478 - 4, // IID479 - 3, // IID480 - 3, // IID481 - 3, // IID482 - 3, // IID483 + 6, // IID442 + 4, // IID443 + 6, // IID444 + 4, // IID445 + 6, // IID446 + 4, // IID447 + 6, // IID448 + 4, // IID449 + 6, // IID450 + 4, // IID451 + 4, // IID452 + 4, // IID453 + 6, // IID454 + 4, // IID455 + 6, // IID456 + 4, // IID457 + 6, // IID458 + 4, // IID459 + 6, // IID460 + 4, // IID461 + 6, // IID462 + 4, // IID463 + 10, // IID464 + 11, // IID465 + 11, // IID466 + 11, // IID467 + 10, // IID468 + 11, // IID469 + 11, // IID470 + 11, // IID471 + 11, // IID472 + 11, // IID473 + 11, // IID474 + 11, // IID475 + 11, // IID476 + 11, // IID477 + 11, // IID478 + 11, // IID479 + 4, // IID480 + 4, // IID481 + 4, // IID482 + 5, // IID483 4, // IID484 - 3, // IID485 - 3, // IID486 - 9, // IID487 - 9, // IID488 - 9, // IID489 - 9, // IID490 - 9, // IID491 - 8, // IID492 - 8, // IID493 - 9, // IID494 - 12, // IID495 - 5, // IID496 - 5, // IID497 - 5, // IID498 - 6, // IID499 - 6, // IID500 - 6, // IID501 - 6, // IID502 + 4, // IID485 + 5, // IID486 + 5, // IID487 + 4, // IID488 + 4, // IID489 + 4, // IID490 + 3, // IID491 + 4, // IID492 + 4, // IID493 + 4, // IID494 + 4, // IID495 + 4, // IID496 + 4, // IID497 + 9, // IID498 + 9, // IID499 + 9, // IID500 + 9, // IID501 + 9, // IID502 9, // IID503 9, // IID504 9, // IID505 - 9, // IID506 - 4, // IID507 - 4, // IID508 - 4, // IID509 - 4, // IID510 - 8, // IID511 - 6, // IID512 - 6, // IID513 - 6, // IID514 - 6, // IID515 - 6, // IID516 - 6, // IID517 - 6, // IID518 - 6, // IID519 - 11, // IID520 - 11, // IID521 - 6, // IID522 - 6, // IID523 - 6, // IID524 - 6, // IID525 - 6, // IID526 - 6, // IID527 - 6, // IID528 - 6, // IID529 - 6, // IID530 - 6, // IID531 - 6, // IID532 - 6, // IID533 - 6, // IID534 - 6, // IID535 - 6, // IID536 - 6, // IID537 - 6, // IID538 - 6, // IID539 - 6, // IID540 - 6, // IID541 - 6, // IID542 - 6, // IID543 - 6, // IID544 - 6, // IID545 - 6, // IID546 - 6, // IID547 - 6, // IID548 - 11, // IID549 - 11, // IID550 + 12, // IID506 + 12, // IID507 + 11, // IID508 + 8, // IID509 + 9, // IID510 + 13, // IID511 + 10, // IID512 + 12, // IID513 + 10, // IID514 + 10, // IID515 + 13, // IID516 + 12, // IID517 + 9, // IID518 + 9, // IID519 + 9, // IID520 + 9, // IID521 + 9, // IID522 + 7, // IID523 + 9, // IID524 + 9, // IID525 + 9, // IID526 + 9, // IID527 + 10, // IID528 + 9, // IID529 + 9, // IID530 + 7, // IID531 + 10, // IID532 + 9, // IID533 + 9, // IID534 + 5, // IID535 + 5, // IID536 + 8, // IID537 + 8, // IID538 + 4, // IID539 + 4, // IID540 + 5, // IID541 + 5, // IID542 + 4, // IID543 + 4, // IID544 + 7, // IID545 + 4, // IID546 + 3, // IID547 + 4, // IID548 + 8, // IID549 + 8, // IID550 10, // IID551 - 10, // IID552 - 11, // IID553 - 11, // IID554 - 11, // IID555 - 11, // IID556 - 10, // IID557 - 11, // IID558 - 11, // IID559 - 11, // IID560 - 11, // IID561 - 11, // IID562 - 11, // IID563 - 11, // IID564 - 11, // IID565 - 10, // IID566 - 11, // IID567 - 11, // IID568 - 11, // IID569 - 11, // IID570 - 11, // IID571 - 11, // IID572 - 11, // IID573 - 11, // IID574 - 10, // IID575 - 11, // IID576 - 11, // IID577 - 11, // IID578 - 14, // IID579 - 15, // IID580 - 15, // IID581 - 15, // IID582 - 12, // IID583 - 12, // IID584 - 15, // IID585 - 15, // IID586 - 12, // IID587 - 12, // IID588 - 12, // IID589 - 12, // IID590 - 12, // IID591 - 12, // IID592 - 12, // IID593 - 14, // IID594 - 15, // IID595 - 12, // IID596 - 10, // IID597 - 10, // IID598 - 10, // IID599 - 10, // IID600 - 10, // IID601 - 10, // IID602 - 10, // IID603 - 10, // IID604 - 10, // IID605 - 10, // IID606 - 10, // IID607 - 10, // IID608 - 10, // IID609 - 10, // IID610 - 10, // IID611 - 10, // IID612 - 7, // IID613 - 7, // IID614 - 7, // IID615 - 7, // IID616 - 7, // IID617 - 7, // IID618 - 7, // IID619 - 7, // IID620 - 7, // IID621 - 7, // IID622 - 7, // IID623 - 7, // IID624 - 7, // IID625 - 7, // IID626 - 7, // IID627 - 7, // IID628 - 7, // IID629 - 7, // IID630 - 7, // IID631 - 7, // IID632 - 7, // IID633 - 7, // IID634 - 7, // IID635 - 7, // IID636 - 7, // IID637 - 7, // IID638 - 10, // IID639 - 10, // IID640 - 10, // IID641 - 10, // IID642 - 10, // IID643 - 10, // IID644 - 10, // IID645 - 10, // IID646 - 10, // IID647 - 10, // IID648 - 10, // IID649 - 10, // IID650 - 10, // IID651 - 10, // IID652 - 10, // IID653 - 10, // IID654 - 11, // IID655 - 11, // IID656 - 11, // IID657 - 11, // IID658 - 11, // IID659 - 11, // IID660 - 10, // IID661 - 10, // IID662 - 10, // IID663 - 11, // IID664 - 11, // IID665 - 11, // IID666 - 6, // IID667 + 5, // IID552 + 8, // IID553 + 8, // IID554 + 7, // IID555 + 9, // IID556 + 8, // IID557 + 9, // IID558 + 9, // IID559 + 9, // IID560 + 9, // IID561 + 8, // IID562 + 9, // IID563 + 9, // IID564 + 9, // IID565 + 9, // IID566 + 9, // IID567 + 9, // IID568 + 9, // IID569 + 9, // IID570 + 9, // IID571 + 4, // IID572 + 4, // IID573 + 4, // IID574 + 3, // IID575 + 3, // IID576 + 4, // IID577 + 4, // IID578 + 3, // IID579 + 4, // IID580 + 3, // IID581 + 4, // IID582 + 4, // IID583 + 4, // IID584 + 3, // IID585 + 3, // IID586 + 3, // IID587 + 3, // IID588 + 9, // IID589 + 9, // IID590 + 9, // IID591 + 9, // IID592 + 9, // IID593 + 9, // IID594 + 9, // IID595 + 9, // IID596 + 13, // IID597 + 8, // IID598 + 5, // IID599 + 5, // IID600 + 6, // IID601 + 6, // IID602 + 6, // IID603 + 6, // IID604 + 9, // IID605 + 9, // IID606 + 9, // IID607 + 9, // IID608 + 4, // IID609 + 4, // IID610 + 4, // IID611 + 4, // IID612 + 9, // IID613 + 6, // IID614 + 6, // IID615 + 6, // IID616 + 6, // IID617 + 6, // IID618 + 6, // IID619 + 6, // IID620 + 6, // IID621 + 11, // IID622 + 11, // IID623 + 6, // IID624 + 4, // IID625 + 6, // IID626 + 6, // IID627 + 6, // IID628 + 6, // IID629 + 6, // IID630 + 6, // IID631 + 6, // IID632 + 4, // IID633 + 6, // IID634 + 6, // IID635 + 6, // IID636 + 4, // IID637 + 6, // IID638 + 6, // IID639 + 6, // IID640 + 6, // IID641 + 6, // IID642 + 4, // IID643 + 6, // IID644 + 6, // IID645 + 6, // IID646 + 4, // IID647 + 6, // IID648 + 6, // IID649 + 6, // IID650 + 3, // IID651 + 6, // IID652 + 6, // IID653 + 6, // IID654 + 3, // IID655 + 6, // IID656 + 6, // IID657 + 6, // IID658 + 3, // IID659 + 6, // IID660 + 6, // IID661 + 4, // IID662 + 4, // IID663 + 6, // IID664 + 6, // IID665 + 6, // IID666 + 3, // IID667 6, // IID668 6, // IID669 6, // IID670 - 6, // IID671 + 4, // IID671 6, // IID672 6, // IID673 6, // IID674 6, // IID675 6, // IID676 6, // IID677 - 6, // IID678 - 6, // IID679 - 6, // IID680 - 7, // IID681 - 7, // IID682 - 7, // IID683 - 7, // IID684 - 6, // IID685 - 6, // IID686 - 6, // IID687 - 6, // IID688 - 6, // IID689 - 6, // IID690 - 6, // IID691 - 6, // IID692 - 6, // IID693 - 6, // IID694 - 6, // IID695 - 6, // IID696 - 6, // IID697 - 6, // IID698 - 6, // IID699 - 6, // IID700 - 11, // IID701 + 10, // IID678 + 10, // IID679 + 11, // IID680 + 11, // IID681 + 11, // IID682 + 11, // IID683 + 11, // IID684 + 10, // IID685 + 10, // IID686 + 11, // IID687 + 11, // IID688 + 11, // IID689 + 11, // IID690 + 11, // IID691 + 11, // IID692 + 11, // IID693 + 11, // IID694 + 10, // IID695 + 11, // IID696 + 11, // IID697 + 10, // IID698 + 11, // IID699 + 11, // IID700 + 10, // IID701 11, // IID702 11, // IID703 11, // IID704 - 11, // IID705 - 10, // IID706 + 10, // IID705 + 11, // IID706 11, // IID707 - 10, // IID708 - 10, // IID709 + 11, // IID708 + 11, // IID709 11, // IID710 11, // IID711 11, // IID712 - 10, // IID713 - 11, // IID714 + 11, // IID713 + 10, // IID714 11, // IID715 11, // IID716 + 10, // IID717 + 15, // IID718 + 12, // IID719 + 12, // IID720 + 15, // IID721 + 15, // IID722 + 12, // IID723 + 12, // IID724 + 15, // IID725 + 12, // IID726 + 12, // IID727 + 12, // IID728 + 11, // IID729 + 12, // IID730 + 12, // IID731 + 14, // IID732 + 15, // IID733 + 15, // IID734 + 12, // IID735 + 7, // IID736 + 7, // IID737 + 8, // IID738 + 10, // IID739 + 10, // IID740 + 10, // IID741 + 10, // IID742 + 10, // IID743 + 8, // IID744 + 10, // IID745 + 10, // IID746 + 10, // IID747 + 10, // IID748 + 10, // IID749 + 10, // IID750 + 10, // IID751 + 10, // IID752 + 10, // IID753 + 10, // IID754 + 10, // IID755 + 8, // IID756 + 10, // IID757 + 10, // IID758 + 10, // IID759 + 7, // IID760 + 7, // IID761 + 4, // IID762 + 7, // IID763 + 7, // IID764 + 4, // IID765 + 6, // IID766 + 6, // IID767 + 7, // IID768 + 7, // IID769 + 7, // IID770 + 5, // IID771 + 6, // IID772 + 6, // IID773 + 6, // IID774 + 7, // IID775 + 7, // IID776 + 5, // IID777 + 7, // IID778 + 7, // IID779 + 6, // IID780 + 7, // IID781 + 7, // IID782 + 4, // IID783 + 6, // IID784 + 6, // IID785 + 7, // IID786 + 7, // IID787 + 7, // IID788 + 4, // IID789 + 7, // IID790 + 7, // IID791 + 7, // IID792 + 7, // IID793 + 7, // IID794 + 4, // IID795 + 7, // IID796 + 7, // IID797 + 6, // IID798 + 10, // IID799 + 10, // IID800 + 5, // IID801 + 7, // IID802 + 7, // IID803 + 10, // IID804 + 10, // IID805 + 10, // IID806 + 8, // IID807 + 10, // IID808 + 10, // IID809 + 10, // IID810 + 7, // IID811 + 10, // IID812 + 8, // IID813 + 10, // IID814 + 10, // IID815 + 8, // IID816 + 10, // IID817 + 10, // IID818 + 8, // IID819 + 10, // IID820 + 10, // IID821 + 10, // IID822 + 11, // IID823 + 11, // IID824 + 10, // IID825 + 11, // IID826 + 11, // IID827 + 11, // IID828 + 11, // IID829 + 11, // IID830 + 10, // IID831 + 11, // IID832 + 11, // IID833 + 10, // IID834 + 6, // IID835 + 3, // IID836 + 6, // IID837 + 6, // IID838 + 6, // IID839 + 6, // IID840 + 6, // IID841 + 6, // IID842 + 6, // IID843 + 4, // IID844 + 6, // IID845 + 6, // IID846 + 6, // IID847 + 4, // IID848 + 6, // IID849 + 6, // IID850 + 6, // IID851 + 3, // IID852 + 6, // IID853 + 6, // IID854 + 6, // IID855 + 3, // IID856 + 6, // IID857 + 6, // IID858 + 6, // IID859 + 4, // IID860 + 6, // IID861 + 6, // IID862 + 7, // IID863 + 5, // IID864 + 7, // IID865 + 7, // IID866 + 7, // IID867 + 5, // IID868 + 7, // IID869 + 7, // IID870 + 6, // IID871 + 4, // IID872 + 6, // IID873 + 4, // IID874 + 6, // IID875 + 4, // IID876 + 6, // IID877 + 4, // IID878 + 6, // IID879 + 4, // IID880 + 6, // IID881 + 4, // IID882 + 6, // IID883 + 4, // IID884 + 6, // IID885 + 4, // IID886 + 6, // IID887 + 4, // IID888 + 6, // IID889 + 4, // IID890 + 6, // IID891 + 4, // IID892 + 6, // IID893 + 4, // IID894 + 6, // IID895 + 4, // IID896 + 6, // IID897 + 4, // IID898 + 6, // IID899 + 4, // IID900 + 6, // IID901 + 4, // IID902 + 11, // IID903 + 11, // IID904 + 11, // IID905 + 10, // IID906 + 11, // IID907 + 9, // IID908 + 11, // IID909 + 11, // IID910 + 11, // IID911 + 10, // IID912 + 11, // IID913 + 11, // IID914 + 11, // IID915 + 11, // IID916 + 11, // IID917 + 11, // IID918 #endif // _LP64 }; @@ -2397,545 +3051,763 @@ "__ emull(Address(r22, r10, (Address::ScaleFactor)1, -0x3d379b56), false);", // IID177 "__ emull(Address(r11, -0x3249efaf), true);", // IID178 "__ elzcntl(r9, r16, false);", // IID179 - "__ elzcntl(r23, r28, true);", // IID180 - "__ enegl(r8, r30, false);", // IID181 - "__ enegl(r23, r11, true);", // IID182 - "__ epopcntl(r13, r16, false);", // IID183 - "__ epopcntl(r11, r11, true);", // IID184 - "__ enotl(r26, rcx);", // IID185 - "__ eroll(rbx, r10, false);", // IID186 - "__ eroll(r14, r29, true);", // IID187 - "__ erorl(r15, r20, false);", // IID188 - "__ erorl(r17, r12, true);", // IID189 - "__ esall(r12, rbx, false);", // IID190 - "__ esall(r23, r27, true);", // IID191 - "__ esarl(r29, r20, false);", // IID192 - "__ esarl(r28, rdx, true);", // IID193 - "__ edecl(r8, r27, false);", // IID194 - "__ edecl(rbx, r15, true);", // IID195 - "__ eincl(r11, r27, false);", // IID196 - "__ eincl(r29, r25, true);", // IID197 - "__ eshll(r12, r8, false);", // IID198 - "__ eshll(r11, r18, true);", // IID199 - "__ eshrl(rdx, r13, false);", // IID200 - "__ eshrl(r23, r24, true);", // IID201 - "__ etzcntl(r15, r15, false);", // IID202 - "__ etzcntl(r26, r28, true);", // IID203 - "__ elzcntl(rbx, Address(r25, r14, (Address::ScaleFactor)0, +0x1c13fdb6), false);", // IID204 - "__ elzcntl(r9, Address(r31, r28, (Address::ScaleFactor)3, -0x30bf8b7f), true);", // IID205 - "__ enegl(r8, Address(r25, -0x9c80fe2), false);", // IID206 - "__ enegl(r22, Address(r27, r19, (Address::ScaleFactor)2, +0x38f27c09), true);", // IID207 - "__ epopcntl(r21, Address(r14, r30, (Address::ScaleFactor)2, +0x39f92c7b), false);", // IID208 - "__ epopcntl(r26, Address(r23, r14, (Address::ScaleFactor)3, -0x602e1b3d), true);", // IID209 - "__ esall(r25, Address(r28, r23, (Address::ScaleFactor)1, +0x4ff120ef), false);", // IID210 - "__ esall(r29, Address(r24, r16, (Address::ScaleFactor)3, -0x6821bb43), true);", // IID211 - "__ esarl(r23, Address(r11, r31, (Address::ScaleFactor)2, +0x7f4224bb), false);", // IID212 - "__ esarl(r12, Address(r23, r31, (Address::ScaleFactor)1, -0x28f87a8), true);", // IID213 - "__ edecl(r19, Address(r16, r30, (Address::ScaleFactor)1, -0x27b89e0d), false);", // IID214 - "__ edecl(r26, Address(r25, +0x3d145d48), true);", // IID215 - "__ eincl(r13, Address(r27, r24, (Address::ScaleFactor)1, +0x625f3862), false);", // IID216 - "__ eincl(r11, Address(r22, +0x765904a6), true);", // IID217 - "__ eshrl(r25, Address(rdx, r17, (Address::ScaleFactor)1, -0x7d50376f), false);", // IID218 - "__ eshrl(r22, Address(r12, -0x50325da9), true);", // IID219 - "__ etzcntl(r13, Address(r13, r20, (Address::ScaleFactor)0, -0xbf3e86c), false);", // IID220 - "__ etzcntl(r26, Address(r14, r19, (Address::ScaleFactor)1, -0x24c59cb9), true);", // IID221 - "__ eaddl(r22, Address(r27, r31, (Address::ScaleFactor)2, -0x7f80902f), 1048576, false);", // IID222 - "__ eaddl(r31, Address(rdx, r21, (Address::ScaleFactor)3, -0x557cc036), 268435456, true);", // IID223 - "__ eandl(r10, Address(r26, +0x4e6bebf9), 4096, false);", // IID224 - "__ eandl(r13, Address(r30, +0x14f1a5fd), 256, true);", // IID225 - "__ eimull(r27, Address(r29, r8, (Address::ScaleFactor)0, +0x37988799), 1, false);", // IID226 - "__ eimull(r27, Address(r9, -0x446d2dc1), 256, true);", // IID227 - "__ eorl(r17, Address(r20, r25, (Address::ScaleFactor)0, +0x4957b5db), 16, false);", // IID228 - "__ eorl(r25, Address(r29, r31, (Address::ScaleFactor)1, +0x3c26a53e), 1, true);", // IID229 - "__ eorb(r15, Address(r9, -0x25974a1e), 64, false);", // IID230 - "__ eorb(r11, Address(r16, r15, (Address::ScaleFactor)2, +0x66a0329f), 4, true);", // IID231 - "__ esall(rcx, Address(rcx, r27, (Address::ScaleFactor)0, +0x38c6485e), 1, false);", // IID232 - "__ esall(r25, Address(r8, r10, (Address::ScaleFactor)0, +0x79131c34), 8, true);", // IID233 - "__ esarl(r13, Address(r9, r31, (Address::ScaleFactor)2, +0x12718ba9), 2, false);", // IID234 - "__ esarl(r15, Address(r25, -0x505836f3), 16, true);", // IID235 - "__ eshrl(r15, Address(rcx, r19, (Address::ScaleFactor)0, +0xc5c1510), 1, false);", // IID236 - "__ eshrl(r13, Address(r29, r21, (Address::ScaleFactor)2, -0x6c67309c), 8, true);", // IID237 - "__ esubl(rbx, Address(r12, r8, (Address::ScaleFactor)1, -0x3575087f), 4096, false);", // IID238 - "__ esubl(r28, Address(rbx, r21, (Address::ScaleFactor)3, -0x55f83db8), 65536, true);", // IID239 - "__ exorl(r30, Address(r21, r26, (Address::ScaleFactor)0, +0x3b4d14e1), 1, false);", // IID240 - "__ exorl(r28, Address(r18, -0x452348a1), 16777216, true);", // IID241 - "__ eaddl(r18, Address(rdx, r10, (Address::ScaleFactor)2, -0x161e1d47), r16, false);", // IID242 - "__ eaddl(r27, Address(r25, r18, (Address::ScaleFactor)3, -0x679bb823), rdx, true);", // IID243 - "__ eorl(r27, Address(r31, r29, (Address::ScaleFactor)3, +0x19ed7934), r9, false);", // IID244 - "__ eorl(r22, Address(r8, r16, (Address::ScaleFactor)2, -0x1bf71f78), r17, true);", // IID245 - "__ eorb(rcx, Address(r15, r28, (Address::ScaleFactor)3, -0x6a4a3934), r16, false);", // IID246 - "__ eorb(r28, Address(r23, r12, (Address::ScaleFactor)2, +0x3c2449f7), r16, true);", // IID247 - "__ esubl(r22, Address(r27, r10, (Address::ScaleFactor)1, -0x3c29396f), r9, false);", // IID248 - "__ esubl(r10, Address(r16, -0x165064ff), r17, true);", // IID249 - "__ exorl(r28, Address(r30, r11, (Address::ScaleFactor)0, +0x17281e3a), r20, false);", // IID250 - "__ exorl(rdx, Address(rbx, r31, (Address::ScaleFactor)3, +0x7753d0dc), r17, true);", // IID251 - "__ exorb(r9, Address(r31, +0x72a4f58e), r30, false);", // IID252 - "__ exorb(r24, Address(r25, r15, (Address::ScaleFactor)0, +0x20fc1a0a), r16, true);", // IID253 - "__ eaddl(r12, rbx, 65536, false);", // IID254 - "__ eaddl(rax, r11, 65536, false);", // IID255 - "__ eaddl(r24, r16, 268435456, true);", // IID256 - "__ eaddl(rax, r18, 268435456, true);", // IID257 - "__ eandl(r29, r13, 1, false);", // IID258 - "__ eandl(rax, r13, 1, false);", // IID259 - "__ eandl(r31, r22, 1, true);", // IID260 - "__ eandl(rax, r29, 1, true);", // IID261 - "__ eimull(r23, r29, 65536, false);", // IID262 - "__ eimull(rax, r15, 65536, false);", // IID263 - "__ eimull(r21, r9, 268435456, true);", // IID264 - "__ eimull(rax, r15, 268435456, true);", // IID265 - "__ eorl(rdx, r18, 65536, false);", // IID266 - "__ eorl(rax, r15, 65536, false);", // IID267 - "__ eorl(r8, r9, 256, true);", // IID268 - "__ eorl(rax, r27, 256, true);", // IID269 - "__ ercll(r9, r15, 8);", // IID270 - "__ ercll(rax, r18, 8);", // IID271 - "__ eroll(r12, rbx, 16, false);", // IID272 - "__ eroll(rax, r19, 16, false);", // IID273 - "__ eroll(r10, r11, 16, true);", // IID274 - "__ eroll(rax, r18, 16, true);", // IID275 - "__ erorl(rdx, r14, 1, false);", // IID276 - "__ erorl(rax, r22, 1, false);", // IID277 - "__ erorl(r25, r31, 16, true);", // IID278 - "__ erorl(rax, r19, 16, true);", // IID279 - "__ esall(r9, r15, 2, false);", // IID280 - "__ esall(rax, r13, 2, false);", // IID281 - "__ esall(r21, r16, 1, true);", // IID282 - "__ esall(rax, r21, 1, true);", // IID283 - "__ esarl(r26, r23, 8, false);", // IID284 - "__ esarl(rax, r28, 8, false);", // IID285 - "__ esarl(r26, r14, 4, true);", // IID286 - "__ esarl(rax, r10, 4, true);", // IID287 - "__ eshll(r22, r9, 1, false);", // IID288 - "__ eshll(rax, r18, 1, false);", // IID289 - "__ eshll(r30, r24, 16, true);", // IID290 - "__ eshll(rax, r23, 16, true);", // IID291 - "__ eshrl(r11, r8, 16, false);", // IID292 - "__ eshrl(rax, r16, 16, false);", // IID293 - "__ eshrl(r11, r12, 8, true);", // IID294 - "__ eshrl(rax, r29, 8, true);", // IID295 - "__ esubl(r16, r21, 1048576, false);", // IID296 - "__ esubl(rax, r15, 1048576, false);", // IID297 - "__ esubl(r9, r18, 16777216, true);", // IID298 + "__ elzcntl(r23, r23, false);", // IID180 + "__ elzcntl(r28, r8, true);", // IID181 + "__ elzcntl(r30, r30, true);", // IID182 + "__ enegl(r23, r11, false);", // IID183 + "__ enegl(r13, r13, false);", // IID184 + "__ enegl(r16, r11, true);", // IID185 + "__ enegl(r11, r11, true);", // IID186 + "__ epopcntl(r26, rcx, false);", // IID187 #endif // _LP64 - "__ esubl(rax, rbx, 16777216, true);", // IID299 + "__ epopcntl(rbx, rbx, false);", // IID188 #ifdef _LP64 - "__ exorl(r19, r23, 65536, false);", // IID300 - "__ exorl(rax, r17, 65536, false);", // IID301 - "__ exorl(r29, r18, 1048576, true);", // IID302 - "__ exorl(rax, r14, 1048576, true);", // IID303 - "__ esubl_imm32(r19, r15, 16777216, false);", // IID304 - "__ esubl_imm32(rax, r27, 16777216, false);", // IID305 - "__ esubl_imm32(r23, r27, 1073741824, true);", // IID306 - "__ esubl_imm32(rax, r23, 1073741824, true);", // IID307 - "__ eaddl(r8, r12, Address(r28, r24, (Address::ScaleFactor)3, -0x6d6d7e68), false);", // IID308 - "__ eaddl(r24, r13, Address(r24, r25, (Address::ScaleFactor)3, +0x784673fd), true);", // IID309 - "__ eandl(r24, r21, Address(r8, r13, (Address::ScaleFactor)2, -0x63663889), false);", // IID310 - "__ eandl(r12, r24, Address(r30, -0x67526556), true);", // IID311 - "__ eimull(r13, r13, Address(rbx, r25, (Address::ScaleFactor)2, -0x5f394dd9), false);", // IID312 - "__ eimull(r26, r25, Address(r25, rdx, (Address::ScaleFactor)3, -0x2e39f79a), true);", // IID313 - "__ eorl(r28, r8, Address(rdx, r24, (Address::ScaleFactor)3, -0xed99a54), false);", // IID314 - "__ eorl(r31, r22, Address(r30, r20, (Address::ScaleFactor)3, +0x3ac41cbd), true);", // IID315 - "__ esubl(r24, r30, Address(r13, r17, (Address::ScaleFactor)1, +0x1efdc2e3), false);", // IID316 - "__ esubl(r16, r16, Address(r9, r15, (Address::ScaleFactor)1, +0x769feb34), true);", // IID317 - "__ exorl(r19, r25, Address(r10, +0x2239b429), false);", // IID318 - "__ exorl(r25, r19, Address(r16, r24, (Address::ScaleFactor)1, +0x1c71faea), true);", // IID319 - "__ exorb(r19, r10, Address(r28, -0x299a0cfd), false);", // IID320 - "__ exorb(rbx, r28, Address(r23, r24, (Address::ScaleFactor)1, -0x5d78ddd9), true);", // IID321 - "__ exorw(r10, r9, Address(r13, r30, (Address::ScaleFactor)2, +0x11151188), false);", // IID322 - "__ exorw(r16, r17, Address(rdx, r31, (Address::ScaleFactor)0, +0x61936ce7), true);", // IID323 - "__ eaddl(r13, rbx, r28, false);", // IID324 - "__ eaddl(rbx, r29, r22, true);", // IID325 - "__ eandl(rbx, r8, r8, false);", // IID326 - "__ eandl(r11, r16, r13, true);", // IID327 - "__ eimull(r12, r15, r17, false);", // IID328 - "__ eimull(r23, r31, r20, true);", // IID329 - "__ eorw(r22, r26, r10, false);", // IID330 - "__ eorw(r25, r19, r11, true);", // IID331 - "__ eorl(r19, r30, r8, false);", // IID332 - "__ eorl(r12, r10, rdx, true);", // IID333 - "__ eshldl(r22, r20, r30, false);", // IID334 - "__ eshldl(r18, r19, r18, true);", // IID335 - "__ eshrdl(r25, r18, rcx, false);", // IID336 - "__ eshrdl(r19, r16, r25, true);", // IID337 - "__ esubl(r11, r31, r24, false);", // IID338 - "__ esubl(r14, r30, r16, true);", // IID339 - "__ exorl(r9, r11, r26, false);", // IID340 - "__ exorl(r27, rdx, r31, true);", // IID341 - "__ eshldl(r29, r10, rcx, 16, false);", // IID342 - "__ eshldl(r15, r23, r17, 16, true);", // IID343 - "__ eshrdl(r27, r13, r15, 8, false);", // IID344 - "__ eshrdl(r15, r29, r26, 16, true);", // IID345 - "__ ecmovl (Assembler::Condition::overflow, r18, r9, r9);", // IID346 - "__ ecmovl (Assembler::Condition::noOverflow, r22, r30, r23);", // IID347 - "__ ecmovl (Assembler::Condition::below, r11, r20, r11);", // IID348 - "__ ecmovl (Assembler::Condition::aboveEqual, rbx, r28, r16);", // IID349 - "__ ecmovl (Assembler::Condition::zero, r20, r17, r24);", // IID350 - "__ ecmovl (Assembler::Condition::notZero, r22, r16, r15);", // IID351 - "__ ecmovl (Assembler::Condition::belowEqual, r15, r28, r29);", // IID352 - "__ ecmovl (Assembler::Condition::above, r16, r25, r25);", // IID353 - "__ ecmovl (Assembler::Condition::negative, r17, r13, r17);", // IID354 - "__ ecmovl (Assembler::Condition::positive, r23, rbx, r30);", // IID355 - "__ ecmovl (Assembler::Condition::parity, r15, r22, r11);", // IID356 - "__ ecmovl (Assembler::Condition::noParity, r27, rdx, r22);", // IID357 - "__ ecmovl (Assembler::Condition::less, r9, r17, r28);", // IID358 - "__ ecmovl (Assembler::Condition::greaterEqual, r24, r11, r26);", // IID359 - "__ ecmovl (Assembler::Condition::lessEqual, r12, rcx, rbx);", // IID360 - "__ ecmovl (Assembler::Condition::greater, r28, r22, r22);", // IID361 - "__ ecmovl (Assembler::Condition::overflow, r10, r14, Address(rcx, r17, (Address::ScaleFactor)3, -0x7857b23d));", // IID362 - "__ ecmovl (Assembler::Condition::noOverflow, r17, r12, Address(r26, r24, (Address::ScaleFactor)3, +0x10642223));", // IID363 - "__ ecmovl (Assembler::Condition::below, r26, r8, Address(r31, -0xb2d2be4));", // IID364 - "__ ecmovl (Assembler::Condition::aboveEqual, r12, r20, Address(r12, r22, (Address::ScaleFactor)2, -0x667ff72b));", // IID365 - "__ ecmovl (Assembler::Condition::zero, r22, r9, Address(r27, r23, (Address::ScaleFactor)2, +0x66ce4d22));", // IID366 - "__ ecmovl (Assembler::Condition::notZero, r12, r8, Address(r30, r27, (Address::ScaleFactor)3, -0x2b9676e1));", // IID367 - "__ ecmovl (Assembler::Condition::belowEqual, r17, r20, Address(r9, r30, (Address::ScaleFactor)3, -0x351022df));", // IID368 - "__ ecmovl (Assembler::Condition::above, rdx, r8, Address(r14, +0x3d6b7a59));", // IID369 - "__ ecmovl (Assembler::Condition::negative, rcx, r31, Address(r11, r14, (Address::ScaleFactor)2, +0x2cd585f2));", // IID370 - "__ ecmovl (Assembler::Condition::positive, r25, r18, Address(r24, r11, (Address::ScaleFactor)2, -0x3f699c34));", // IID371 - "__ ecmovl (Assembler::Condition::parity, r18, r8, Address(r19, r17, (Address::ScaleFactor)2, -0x390da4c5));", // IID372 - "__ ecmovl (Assembler::Condition::noParity, r11, r29, Address(r29, rdx, (Address::ScaleFactor)2, +0x3a94a93f));", // IID373 - "__ ecmovl (Assembler::Condition::less, r13, r29, Address(r15, r23, (Address::ScaleFactor)1, +0x76d43532));", // IID374 - "__ ecmovl (Assembler::Condition::greaterEqual, r15, r12, Address(r13, r9, (Address::ScaleFactor)1, +0x16f7a5b));", // IID375 - "__ ecmovl (Assembler::Condition::lessEqual, r9, rdx, Address(r17, r23, (Address::ScaleFactor)1, +0x43b6bfe1));", // IID376 - "__ ecmovl (Assembler::Condition::greater, r28, r20, Address(r24, r10, (Address::ScaleFactor)0, -0x326e802f));", // IID377 - "__ adcq(r27, rcx);", // IID378 - "__ cmpq(r22, r15);", // IID379 - "__ imulq(r31, r30);", // IID380 - "__ popcntq(r19, r19);", // IID381 - "__ sbbq(r26, r21);", // IID382 - "__ subq(r14, r26);", // IID383 - "__ tzcntq(r20, r15);", // IID384 - "__ lzcntq(r12, r13);", // IID385 - "__ addq(r23, r28);", // IID386 - "__ andq(r20, r20);", // IID387 - "__ orq(r24, r11);", // IID388 - "__ xorq(r10, r15);", // IID389 - "__ movq(r19, r20);", // IID390 - "__ bsfq(r23, r15);", // IID391 - "__ bsrq(r26, r19);", // IID392 - "__ btq(r24, r23);", // IID393 - "__ xchgq(r28, r11);", // IID394 - "__ testq(r13, r13);", // IID395 - "__ addq(Address(r31, r23, (Address::ScaleFactor)3, +0x59da0437), rdx);", // IID396 - "__ andq(Address(r21, r20, (Address::ScaleFactor)3, +0x6fd0d557), r27);", // IID397 - "__ cmpq(Address(r21, +0x23ef6744), r11);", // IID398 - "__ orq(Address(r10, rcx, (Address::ScaleFactor)3, +0x7e8544ab), rcx);", // IID399 - "__ xorq(Address(rcx, r24, (Address::ScaleFactor)3, -0x79ca4889), rbx);", // IID400 - "__ subq(Address(r27, r31, (Address::ScaleFactor)0, +0x11f85f9a), r27);", // IID401 - "__ movq(Address(r20, r16, (Address::ScaleFactor)3, +0x72158dda), r17);", // IID402 - "__ xaddq(Address(r29, r9, (Address::ScaleFactor)2, +0x6e8febd1), r12);", // IID403 - "__ andq(Address(r15, -0x47c94ecd), 268435456);", // IID404 - "__ addq(Address(r23, r19, (Address::ScaleFactor)1, +0x32bfde3f), 256);", // IID405 - "__ cmpq(Address(r15, r11, (Address::ScaleFactor)3, +0x548e7560), 4096);", // IID406 - "__ sarq(Address(r20, r14, (Address::ScaleFactor)1, +0x1b43fc34), 2);", // IID407 - "__ salq(Address(r26, r21, (Address::ScaleFactor)0, -0x3bae50c3), 8);", // IID408 - "__ sbbq(Address(r22, r10, (Address::ScaleFactor)3, +0x47e1403), 65536);", // IID409 - "__ shrq(Address(rcx, rdx, (Address::ScaleFactor)2, +0x7ea3924d), 16);", // IID410 - "__ subq(Address(rcx, r26, (Address::ScaleFactor)3, -0x356ea53e), 16);", // IID411 - "__ xorq(Address(r30, r26, (Address::ScaleFactor)2, +0x78a12f5c), 16);", // IID412 - "__ orq(Address(r11, r10, (Address::ScaleFactor)1, +0x3713b5b5), 268435456);", // IID413 - "__ movq(Address(r30, r30, (Address::ScaleFactor)3, +0x2541a10), 65536);", // IID414 - "__ testq(Address(r16, r15, (Address::ScaleFactor)3, +0x558e3251), -16);", // IID415 - "__ addq(r27, Address(r8, r10, (Address::ScaleFactor)2, +0x635f732d));", // IID416 - "__ andq(r21, Address(r12, r31, (Address::ScaleFactor)0, -0x75e8c4a0));", // IID417 - "__ cmpq(r18, Address(r19, r16, (Address::ScaleFactor)2, -0x120ae81e));", // IID418 - "__ lzcntq(rbx, Address(r31, r30, (Address::ScaleFactor)0, +0x1ec3265d));", // IID419 - "__ orq(r16, Address(rdx, r26, (Address::ScaleFactor)0, +0x3586831b));", // IID420 - "__ adcq(r12, Address(r18, -0x3c3e9f7a));", // IID421 - "__ imulq(rcx, Address(r8, r21, (Address::ScaleFactor)3, +0x6b1515ab));", // IID422 - "__ popcntq(r29, Address(rcx, r23, (Address::ScaleFactor)2, +0x4ff06c4d));", // IID423 - "__ sbbq(r26, Address(r24, r10, (Address::ScaleFactor)1, -0x75d9a189));", // IID424 - "__ subq(r17, Address(rbx, rbx, (Address::ScaleFactor)0, +0x4033d59c));", // IID425 - "__ tzcntq(r18, Address(r22, r12, (Address::ScaleFactor)3, -0x3893347d));", // IID426 - "__ xorq(r12, Address(r20, r23, (Address::ScaleFactor)3, +0x4b311560));", // IID427 - "__ movq(r29, Address(r10, r28, (Address::ScaleFactor)2, +0x5c3a2657));", // IID428 - "__ leaq(r22, Address(r13, r25, (Address::ScaleFactor)3, +0x1a3d6f3f));", // IID429 - "__ cvttsd2siq(r25, Address(r17, r24, (Address::ScaleFactor)3, -0x35addbd8));", // IID430 - "__ xchgq(r18, Address(r25, +0x632184c3));", // IID431 - "__ testq(r29, Address(r18, r13, (Address::ScaleFactor)1, -0x5039fd8a));", // IID432 - "__ addq(r20, 4096);", // IID433 - "__ andq(r9, 16);", // IID434 - "__ adcq(rdx, 256);", // IID435 - "__ cmpq(r22, 16777216);", // IID436 - "__ rclq(r17, 1);", // IID437 - "__ rcrq(r31, 1);", // IID438 - "__ rolq(r27, 4);", // IID439 - "__ rorq(r28, 2);", // IID440 - "__ sarq(rcx, 16);", // IID441 - "__ salq(r31, 8);", // IID442 - "__ sbbq(r27, 1048576);", // IID443 - "__ shlq(r20, 16);", // IID444 - "__ shrq(r31, 8);", // IID445 - "__ subq(r27, 1048576);", // IID446 - "__ xorq(r22, 4096);", // IID447 - "__ movq(r8, 4096);", // IID448 - "__ mov64(r28, 1099511627776);", // IID449 - "__ btq(r13, 1);", // IID450 - "__ testq(r16, -1048576);", // IID451 - "__ orq_imm32(r20, 262144);", // IID452 - "__ subq_imm32(r18, 1048576);", // IID453 - "__ cmovq(Assembler::Condition::overflow, rbx, Address(r29, r8, (Address::ScaleFactor)0, +0x1d022615));", // IID454 - "__ cmovq(Assembler::Condition::noOverflow, rdx, Address(r12, r28, (Address::ScaleFactor)1, -0x34c898e2));", // IID455 - "__ cmovq(Assembler::Condition::below, r27, Address(r10, rcx, (Address::ScaleFactor)3, -0x1ef7abf1));", // IID456 - "__ cmovq(Assembler::Condition::aboveEqual, r14, Address(r13, r29, (Address::ScaleFactor)2, -0x7c4c8369));", // IID457 - "__ cmovq(Assembler::Condition::zero, r15, Address(r23, rcx, (Address::ScaleFactor)2, -0x6bd22ccf));", // IID458 - "__ cmovq(Assembler::Condition::notZero, r24, Address(r15, r10, (Address::ScaleFactor)1, -0x7ffb3d09));", // IID459 - "__ cmovq(Assembler::Condition::belowEqual, r23, Address(r11, +0x276a863b));", // IID460 - "__ cmovq(Assembler::Condition::above, r28, Address(r29, +0x3fb4396e));", // IID461 - "__ cmovq(Assembler::Condition::negative, r26, Address(r27, rcx, (Address::ScaleFactor)3, +0x4ddea61c));", // IID462 - "__ cmovq(Assembler::Condition::positive, r10, Address(r22, r19, (Address::ScaleFactor)1, +0x2a126966));", // IID463 - "__ cmovq(Assembler::Condition::parity, r12, Address(r10, +0x3d7c59f));", // IID464 - "__ cmovq(Assembler::Condition::noParity, r10, Address(r8, r8, (Address::ScaleFactor)3, -0xe61862d));", // IID465 - "__ cmovq(Assembler::Condition::less, r23, Address(r29, -0x777ed96d));", // IID466 - "__ cmovq(Assembler::Condition::greaterEqual, rcx, Address(rbx, r19, (Address::ScaleFactor)1, +0x53c601cb));", // IID467 - "__ cmovq(Assembler::Condition::lessEqual, r14, Address(r17, rbx, (Address::ScaleFactor)0, -0x768bf073));", // IID468 - "__ cmovq(Assembler::Condition::greater, r29, Address(r10, r19, (Address::ScaleFactor)1, +0x30c98d3c));", // IID469 - "__ call(r10);", // IID470 - "__ divq(r16);", // IID471 - "__ idivq(r27);", // IID472 - "__ imulq(r9);", // IID473 - "__ mulq(r13);", // IID474 - "__ negq(r14);", // IID475 - "__ notq(r18);", // IID476 - "__ rolq(r28);", // IID477 - "__ rorq(r28);", // IID478 - "__ sarq(r22);", // IID479 - "__ salq(r8);", // IID480 - "__ shlq(r12);", // IID481 - "__ shrq(rbx);", // IID482 - "__ incrementq(rcx);", // IID483 - "__ decrementq(r23);", // IID484 - "__ pushp(rcx);", // IID485 - "__ popp(r26);", // IID486 - "__ call(Address(r29, r10, (Address::ScaleFactor)0, +0x5655bc9f));", // IID487 - "__ mulq(Address(rdx, r21, (Address::ScaleFactor)3, -0x6798a630));", // IID488 - "__ negq(Address(r31, r24, (Address::ScaleFactor)0, -0x20071802));", // IID489 - "__ sarq(Address(r21, rdx, (Address::ScaleFactor)2, -0x343cb9e5));", // IID490 - "__ salq(Address(r20, r24, (Address::ScaleFactor)3, +0xa667574));", // IID491 - "__ shrq(Address(r27, +0x76b77974));", // IID492 - "__ incrementq(Address(r25, -0x534e8d31));", // IID493 - "__ decrementq(Address(r20, -0x180d3ea1));", // IID494 - "__ imulq(r17, Address(r16, -0x2af2fd58), 4096);", // IID495 - "__ imulq(r28, r25, 16);", // IID496 - "__ shldq(r27, r13, 16);", // IID497 - "__ shrdq(r8, r10, 16);", // IID498 - "__ pop2(r14, r8);", // IID499 - "__ pop2p(r18, rbx);", // IID500 - "__ push2(r23, r19);", // IID501 - "__ push2p(r12, rbx);", // IID502 - "__ movzbq(r9, Address(r14, r23, (Address::ScaleFactor)3, -0x428d2646));", // IID503 - "__ movzwq(r28, Address(r9, rcx, (Address::ScaleFactor)2, -0x72611661));", // IID504 - "__ movsbq(rbx, Address(r24, r21, (Address::ScaleFactor)2, +0x3a6be990));", // IID505 - "__ movswq(r16, Address(r22, r10, (Address::ScaleFactor)0, +0x7ef8bdd));", // IID506 - "__ movzbq(r28, r14);", // IID507 - "__ movzwq(r13, r28);", // IID508 - "__ movsbq(r11, rdx);", // IID509 - "__ movswq(r12, r26);", // IID510 - "__ cmpxchgq(r20, Address(r10, -0xbd2a8da));", // IID511 - "__ eidivq(r15, false);", // IID512 - "__ eidivq(r23, true);", // IID513 - "__ edivq(r14, false);", // IID514 - "__ edivq(r14, true);", // IID515 - "__ eimulq(r15, false);", // IID516 - "__ eimulq(r20, true);", // IID517 - "__ emulq(rcx, false);", // IID518 - "__ emulq(r21, true);", // IID519 - "__ emulq(Address(r16, r10, (Address::ScaleFactor)3, +0x5f66ac1e), false);", // IID520 - "__ emulq(Address(r21, r22, (Address::ScaleFactor)3, -0xbbc807d), true);", // IID521 - "__ eimulq(r22, r26, false);", // IID522 - "__ eimulq(r25, r21, true);", // IID523 - "__ elzcntq(r20, r13, false);", // IID524 - "__ elzcntq(r25, r19, true);", // IID525 - "__ enegq(r21, r30, false);", // IID526 - "__ enegq(r29, r11, true);", // IID527 - "__ enotq(r22, r8);", // IID528 - "__ epopcntq(r12, r19, false);", // IID529 - "__ epopcntq(r29, r23, true);", // IID530 - "__ erolq(r28, r24, false);", // IID531 - "__ erolq(rdx, r20, true);", // IID532 - "__ erorq(rbx, r30, false);", // IID533 - "__ erorq(r10, r15, true);", // IID534 - "__ esalq(r17, r13, false);", // IID535 - "__ esalq(r21, r24, true);", // IID536 - "__ esarq(r31, r12, false);", // IID537 - "__ esarq(rdx, r24, true);", // IID538 - "__ edecq(r21, r24, false);", // IID539 - "__ edecq(r15, r31, true);", // IID540 - "__ eincq(r10, rbx, false);", // IID541 - "__ eincq(r18, r8, true);", // IID542 - "__ eshlq(r10, r26, false);", // IID543 - "__ eshlq(r28, r14, true);", // IID544 - "__ eshrq(r10, r19, false);", // IID545 - "__ eshrq(r28, r21, true);", // IID546 - "__ etzcntq(r21, r22, false);", // IID547 - "__ etzcntq(r16, r23, true);", // IID548 - "__ eimulq(r11, Address(r18, r9, (Address::ScaleFactor)2, -0x132285a1), false);", // IID549 - "__ eimulq(r13, Address(r24, r15, (Address::ScaleFactor)3, +0x48f50ca0), true);", // IID550 - "__ elzcntq(r9, Address(r13, +0x2115cf0e), false);", // IID551 - "__ elzcntq(r27, Address(r30, +0x49cabbb), true);", // IID552 - "__ enegq(r21, Address(r13, r31, (Address::ScaleFactor)2, +0x50a8f4d2), false);", // IID553 - "__ enegq(r22, Address(r18, r20, (Address::ScaleFactor)1, -0x5da0584c), true);", // IID554 - "__ epopcntq(r14, Address(rbx, r22, (Address::ScaleFactor)2, -0x606349d1), false);", // IID555 - "__ epopcntq(r26, Address(r23, r22, (Address::ScaleFactor)3, -0x72c66c23), true);", // IID556 - "__ esalq(r26, Address(r9, +0x334aba09), false);", // IID557 - "__ esalq(r9, Address(r9, r30, (Address::ScaleFactor)3, -0x219a6102), true);", // IID558 - "__ esarq(r25, Address(r20, -0x2131bab1), false);", // IID559 - "__ esarq(r16, Address(r28, r16, (Address::ScaleFactor)1, +0x48c483b9), true);", // IID560 - "__ edecq(r30, Address(r9, r16, (Address::ScaleFactor)0, -0x88ce84f), false);", // IID561 - "__ edecq(r11, Address(r30, r29, (Address::ScaleFactor)2, +0x3eeb8fd0), true);", // IID562 - "__ eincq(r26, Address(r29, r10, (Address::ScaleFactor)3, +0x3ef4822e), false);", // IID563 - "__ eincq(r29, Address(r19, r20, (Address::ScaleFactor)2, -0x3f0f3db9), true);", // IID564 - "__ eshrq(r8, Address(r30, r20, (Address::ScaleFactor)0, +0x15b56a17), false);", // IID565 - "__ eshrq(r26, Address(r11, -0x2de86561), true);", // IID566 - "__ etzcntq(r11, Address(rcx, r30, (Address::ScaleFactor)1, -0x32ffb1c2), false);", // IID567 - "__ etzcntq(r23, Address(r9, r12, (Address::ScaleFactor)1, -0x54823e69), true);", // IID568 - "__ eaddq(r20, Address(r13, rcx, (Address::ScaleFactor)3, -0x46116c0d), r15, false);", // IID569 - "__ eaddq(r13, Address(r9, r23, (Address::ScaleFactor)1, -0x286c7605), r16, true);", // IID570 - "__ eandq(r21, Address(r30, r17, (Address::ScaleFactor)0, +0xf4e30b2), r29, false);", // IID571 - "__ eandq(r30, Address(r17, r31, (Address::ScaleFactor)0, +0x3ab9dec4), r17, true);", // IID572 - "__ eorq(r10, Address(r27, r30, (Address::ScaleFactor)1, -0x197f1266), r28, false);", // IID573 - "__ eorq(r9, Address(r29, r30, (Address::ScaleFactor)0, -0x24ea9b08), r11, true);", // IID574 - "__ esubq(r15, Address(r14, -0x4f44bf90), r16, false);", // IID575 - "__ esubq(rcx, Address(r21, r18, (Address::ScaleFactor)1, -0x11d0ac8f), r28, true);", // IID576 - "__ exorq(r19, Address(r19, r18, (Address::ScaleFactor)0, -0xa5e55ec), r8, false);", // IID577 - "__ exorq(r28, Address(r17, r28, (Address::ScaleFactor)1, -0x6eb42fe0), r16, true);", // IID578 - "__ eaddq(r17, Address(r18, -0x60ab1105), 16777216, false);", // IID579 - "__ eaddq(r25, Address(r19, r25, (Address::ScaleFactor)0, +0x122444d9), 65536, true);", // IID580 - "__ eandq(r30, Address(r9, r28, (Address::ScaleFactor)1, -0x25b00cf3), 4096, false);", // IID581 - "__ eandq(r9, Address(r22, rbx, (Address::ScaleFactor)1, -0x7e465026), 268435456, true);", // IID582 - "__ eimulq(r12, Address(r25, r25, (Address::ScaleFactor)1, -0x432d68cc), 1, false);", // IID583 - "__ eimulq(r15, Address(r17, r31, (Address::ScaleFactor)3, -0x2b97565e), 16, true);", // IID584 - "__ eorq(r28, Address(rdx, r31, (Address::ScaleFactor)0, +0x3f1363b1), 256, false);", // IID585 - "__ eorq(r16, Address(r12, r23, (Address::ScaleFactor)3, -0x1785863c), 16777216, true);", // IID586 - "__ esalq(r8, Address(r14, r24, (Address::ScaleFactor)2, -0x714290a5), 2, false);", // IID587 - "__ esalq(r8, Address(r15, r14, (Address::ScaleFactor)2, +0x21f13243), 16, true);", // IID588 - "__ esarq(r10, Address(r13, r29, (Address::ScaleFactor)0, +0x7d04cb72), 2, false);", // IID589 - "__ esarq(r11, Address(r21, r31, (Address::ScaleFactor)3, -0x2176b4dc), 8, true);", // IID590 - "__ eshrq(rcx, Address(r16, r12, (Address::ScaleFactor)1, +0x260c9a38), 4, false);", // IID591 - "__ eshrq(r22, Address(r26, r9, (Address::ScaleFactor)0, -0x5e56bb62), 8, true);", // IID592 - "__ esubq(r31, Address(rbx, r28, (Address::ScaleFactor)1, +0x2b00bb10), 1, false);", // IID593 - "__ esubq(r21, Address(r31, -0x6c10f4ad), 4096, true);", // IID594 - "__ exorq(r11, Address(r23, r30, (Address::ScaleFactor)1, +0x51a6026b), 65536, false);", // IID595 - "__ exorq(r14, Address(r27, r10, (Address::ScaleFactor)2, -0x34ad9bab), 16, true);", // IID596 - "__ eaddq(r20, r23, 16777216, false);", // IID597 - "__ eaddq(rax, r30, 16777216, false);", // IID598 - "__ eaddq(r9, r21, 4096, true);", // IID599 - "__ eaddq(rax, rbx, 4096, true);", // IID600 - "__ eandq(rdx, r21, 268435456, false);", // IID601 - "__ eandq(rax, r8, 268435456, false);", // IID602 - "__ eandq(r19, r31, 65536, true);", // IID603 - "__ eandq(rax, rbx, 65536, true);", // IID604 - "__ eimulq(r21, r9, 16777216, false);", // IID605 - "__ eimulq(rax, r30, 16777216, false);", // IID606 - "__ eimulq(r30, r18, 65536, true);", // IID607 - "__ eimulq(rax, r19, 65536, true);", // IID608 - "__ eorq(r20, r16, 1048576, false);", // IID609 - "__ eorq(rax, r28, 1048576, false);", // IID610 - "__ eorq(rbx, r24, 4096, true);", // IID611 - "__ eorq(rax, r22, 4096, true);", // IID612 - "__ erclq(r20, r30, 4);", // IID613 - "__ erclq(rax, r22, 4);", // IID614 - "__ erolq(rcx, r28, 2, false);", // IID615 - "__ erolq(rax, r21, 2, false);", // IID616 - "__ erolq(r26, r15, 4, true);", // IID617 - "__ erolq(rax, r19, 4, true);", // IID618 - "__ erorq(r24, r19, 8, false);", // IID619 - "__ erorq(rax, r28, 8, false);", // IID620 - "__ erorq(r25, r18, 4, true);", // IID621 - "__ erorq(rax, r13, 4, true);", // IID622 - "__ esalq(r27, r17, 2, false);", // IID623 - "__ esalq(rax, rdx, 2, false);", // IID624 - "__ esalq(rbx, r28, 16, true);", // IID625 - "__ esalq(rax, r15, 16, true);", // IID626 - "__ esarq(rbx, r12, 4, false);", // IID627 - "__ esarq(rax, rbx, 4, false);", // IID628 - "__ esarq(r17, rdx, 2, true);", // IID629 - "__ esarq(rax, r31, 2, true);", // IID630 - "__ eshlq(r21, rbx, 4, false);", // IID631 - "__ eshlq(rax, r24, 4, false);", // IID632 - "__ eshlq(r27, r13, 16, true);", // IID633 - "__ eshlq(rax, r25, 16, true);", // IID634 - "__ eshrq(rcx, r22, 16, false);", // IID635 - "__ eshrq(rax, r14, 16, false);", // IID636 - "__ eshrq(r11, r30, 4, true);", // IID637 - "__ eshrq(rax, r24, 4, true);", // IID638 - "__ esubq(r20, r19, 256, false);", // IID639 - "__ esubq(rax, r17, 256, false);", // IID640 - "__ esubq(r31, r30, 65536, true);", // IID641 - "__ esubq(rax, r18, 65536, true);", // IID642 - "__ exorq(r18, r11, 4096, false);", // IID643 - "__ exorq(rax, r10, 4096, false);", // IID644 - "__ exorq(r24, r18, 268435456, true);", // IID645 - "__ exorq(rax, rbx, 268435456, true);", // IID646 - "__ eorq_imm32(r26, r21, 4194304, false);", // IID647 - "__ eorq_imm32(rax, r8, 4194304, false);", // IID648 - "__ eorq_imm32(r22, r21, 262144, false);", // IID649 - "__ eorq_imm32(rax, r27, 262144, false);", // IID650 - "__ esubq_imm32(r16, r8, 4194304, false);", // IID651 - "__ esubq_imm32(rax, rdx, 4194304, false);", // IID652 - "__ esubq_imm32(r20, r31, 1048576, true);", // IID653 - "__ esubq_imm32(rax, r21, 1048576, true);", // IID654 - "__ eaddq(r20, r14, Address(rcx, r16, (Address::ScaleFactor)0, +0x7c6654d9), false);", // IID655 - "__ eaddq(r29, rcx, Address(r15, r23, (Address::ScaleFactor)0, +0x45b7f72d), true);", // IID656 - "__ eandq(r19, r17, Address(r13, r22, (Address::ScaleFactor)1, -0x750c1996), false);", // IID657 - "__ eandq(r13, r8, Address(r31, r23, (Address::ScaleFactor)1, -0x2211b6b2), true);", // IID658 - "__ eorq(r11, r28, Address(r13, r11, (Address::ScaleFactor)3, +0x5c0013ab), false);", // IID659 - "__ eorq(rdx, r18, Address(r18, rcx, (Address::ScaleFactor)0, +0x59557e71), true);", // IID660 - "__ eimulq(r27, r11, Address(r22, -0x28469649), false);", // IID661 - "__ eimulq(r10, r9, Address(r24, +0x49691d54), true);", // IID662 - "__ esubq(r24, r12, Address(r19, +0x22d529aa), false);", // IID663 - "__ esubq(r20, r18, Address(r9, r10, (Address::ScaleFactor)2, -0x264a7a48), true);", // IID664 - "__ exorq(rbx, r9, Address(r14, r27, (Address::ScaleFactor)0, +0xf71c02f), false);", // IID665 - "__ exorq(r25, r15, Address(r10, r12, (Address::ScaleFactor)1, +0x732367bd), true);", // IID666 - "__ eaddq(r11, r9, r10, false);", // IID667 - "__ eaddq(r25, r13, r16, true);", // IID668 - "__ eadcxq(r11, r21, r25);", // IID669 - "__ eadoxq(rdx, r20, rbx);", // IID670 - "__ eandq(r25, r21, r26, false);", // IID671 - "__ eandq(r23, r27, r21, true);", // IID672 - "__ eimulq(r10, r10, r12, false);", // IID673 - "__ eimulq(r31, r12, r23, true);", // IID674 - "__ eorq(r16, r29, r14, false);", // IID675 - "__ eorq(r19, r24, r23, true);", // IID676 - "__ esubq(r14, r21, r15, false);", // IID677 - "__ esubq(r25, r9, r29, true);", // IID678 - "__ exorq(rdx, r11, r25, false);", // IID679 - "__ exorq(r19, r10, r16, true);", // IID680 - "__ eshldq(r8, r23, r31, 8, false);", // IID681 - "__ eshldq(r31, rbx, r16, 2, true);", // IID682 - "__ eshrdq(r24, r10, r9, 2, false);", // IID683 - "__ eshrdq(r28, r26, r18, 16, true);", // IID684 - "__ ecmovq (Assembler::Condition::overflow, r25, r20, r16);", // IID685 - "__ ecmovq (Assembler::Condition::noOverflow, r21, rbx, r28);", // IID686 - "__ ecmovq (Assembler::Condition::below, r22, r19, r13);", // IID687 - "__ ecmovq (Assembler::Condition::aboveEqual, r15, rdx, r8);", // IID688 - "__ ecmovq (Assembler::Condition::zero, r22, r14, r12);", // IID689 - "__ ecmovq (Assembler::Condition::notZero, r24, r14, r24);", // IID690 - "__ ecmovq (Assembler::Condition::belowEqual, r13, r21, rbx);", // IID691 - "__ ecmovq (Assembler::Condition::above, rbx, r27, r14);", // IID692 - "__ ecmovq (Assembler::Condition::negative, r24, r27, r17);", // IID693 - "__ ecmovq (Assembler::Condition::positive, r21, r27, r27);", // IID694 - "__ ecmovq (Assembler::Condition::parity, r27, r14, r24);", // IID695 - "__ ecmovq (Assembler::Condition::noParity, r28, r29, r22);", // IID696 - "__ ecmovq (Assembler::Condition::less, r15, r13, r31);", // IID697 - "__ ecmovq (Assembler::Condition::greaterEqual, r21, r15, r30);", // IID698 - "__ ecmovq (Assembler::Condition::lessEqual, r20, r8, r13);", // IID699 - "__ ecmovq (Assembler::Condition::greater, r31, r25, r27);", // IID700 - "__ ecmovq (Assembler::Condition::overflow, r31, r15, Address(r14, r13, (Address::ScaleFactor)1, -0x6e68556));", // IID701 - "__ ecmovq (Assembler::Condition::noOverflow, r12, r28, Address(r30, r15, (Address::ScaleFactor)3, +0x3ba33f9e));", // IID702 - "__ ecmovq (Assembler::Condition::below, r16, r25, Address(r12, r9, (Address::ScaleFactor)0, -0x28e03b33));", // IID703 - "__ ecmovq (Assembler::Condition::aboveEqual, r8, r27, Address(r8, r25, (Address::ScaleFactor)3, -0x1e42bd95));", // IID704 - "__ ecmovq (Assembler::Condition::zero, rcx, r20, Address(r27, rbx, (Address::ScaleFactor)2, +0x46823c58));", // IID705 - "__ ecmovq (Assembler::Condition::notZero, rbx, r12, Address(r21, -0x635b8c8));", // IID706 - "__ ecmovq (Assembler::Condition::belowEqual, r23, rbx, Address(r27, r26, (Address::ScaleFactor)3, +0x922bcc0));", // IID707 - "__ ecmovq (Assembler::Condition::above, r25, r9, Address(r23, +0xd2a14ec));", // IID708 - "__ ecmovq (Assembler::Condition::negative, r11, r19, Address(r11, -0xfb95a9d));", // IID709 - "__ ecmovq (Assembler::Condition::positive, r13, r18, Address(r28, r19, (Address::ScaleFactor)0, +0x716b9b7e));", // IID710 - "__ ecmovq (Assembler::Condition::parity, r21, r16, Address(rcx, r29, (Address::ScaleFactor)0, -0x5af0441e));", // IID711 - "__ ecmovq (Assembler::Condition::noParity, r12, r31, Address(r20, r26, (Address::ScaleFactor)0, +0xe0b7fb1));", // IID712 - "__ ecmovq (Assembler::Condition::less, r15, r24, Address(r30, +0x2d3b7b4f));", // IID713 - "__ ecmovq (Assembler::Condition::greaterEqual, r12, r15, Address(r14, r21, (Address::ScaleFactor)2, -0x1222aee8));", // IID714 - "__ ecmovq (Assembler::Condition::lessEqual, rbx, r31, Address(r23, r20, (Address::ScaleFactor)0, -0x96e4d6a));", // IID715 - "__ ecmovq (Assembler::Condition::greater, rdx, rdx, Address(r10, rdx, (Address::ScaleFactor)3, +0x3875f17c));", // IID716 + "__ epopcntl(r10, r14, true);", // IID189 + "__ epopcntl(r29, r29, true);", // IID190 + "__ enotl(r15, r20);", // IID191 + "__ enotl(r17, r17);", // IID192 + "__ eroll(r12, r12, false);", // IID193 +#endif // _LP64 + "__ eroll(rbx, rbx, false);", // IID194 +#ifdef _LP64 + "__ eroll(r23, r27, true);", // IID195 + "__ eroll(r29, r29, true);", // IID196 + "__ erorl(r20, r28, false);", // IID197 +#endif // _LP64 + "__ erorl(rdx, rdx, false);", // IID198 +#ifdef _LP64 + "__ erorl(r8, r27, true);", // IID199 +#endif // _LP64 + "__ erorl(rbx, rbx, true);", // IID200 +#ifdef _LP64 + "__ esall(r15, r11, false);", // IID201 + "__ esall(r27, r27, false);", // IID202 + "__ esall(r29, r25, true);", // IID203 + "__ esall(r12, r12, true);", // IID204 + "__ esarl(r8, r11, false);", // IID205 + "__ esarl(r18, r18, false);", // IID206 + "__ esarl(rdx, r13, true);", // IID207 + "__ esarl(r23, r23, true);", // IID208 + "__ edecl(r24, r15, false);", // IID209 + "__ edecl(r15, r15, false);", // IID210 + "__ edecl(r26, r28, true);", // IID211 +#endif // _LP64 + "__ edecl(rbx, rbx, true);", // IID212 +#ifdef _LP64 + "__ eincl(r25, r14, false);", // IID213 + "__ eincl(r12, r12, false);", // IID214 + "__ eincl(rcx, r23, true);", // IID215 + "__ eincl(r29, r29, true);", // IID216 + "__ eshll(r22, r24, false);", // IID217 + "__ eshll(r15, r15, false);", // IID218 + "__ eshll(r9, r31, true);", // IID219 + "__ eshll(r28, r28, true);", // IID220 + "__ eshrl(r21, r18, false);", // IID221 + "__ eshrl(r24, r24, false);", // IID222 + "__ eshrl(r14, r19, true);", // IID223 + "__ eshrl(r8, r8, true);", // IID224 + "__ etzcntl(r25, r9, false);", // IID225 + "__ etzcntl(r26, r26, false);", // IID226 + "__ etzcntl(r8, r30, true);", // IID227 + "__ etzcntl(r26, r26, true);", // IID228 + "__ elzcntl(r29, Address(r25, r20, (Address::ScaleFactor)3, -0x9c80fe2), false);", // IID229 + "__ elzcntl(r22, Address(r27, r19, (Address::ScaleFactor)2, +0x38f27c09), true);", // IID230 + "__ enegl(r21, Address(r14, r30, (Address::ScaleFactor)2, +0x39f92c7b), false);", // IID231 + "__ enegl(r26, Address(r23, r14, (Address::ScaleFactor)3, -0x602e1b3d), true);", // IID232 + "__ epopcntl(r25, Address(r28, r23, (Address::ScaleFactor)1, +0x4ff120ef), false);", // IID233 + "__ epopcntl(r29, Address(r24, r16, (Address::ScaleFactor)3, -0x6821bb43), true);", // IID234 + "__ esall(r23, Address(r11, r31, (Address::ScaleFactor)2, +0x7f4224bb), false);", // IID235 + "__ esall(r12, Address(r23, r31, (Address::ScaleFactor)1, -0x28f87a8), true);", // IID236 + "__ esarl(r19, Address(r16, r30, (Address::ScaleFactor)1, -0x27b89e0d), false);", // IID237 + "__ esarl(r26, Address(r25, +0x3d145d48), true);", // IID238 + "__ edecl(r13, Address(r27, r24, (Address::ScaleFactor)1, +0x625f3862), false);", // IID239 + "__ edecl(r11, Address(r22, +0x765904a6), true);", // IID240 + "__ eincl(r25, Address(rdx, r17, (Address::ScaleFactor)1, -0x7d50376f), false);", // IID241 + "__ eincl(r22, Address(r12, -0x50325da9), true);", // IID242 + "__ eshrl(r13, Address(r13, r20, (Address::ScaleFactor)0, -0xbf3e86c), false);", // IID243 + "__ eshrl(r26, Address(r14, r19, (Address::ScaleFactor)1, -0x24c59cb9), true);", // IID244 + "__ etzcntl(r16, Address(r22, r27, (Address::ScaleFactor)2, -0x7f80902f), false);", // IID245 + "__ etzcntl(r20, Address(r31, rdx, (Address::ScaleFactor)3, +0x12254818), true);", // IID246 + "__ eaddl(r21, Address(r12, r10, (Address::ScaleFactor)3, +0x6417cf06), 1048576, false);", // IID247 + "__ eaddl(r9, Address(r13, +0x14f1a5fd), 4096, true);", // IID248 + "__ eandl(r27, Address(r29, r8, (Address::ScaleFactor)0, +0x37988799), 1, false);", // IID249 + "__ eandl(r27, Address(r9, -0x446d2dc1), 256, true);", // IID250 + "__ eimull(r17, Address(r20, r25, (Address::ScaleFactor)0, +0x4957b5db), 16, false);", // IID251 + "__ eimull(r25, Address(r29, r31, (Address::ScaleFactor)1, +0x3c26a53e), 1, true);", // IID252 + "__ eorl(r15, Address(r9, -0x25974a1e), 268435456, false);", // IID253 + "__ eorl(r11, Address(r16, r15, (Address::ScaleFactor)2, +0x66a0329f), 4096, true);", // IID254 + "__ eorb(rcx, Address(rcx, r27, (Address::ScaleFactor)0, +0x38c6485e), 1, false);", // IID255 + "__ eorb(r25, Address(r8, r10, (Address::ScaleFactor)0, +0x79131c34), 64, true);", // IID256 + "__ esall(r13, Address(r9, r31, (Address::ScaleFactor)2, +0x12718ba9), 2, false);", // IID257 + "__ esall(r15, Address(r25, -0x505836f3), 16, true);", // IID258 + "__ esarl(r15, Address(rcx, r19, (Address::ScaleFactor)0, +0xc5c1510), 1, false);", // IID259 + "__ esarl(r13, Address(r29, r21, (Address::ScaleFactor)2, -0x6c67309c), 8, true);", // IID260 + "__ eshrl(r11, Address(rbx, +0x749f67d0), 16, false);", // IID261 + "__ eshrl(r14, Address(r14, -0x55f83db8), 4, true);", // IID262 + "__ esubl(r30, Address(r21, r26, (Address::ScaleFactor)0, +0x3b4d14e1), 1, false);", // IID263 + "__ esubl(r28, Address(r18, -0x452348a1), 16777216, true);", // IID264 + "__ exorl(rdx, Address(r10, r16, (Address::ScaleFactor)2, -0x161e1d47), 16777216, false);", // IID265 + "__ exorl(rdx, Address(r29, r23, (Address::ScaleFactor)1, +0x1b34e2f8), 16777216, true);", // IID266 + "__ eaddl(r19, Address(r27, r31, (Address::ScaleFactor)0, +0x1f3ce7d8), r29, false);", // IID267 + "__ eaddl(r28, Address(r24, rcx, (Address::ScaleFactor)3, -0x6053edc2), r28, false);", // IID268 + "__ eaddl(r17, Address(r18, r24, (Address::ScaleFactor)3, -0x1bf71f78), r29, true);", // IID269 + "__ eaddl(rcx, Address(r15, r28, (Address::ScaleFactor)1, +0x15b8216), rcx, true);", // IID270 + "__ eorl(r30, Address(rbx, rdx, (Address::ScaleFactor)3, -0x463540b4), r28, false);", // IID271 + "__ eorl(r18, Address(r28, r10, (Address::ScaleFactor)3, +0x3523a73b), r18, false);", // IID272 + "__ eorl(r9, Address(r15, r15, (Address::ScaleFactor)1, -0x2a0bdd56), r21, true);", // IID273 + "__ eorl(r16, Address(r23, -0x165064ff), r16, true);", // IID274 + "__ eorb(r28, Address(r30, r11, (Address::ScaleFactor)0, +0x17281e3a), r20, false);", // IID275 + "__ eorb(rdx, Address(rbx, r31, (Address::ScaleFactor)2, +0x2477b5bb), rdx, false);", // IID276 + "__ eorb(r16, Address(r11, rcx, (Address::ScaleFactor)1, -0x3175d1af), r24, true);", // IID277 + "__ eorb(rbx, Address(r11, r20, (Address::ScaleFactor)3, -0x22d67bd3), rbx, true);", // IID278 + "__ esubl(r26, Address(r27, r30, (Address::ScaleFactor)1, -0x3d9bce2e), rdx, false);", // IID279 + "__ esubl(r31, Address(r22, r29, (Address::ScaleFactor)1, +0x14218519), r31, false);", // IID280 + "__ esubl(r21, Address(r9, -0x1050127a), r13, true);", // IID281 + "__ esubl(r31, Address(r9, r8, (Address::ScaleFactor)0, -0xae18961), r31, true);", // IID282 + "__ exorl(r15, Address(r18, +0x5c2bbce5), r12, false);", // IID283 + "__ exorl(r27, Address(r25, r23, (Address::ScaleFactor)0, +0x5c6078b3), r27, false);", // IID284 + "__ exorl(r18, Address(r8, rdx, (Address::ScaleFactor)3, -0x9ed3881), r14, true);", // IID285 + "__ exorl(r9, Address(r15, +0x775acdad), r9, true);", // IID286 + "__ exorb(r21, Address(r18, r26, (Address::ScaleFactor)1, +0x2fe31fd5), r23, false);", // IID287 + "__ exorb(r10, Address(r27, +0xa3150de), r10, false);", // IID288 + "__ exorb(r18, Address(r22, r30, (Address::ScaleFactor)3, +0x1ad4e897), r24, true);", // IID289 + "__ exorb(r8, Address(r16, r20, (Address::ScaleFactor)0, +0x626eae82), r8, true);", // IID290 + "__ eaddl(r21, r15, 1048576, false);", // IID291 + "__ eaddl(rax, r18, 1048576, false);", // IID292 + "__ eaddl(r18, r18, 256, false);", // IID293 + "__ eaddl(r13, r19, 16, true);", // IID294 + "__ eaddl(rax, r23, 16, true);", // IID295 + "__ eaddl(r25, r25, 16777216, true);", // IID296 + "__ eandl(r29, r18, 1048576, false);", // IID297 + "__ eandl(rax, r14, 1048576, false);", // IID298 + "__ eandl(r19, r19, 65536, false);", // IID299 + "__ eandl(r27, r25, 1048576, true);", // IID300 + "__ eandl(rax, r20, 1048576, true);", // IID301 + "__ eandl(r28, r28, 16, true);", // IID302 + "__ eimull(r31, r22, 4096, false);", // IID303 +#endif // _LP64 + "__ eimull(rax, rbx, 4096, false);", // IID304 +#ifdef _LP64 + "__ eimull(r24, r24, 1048576, false);", // IID305 + "__ eimull(r21, r16, 65536, true);", // IID306 + "__ eimull(rax, r24, 65536, true);", // IID307 + "__ eimull(r13, r13, 16, true);", // IID308 + "__ eorl(r29, r8, 16777216, false);", // IID309 + "__ eorl(rax, r12, 16777216, false);", // IID310 + "__ eorl(r30, r30, 4096, false);", // IID311 + "__ eorl(r24, rdx, 16, true);", // IID312 + "__ eorl(rax, r8, 16, true);", // IID313 + "__ eorl(r13, r13, 4096, true);", // IID314 + "__ ercll(r25, r13, 1);", // IID315 + "__ ercll(rax, r18, 1);", // IID316 + "__ ercll(r9, r9, 16);", // IID317 + "__ eroll(r26, r25, 8, false);", // IID318 +#endif // _LP64 + "__ eroll(rax, rdx, 8, false);", // IID319 +#ifdef _LP64 + "__ eroll(r24, r24, 16, false);", // IID320 + "__ eroll(r24, rcx, 8, true);", // IID321 + "__ eroll(rax, r30, 8, true);", // IID322 + "__ eroll(r28, r28, 16, true);", // IID323 + "__ erorl(r17, r28, 4, false);", // IID324 +#endif // _LP64 + "__ erorl(rax, rdx, 4, false);", // IID325 +#ifdef _LP64 + "__ erorl(r8, r8, 16, false);", // IID326 + "__ erorl(r19, rdx, 16, true);", // IID327 + "__ erorl(rax, r31, 16, true);", // IID328 + "__ erorl(r22, r22, 8, true);", // IID329 + "__ esall(r23, r25, 16, false);", // IID330 + "__ esall(rax, r14, 16, false);", // IID331 + "__ esall(r31, r31, 8, false);", // IID332 + "__ esall(r30, r24, 2, true);", // IID333 + "__ esall(rax, r29, 2, true);", // IID334 + "__ esall(r8, r8, 2, true);", // IID335 + "__ esarl(r18, r24, 16, false);", // IID336 + "__ esarl(rax, r13, 16, false);", // IID337 + "__ esarl(r24, r24, 1, false);", // IID338 + "__ esarl(r28, r17, 16, true);", // IID339 + "__ esarl(rax, r24, 16, true);", // IID340 + "__ esarl(r17, r17, 4, true);", // IID341 + "__ eshll(r24, rcx, 4, false);", // IID342 + "__ eshll(rax, r16, 4, false);", // IID343 + "__ eshll(r15, r15, 2, false);", // IID344 + "__ eshll(r14, r27, 4, true);", // IID345 + "__ eshll(rax, r23, 4, true);", // IID346 + "__ eshll(r30, r30, 4, true);", // IID347 + "__ eshrl(r27, rdx, 2, false);", // IID348 + "__ eshrl(rax, r19, 2, false);", // IID349 + "__ eshrl(r20, r20, 2, false);", // IID350 + "__ eshrl(r21, r23, 1, true);", // IID351 + "__ eshrl(rax, r30, 1, true);", // IID352 + "__ eshrl(r25, r25, 2, true);", // IID353 + "__ esubl(r24, r19, 1048576, false);", // IID354 + "__ esubl(rax, r14, 1048576, false);", // IID355 + "__ esubl(r22, r22, 268435456, false);", // IID356 + "__ esubl(r24, r24, 65536, true);", // IID357 + "__ esubl(rax, r14, 65536, true);", // IID358 + "__ esubl(r28, r28, 268435456, true);", // IID359 + "__ exorl(rbx, r20, 256, false);", // IID360 + "__ exorl(rax, r15, 256, false);", // IID361 +#endif // _LP64 + "__ exorl(rbx, rbx, 4096, false);", // IID362 +#ifdef _LP64 + "__ exorl(r24, r30, 65536, true);", // IID363 + "__ exorl(rax, r31, 65536, true);", // IID364 + "__ exorl(r31, r31, 4096, true);", // IID365 + "__ esubl_imm32(r20, r10, 1048576, false);", // IID366 + "__ esubl_imm32(rax, r13, 1048576, false);", // IID367 + "__ esubl_imm32(r25, r25, 1048576, false);", // IID368 + "__ esubl_imm32(r23, r12, 1073741824, true);", // IID369 + "__ esubl_imm32(rax, r16, 1073741824, true);", // IID370 + "__ esubl_imm32(r31, r31, 65536, true);", // IID371 + "__ eaddl(r17, r13, Address(r9, +0x7fef2f98), false);", // IID372 + "__ eaddl(r29, r8, Address(r22, -0x4df70aac), true);", // IID373 + "__ eandl(r13, r17, Address(r12, r15, (Address::ScaleFactor)3, +0x50a8a902), false);", // IID374 + "__ eandl(r22, r25, Address(r26, r10, (Address::ScaleFactor)2, +0x70ea2754), true);", // IID375 + "__ eimull(r19, r12, Address(r30, r8, (Address::ScaleFactor)0, +0x6a1a0a73), false);", // IID376 + "__ eimull(r30, r18, Address(r18, r19, (Address::ScaleFactor)2, -0x7fcd28c7), true);", // IID377 + "__ eorl(r16, r31, Address(r25, r11, (Address::ScaleFactor)3, +0x482d5dbc), false);", // IID378 + "__ eorl(r9, r27, Address(r11, +0x43d5ee01), true);", // IID379 + "__ esubl(rcx, r23, Address(r21, r15, (Address::ScaleFactor)2, +0x2825c2bc), false);", // IID380 + "__ esubl(r27, r22, Address(r13, r15, (Address::ScaleFactor)1, +0x771f0da7), true);", // IID381 + "__ exorl(r9, r30, Address(r9, r22, (Address::ScaleFactor)3, -0x4ad6c88e), false);", // IID382 + "__ exorl(r11, r16, Address(rbx, r28, (Address::ScaleFactor)2, +0xb0223ee), true);", // IID383 + "__ exorb(r15, r29, Address(r15, r28, (Address::ScaleFactor)1, -0x1f297a69), false);", // IID384 + "__ exorb(r17, r30, Address(r23, rbx, (Address::ScaleFactor)1, +0xadc7545), true);", // IID385 + "__ exorw(r27, r9, Address(rdx, r22, (Address::ScaleFactor)2, -0x43d90f61), false);", // IID386 + "__ exorw(rbx, r22, Address(r28, r22, (Address::ScaleFactor)0, -0x7d30a0b1), true);", // IID387 + "__ eaddl(r14, r24, rcx, false);", // IID388 + "__ eaddl(r8, r8, r17, false);", // IID389 + "__ eaddl(r26, r24, r12, true);", // IID390 + "__ eaddl(r24, r24, r23, true);", // IID391 + "__ eandl(r13, r26, r31, false);", // IID392 + "__ eandl(r11, r11, r8, false);", // IID393 + "__ eandl(rcx, r19, r15, true);", // IID394 + "__ eandl(r12, r12, r12, true);", // IID395 + "__ eimull(r22, r20, r19, false);", // IID396 + "__ eimull(r8, r8, rdx, false);", // IID397 + "__ eimull(r22, r27, r23, true);", // IID398 + "__ eimull(r9, r9, r18, true);", // IID399 + "__ eorw(rcx, r30, r13, false);", // IID400 + "__ eorw(r28, r28, r19, false);", // IID401 + "__ eorw(r12, r30, r27, true);", // IID402 + "__ eorw(r8, r8, r22, true);", // IID403 + "__ eorl(r16, rcx, r30, false);", // IID404 + "__ eorl(r10, r10, r25, false);", // IID405 + "__ eorl(r15, r17, r17, true);", // IID406 + "__ eorl(r9, r9, r30, true);", // IID407 + "__ eshldl(r20, r21, r8, false);", // IID408 + "__ eshldl(r26, r26, r14, false);", // IID409 + "__ eshldl(r16, rdx, r14, true);", // IID410 + "__ eshldl(r19, r19, r8, true);", // IID411 + "__ eshrdl(r27, rbx, r26, false);", // IID412 + "__ eshrdl(r28, r28, r19, false);", // IID413 + "__ eshrdl(rcx, r11, r14, true);", // IID414 + "__ eshrdl(r31, r31, r19, true);", // IID415 + "__ esubl(r26, r13, r25, false);", // IID416 + "__ esubl(r24, r24, r11, false);", // IID417 + "__ esubl(r18, r20, r13, true);", // IID418 + "__ esubl(r16, r16, r18, true);", // IID419 + "__ exorl(r19, r17, r8, false);", // IID420 + "__ exorl(r19, r19, r13, false);", // IID421 + "__ exorl(r23, r13, r15, true);", // IID422 + "__ exorl(r11, r11, r29, true);", // IID423 + "__ eshldl(r29, r17, r17, 1, false);", // IID424 + "__ eshldl(r22, r22, r24, 4, false);", // IID425 + "__ eshldl(r8, r28, r11, 16, true);", // IID426 + "__ eshldl(r15, r15, r23, 4, true);", // IID427 + "__ eshrdl(r29, r22, r16, 4, false);", // IID428 + "__ eshrdl(r13, r13, r9, 4, false);", // IID429 + "__ eshrdl(r15, r21, r12, 2, true);", // IID430 + "__ eshrdl(r17, r17, r23, 2, true);", // IID431 + "__ ecmovl (Assembler::Condition::overflow, rdx, r16, r29);", // IID432 + "__ ecmovl (Assembler::Condition::overflow, r10, r10, r21);", // IID433 + "__ ecmovl (Assembler::Condition::noOverflow, r17, r29, r18);", // IID434 + "__ ecmovl (Assembler::Condition::noOverflow, r28, r28, r24);", // IID435 + "__ ecmovl (Assembler::Condition::below, r10, r20, r27);", // IID436 + "__ ecmovl (Assembler::Condition::below, r10, r10, r14);", // IID437 + "__ ecmovl (Assembler::Condition::aboveEqual, r11, r27, rcx);", // IID438 + "__ ecmovl (Assembler::Condition::aboveEqual, r22, r22, r15);", // IID439 + "__ ecmovl (Assembler::Condition::zero, r31, r30, r19);", // IID440 + "__ ecmovl (Assembler::Condition::zero, r19, r19, r26);", // IID441 + "__ ecmovl (Assembler::Condition::notZero, r21, r14, r26);", // IID442 + "__ ecmovl (Assembler::Condition::notZero, r20, r20, r15);", // IID443 + "__ ecmovl (Assembler::Condition::belowEqual, r12, r13, r23);", // IID444 + "__ ecmovl (Assembler::Condition::belowEqual, r28, r28, r20);", // IID445 + "__ ecmovl (Assembler::Condition::above, r20, r24, r11);", // IID446 + "__ ecmovl (Assembler::Condition::above, r10, r10, r15);", // IID447 + "__ ecmovl (Assembler::Condition::negative, r19, r20, r23);", // IID448 + "__ ecmovl (Assembler::Condition::negative, r15, r15, r26);", // IID449 + "__ ecmovl (Assembler::Condition::positive, r19, r24, r23);", // IID450 + "__ ecmovl (Assembler::Condition::positive, r28, r28, r11);", // IID451 + "__ ecmovl (Assembler::Condition::parity, r13, r13, rdx);", // IID452 + "__ ecmovl (Assembler::Condition::parity, r31, r31, r23);", // IID453 + "__ ecmovl (Assembler::Condition::noParity, r23, r9, r27);", // IID454 + "__ ecmovl (Assembler::Condition::noParity, r21, r21, r20);", // IID455 + "__ ecmovl (Assembler::Condition::less, r24, r21, r29);", // IID456 + "__ ecmovl (Assembler::Condition::less, rbx, rbx, r11);", // IID457 + "__ ecmovl (Assembler::Condition::greaterEqual, r21, rbx, rcx);", // IID458 + "__ ecmovl (Assembler::Condition::greaterEqual, r31, r31, r21);", // IID459 + "__ ecmovl (Assembler::Condition::lessEqual, r15, r25, r30);", // IID460 + "__ ecmovl (Assembler::Condition::lessEqual, r23, r23, r25);", // IID461 + "__ ecmovl (Assembler::Condition::greater, r18, rcx, r10);", // IID462 + "__ ecmovl (Assembler::Condition::greater, rcx, rcx, r31);", // IID463 + "__ ecmovl (Assembler::Condition::overflow, r21, r19, Address(r26, -0x6e290873));", // IID464 + "__ ecmovl (Assembler::Condition::noOverflow, r24, r19, Address(r22, rcx, (Address::ScaleFactor)0, +0x11f85f9a));", // IID465 + "__ ecmovl (Assembler::Condition::below, r17, r24, Address(r20, +0x534d775e));", // IID466 + "__ ecmovl (Assembler::Condition::aboveEqual, r20, r18, Address(r20, -0x47c94ecd));", // IID467 + "__ ecmovl (Assembler::Condition::zero, r9, r13, Address(r23, -0x4b83c563));", // IID468 + "__ ecmovl (Assembler::Condition::notZero, r11, r25, Address(r24, r14, (Address::ScaleFactor)1, -0x446507af));", // IID469 + "__ ecmovl (Assembler::Condition::belowEqual, r14, r24, Address(r30, r13, (Address::ScaleFactor)2, +0xd0661d));", // IID470 + "__ ecmovl (Assembler::Condition::above, r13, r25, Address(r14, r27, (Address::ScaleFactor)3, +0x47e1403));", // IID471 + "__ ecmovl (Assembler::Condition::negative, r24, r19, Address(rcx, rdx, (Address::ScaleFactor)3, -0x644a5318));", // IID472 + "__ ecmovl (Assembler::Condition::positive, r26, r24, Address(r22, r22, (Address::ScaleFactor)0, +0x70352446));", // IID473 + "__ ecmovl (Assembler::Condition::parity, r19, r26, Address(r8, r30, (Address::ScaleFactor)2, +0x78a12f5c));", // IID474 + "__ ecmovl (Assembler::Condition::noParity, r29, r11, Address(r25, r20, (Address::ScaleFactor)0, +0x27a8303a));", // IID475 + "__ ecmovl (Assembler::Condition::less, r22, r24, Address(r27, r16, (Address::ScaleFactor)1, +0x2541a10));", // IID476 + "__ ecmovl (Assembler::Condition::greaterEqual, r31, r15, Address(r8, r16, (Address::ScaleFactor)3, +0x558e3251));", // IID477 + "__ ecmovl (Assembler::Condition::lessEqual, r27, r18, Address(r8, r10, (Address::ScaleFactor)0, -0x471987b7));", // IID478 + "__ ecmovl (Assembler::Condition::greater, r18, r16, Address(r18, r19, (Address::ScaleFactor)2, -0x120ae81e));", // IID479 + "__ adcq(rbx, r31);", // IID480 + "__ cmpq(r30, r31);", // IID481 + "__ imulq(r29, r28);", // IID482 + "__ popcntq(r25, r10);", // IID483 + "__ sbbq(r24, r20);", // IID484 + "__ subq(r16, rdx);", // IID485 + "__ tzcntq(r26, r28);", // IID486 + "__ lzcntq(r28, r9);", // IID487 + "__ addq(r20, r24);", // IID488 + "__ andq(r24, r29);", // IID489 + "__ orq(r23, r27);", // IID490 + "__ xorq(r15, r12);", // IID491 + "__ movq(r18, r19);", // IID492 + "__ bsfq(r31, rcx);", // IID493 + "__ bsrq(r9, r13);", // IID494 + "__ btq(r20, rcx);", // IID495 + "__ xchgq(r8, r21);", // IID496 + "__ testq(r24, r14);", // IID497 + "__ addq(Address(rcx, r23, (Address::ScaleFactor)2, +0x4ff06c4d), r29);", // IID498 + "__ andq(Address(r24, r10, (Address::ScaleFactor)1, -0x75d9a189), r26);", // IID499 + "__ cmpq(Address(rbx, rbx, (Address::ScaleFactor)0, +0x4033d59c), r17);", // IID500 + "__ orq(Address(r22, r12, (Address::ScaleFactor)3, -0x3893347d), r18);", // IID501 + "__ xorq(Address(r20, r23, (Address::ScaleFactor)3, +0x4b311560), r12);", // IID502 + "__ subq(Address(r10, r28, (Address::ScaleFactor)2, +0x5c3a2657), r29);", // IID503 + "__ movq(Address(r13, r25, (Address::ScaleFactor)3, +0x1a3d6f3f), r22);", // IID504 + "__ xaddq(Address(r17, r24, (Address::ScaleFactor)3, -0x35addbd8), r25);", // IID505 + "__ andq(Address(r25, +0x632184c3), 16777216);", // IID506 + "__ addq(Address(r13, r13, (Address::ScaleFactor)0, -0x3972eac6), 16777216);", // IID507 + "__ cmpq(Address(r9, -0x13b4c806), 4096);", // IID508 + "__ sarq(Address(r31, +0x4fa7f551), 1);", // IID509 + "__ salq(Address(r21, r31, (Address::ScaleFactor)2, +0x31aa8232), 1);", // IID510 + "__ sbbq(Address(r24, r31, (Address::ScaleFactor)2, -0x466538b7), 268435456);", // IID511 + "__ shrq(Address(r28, r22, (Address::ScaleFactor)0, -0x3efe85b1), 2);", // IID512 + "__ subq(Address(r16, -0x1389a3eb), 1048576);", // IID513 + "__ xorq(Address(r29, r8, (Address::ScaleFactor)0, +0x1d022615), 16);", // IID514 + "__ orq(Address(r12, r28, (Address::ScaleFactor)1, -0x34c898e2), 1);", // IID515 + "__ movq(Address(rcx, r24, (Address::ScaleFactor)2, -0x1644eb08), 256);", // IID516 + "__ testq(Address(r29, -0x7d23890b), -65536);", // IID517 + "__ addq(r23, Address(rcx, r19, (Address::ScaleFactor)2, +0x70eac654));", // IID518 + "__ andq(rdx, Address(r24, r15, (Address::ScaleFactor)0, -0x204ddaa9));", // IID519 + "__ cmpq(rdx, Address(r23, r11, (Address::ScaleFactor)3, +0x32c930bd));", // IID520 + "__ lzcntq(r28, Address(rdx, -0x5433c28f));", // IID521 + "__ orq(r22, Address(r19, r14, (Address::ScaleFactor)1, -0x2cc67d38));", // IID522 + "__ adcq(r10, Address(r10, +0x3d7c59f));", // IID523 + "__ imulq(r10, Address(r8, r8, (Address::ScaleFactor)3, -0xe61862d));", // IID524 + "__ popcntq(r23, Address(r29, -0x777ed96d));", // IID525 + "__ sbbq(rcx, Address(rbx, r19, (Address::ScaleFactor)1, +0x53c601cb));", // IID526 + "__ subq(r14, Address(r17, rbx, (Address::ScaleFactor)0, -0x768bf073));", // IID527 + "__ tzcntq(r29, Address(r10, r19, (Address::ScaleFactor)1, +0x30c98d3c));", // IID528 + "__ xorq(r10, Address(r16, r27, (Address::ScaleFactor)0, -0x3d08d602));", // IID529 + "__ movq(r18, Address(r28, r28, (Address::ScaleFactor)3, -0x62fbac91));", // IID530 + "__ leaq(rbx, Address(rcx, +0x450602a5));", // IID531 + "__ cvttsd2siq(r12, Address(r30, r31, (Address::ScaleFactor)0, -0x6798a630));", // IID532 + "__ xchgq(r31, Address(r24, r10, (Address::ScaleFactor)1, -0x706712ed));", // IID533 + "__ testq(r14, Address(r13, r20, (Address::ScaleFactor)3, +0x171081f2));", // IID534 + "__ addq(r31, 16);", // IID535 + "__ andq(r25, 16);", // IID536 + "__ adcq(r23, 256);", // IID537 + "__ cmpq(r19, 268435456);", // IID538 + "__ rclq(r31, 1);", // IID539 + "__ rcrq(r17, 1);", // IID540 + "__ rolq(r25, 2);", // IID541 + "__ rorq(r17, 4);", // IID542 + "__ sarq(r28, 1);", // IID543 + "__ salq(r15, 4);", // IID544 + "__ sbbq(rbx, 65536);", // IID545 + "__ shlq(r21, 1);", // IID546 + "__ shrq(r10, 1);", // IID547 + "__ subq(r14, 16);", // IID548 + "__ xorq(r18, 268435456);", // IID549 + "__ movq(r23, 16);", // IID550 + "__ mov64(r12, 1099511627776);", // IID551 + "__ btq(r14, 4);", // IID552 + "__ testq(r24, -4096);", // IID553 + "__ orq_imm32(r19, 1048576);", // IID554 + "__ subq_imm32(rcx, 268435456);", // IID555 + "__ cmovq(Assembler::Condition::overflow, rdx, Address(r19, rbx, (Address::ScaleFactor)3, +0x211c8c4));", // IID556 + "__ cmovq(Assembler::Condition::noOverflow, rbx, Address(r21, +0x49267743));", // IID557 + "__ cmovq(Assembler::Condition::below, r21, Address(r8, r28, (Address::ScaleFactor)1, -0x4c8c2946));", // IID558 + "__ cmovq(Assembler::Condition::aboveEqual, r12, Address(r26, r20, (Address::ScaleFactor)0, -0x264df89c));", // IID559 + "__ cmovq(Assembler::Condition::zero, r17, Address(r28, r9, (Address::ScaleFactor)2, +0x3497196b));", // IID560 + "__ cmovq(Assembler::Condition::notZero, r13, Address(r15, r23, (Address::ScaleFactor)1, -0x27a30999));", // IID561 + "__ cmovq(Assembler::Condition::belowEqual, r22, Address(r22, +0xf39ab05));", // IID562 + "__ cmovq(Assembler::Condition::above, rcx, Address(r22, r26, (Address::ScaleFactor)3, -0x48c954c));", // IID563 + "__ cmovq(Assembler::Condition::negative, r25, Address(r19, r21, (Address::ScaleFactor)0, +0xe405b0b));", // IID564 + "__ cmovq(Assembler::Condition::positive, r12, Address(r19, r29, (Address::ScaleFactor)3, -0x7762044b));", // IID565 + "__ cmovq(Assembler::Condition::parity, rbx, Address(r30, r10, (Address::ScaleFactor)1, -0x19798323));", // IID566 + "__ cmovq(Assembler::Condition::noParity, r21, Address(r24, r31, (Address::ScaleFactor)0, -0x5731652b));", // IID567 + "__ cmovq(Assembler::Condition::less, r18, Address(r8, r10, (Address::ScaleFactor)1, -0x5613be89));", // IID568 + "__ cmovq(Assembler::Condition::greaterEqual, r28, Address(r21, r21, (Address::ScaleFactor)3, +0x65a0fdc4));", // IID569 + "__ cmovq(Assembler::Condition::lessEqual, r23, Address(r11, r18, (Address::ScaleFactor)0, -0x1d1af10c));", // IID570 + "__ cmovq(Assembler::Condition::greater, r22, Address(r18, r12, (Address::ScaleFactor)1, +0x1a5f1c38));", // IID571 + "__ call(r23);", // IID572 + "__ divq(r30);", // IID573 + "__ idivq(r19);", // IID574 + "__ imulq(r9);", // IID575 + "__ mulq(r13);", // IID576 + "__ negq(r16);", // IID577 + "__ notq(r29);", // IID578 + "__ rolq(rcx);", // IID579 + "__ rorq(r25);", // IID580 + "__ sarq(r8);", // IID581 + "__ salq(r27);", // IID582 + "__ shlq(r30);", // IID583 + "__ shrq(r23);", // IID584 + "__ incrementq(rbx);", // IID585 + "__ decrementq(r14);", // IID586 + "__ pushp(r21);", // IID587 + "__ popp(r21);", // IID588 + "__ call(Address(r20, r21, (Address::ScaleFactor)1, +0x56c6af2f));", // IID589 + "__ mulq(Address(r31, r19, (Address::ScaleFactor)3, -0x1b4eb23));", // IID590 + "__ negq(Address(r27, r27, (Address::ScaleFactor)0, -0x58dbfc1f));", // IID591 + "__ sarq(Address(rbx, r22, (Address::ScaleFactor)2, -0x606349d1));", // IID592 + "__ salq(Address(r26, r23, (Address::ScaleFactor)3, +0xb95a079));", // IID593 + "__ shrq(Address(r14, r26, (Address::ScaleFactor)0, +0x3544e09));", // IID594 + "__ incrementq(Address(r27, rdx, (Address::ScaleFactor)0, +0x120b3250));", // IID595 + "__ decrementq(Address(r9, r25, (Address::ScaleFactor)2, -0x34aaeccb));", // IID596 + "__ imulq(r20, Address(r16, r28, (Address::ScaleFactor)1, -0x59de05a5), 1048576);", // IID597 + "__ imulq(r17, r23, 256);", // IID598 + "__ shldq(r19, r11, 8);", // IID599 + "__ shrdq(r28, r10, 8);", // IID600 + "__ pop2(r29, r26);", // IID601 + "__ pop2p(r22, r10);", // IID602 + "__ push2(r25, r30);", // IID603 + "__ push2p(r28, r15);", // IID604 + "__ movzbq(r11, Address(r29, r19, (Address::ScaleFactor)2, -0x12368d34));", // IID605 + "__ movzwq(r14, Address(r8, r30, (Address::ScaleFactor)2, -0x4a9392de));", // IID606 + "__ movsbq(r28, Address(r23, r15, (Address::ScaleFactor)0, +0x6189cb54));", // IID607 + "__ movswq(r28, Address(rbx, r23, (Address::ScaleFactor)3, -0x2de86561));", // IID608 + "__ movzbq(r11, rcx);", // IID609 + "__ movzwq(r30, r15);", // IID610 + "__ movsbq(r14, rcx);", // IID611 + "__ movswq(r23, r9);", // IID612 + "__ cmpxchgq(r12, Address(r13, r10, (Address::ScaleFactor)1, -0x7c62c3a));", // IID613 + "__ eidivq(rcx, false);", // IID614 + "__ eidivq(r15, true);", // IID615 + "__ edivq(r23, false);", // IID616 + "__ edivq(r24, true);", // IID617 + "__ eimulq(r27, false);", // IID618 + "__ eimulq(r30, true);", // IID619 + "__ emulq(r12, false);", // IID620 + "__ emulq(rcx, true);", // IID621 + "__ emulq(Address(r13, r9, (Address::ScaleFactor)3, -0x226aab94), false);", // IID622 + "__ emulq(Address(r13, r24, (Address::ScaleFactor)3, -0x286c7605), true);", // IID623 + "__ eimulq(r21, r30, false);", // IID624 + "__ eimulq(r17, r17, false);", // IID625 + "__ eimulq(r29, r12, true);", // IID626 + "__ eimulq(r30, r30, true);", // IID627 + "__ elzcntq(r24, r15, false);", // IID628 + "__ elzcntq(r25, r25, false);", // IID629 + "__ elzcntq(r25, r21, true);", // IID630 + "__ elzcntq(r22, r22, true);", // IID631 + "__ enegq(r17, r30, false);", // IID632 + "__ enegq(r17, r17, false);", // IID633 + "__ enegq(r31, r17, true);", // IID634 + "__ enegq(r29, r29, true);", // IID635 + "__ enotq(r10, r9);", // IID636 + "__ enotq(r24, r24);", // IID637 + "__ epopcntq(r28, r15, false);", // IID638 + "__ epopcntq(r10, r10, false);", // IID639 + "__ epopcntq(r27, r30, true);", // IID640 + "__ epopcntq(r28, r28, true);", // IID641 + "__ erolq(r28, r14, false);", // IID642 + "__ erolq(r23, r23, false);", // IID643 + "__ erolq(r23, r24, true);", // IID644 + "__ erolq(r21, r21, true);", // IID645 + "__ erorq(r31, r22, false);", // IID646 + "__ erorq(r28, r28, false);", // IID647 + "__ erorq(r17, r10, true);", // IID648 + "__ erorq(r9, r9, true);", // IID649 + "__ esalq(r29, r30, false);", // IID650 + "__ esalq(r11, r11, false);", // IID651 + "__ esalq(r26, r11, true);", // IID652 + "__ esalq(r16, r16, true);", // IID653 + "__ esarq(rbx, r15, false);", // IID654 + "__ esarq(r14, r14, false);", // IID655 + "__ esarq(r25, r16, true);", // IID656 + "__ esarq(r8, r8, true);", // IID657 + "__ edecq(r11, r13, false);", // IID658 + "__ edecq(rcx, rcx, false);", // IID659 + "__ edecq(r21, r18, true);", // IID660 + "__ edecq(r28, r28, true);", // IID661 + "__ eincq(r16, r16, false);", // IID662 + "__ eincq(r29, r29, false);", // IID663 + "__ eincq(r18, r9, true);", // IID664 + "__ eincq(r19, r19, true);", // IID665 + "__ eshlq(r19, r18, false);", // IID666 + "__ eshlq(r8, r8, false);", // IID667 + "__ eshlq(r12, r15, true);", // IID668 + "__ eshlq(r29, r29, true);", // IID669 + "__ eshrq(r28, r24, false);", // IID670 + "__ eshrq(r19, r19, false);", // IID671 + "__ eshrq(r8, r28, true);", // IID672 + "__ eshrq(r17, r17, true);", // IID673 + "__ etzcntq(r28, r16, false);", // IID674 + "__ etzcntq(r14, r14, false);", // IID675 + "__ etzcntq(r12, r31, true);", // IID676 + "__ etzcntq(r14, r14, true);", // IID677 + "__ eimulq(r31, Address(r13, -0x69c4b352), false);", // IID678 + "__ eimulq(r17, Address(r18, -0x60ab1105), true);", // IID679 + "__ elzcntq(r27, Address(r14, r25, (Address::ScaleFactor)2, +0x2798bf83), false);", // IID680 + "__ elzcntq(r23, Address(r10, r11, (Address::ScaleFactor)0, -0x378e635d), true);", // IID681 + "__ enegq(rcx, Address(r19, r9, (Address::ScaleFactor)3, -0x6847d440), false);", // IID682 + "__ enegq(rcx, Address(rbx, rcx, (Address::ScaleFactor)0, +0x6f92d38d), true);", // IID683 + "__ epopcntq(r20, Address(r12, -0x2a8b27d6), false);", // IID684 + "__ epopcntq(r31, Address(r30, +0x4603f6d0), true);", // IID685 + "__ esalq(rbx, Address(r24, +0x567d06f9), false);", // IID686 + "__ esalq(r12, Address(r24, r28, (Address::ScaleFactor)0, -0x1c4c584e), true);", // IID687 + "__ esarq(r12, Address(r23, r24, (Address::ScaleFactor)2, -0x3157bcba), false);", // IID688 + "__ esarq(r8, Address(r14, r24, (Address::ScaleFactor)2, -0x714290a5), true);", // IID689 + "__ edecq(r23, Address(r8, r15, (Address::ScaleFactor)1, -0x5ae272dd), false);", // IID690 + "__ edecq(r13, Address(r29, r9, (Address::ScaleFactor)3, -0x5b5174a9), true);", // IID691 + "__ eincq(r11, Address(r21, r31, (Address::ScaleFactor)3, -0x2176b4dc), false);", // IID692 + "__ eincq(r13, Address(rcx, r16, (Address::ScaleFactor)0, -0x36b448c9), true);", // IID693 + "__ eshrq(r26, Address(r25, rcx, (Address::ScaleFactor)2, -0x5f894993), false);", // IID694 + "__ eshrq(r25, Address(r9, +0x51798d21), true);", // IID695 + "__ etzcntq(r28, Address(r13, r26, (Address::ScaleFactor)2, +0x207196f6), false);", // IID696 + "__ etzcntq(rbx, Address(r19, r13, (Address::ScaleFactor)0, -0x24d937d5), true);", // IID697 + "__ eaddq(r17, Address(r30, +0x3935ccff), r31, false);", // IID698 + "__ eaddq(r14, Address(r27, r10, (Address::ScaleFactor)2, -0x34ad9bab), r14, false);", // IID699 + "__ eaddq(r18, Address(r20, r23, (Address::ScaleFactor)0, +0x5ad3ed4b), r30, true);", // IID700 + "__ eaddq(r20, Address(rdx, -0x322a99e5), r20, true);", // IID701 + "__ eandq(r31, Address(rbx, r27, (Address::ScaleFactor)3, +0x4ce247d2), r17, false);", // IID702 + "__ eandq(r30, Address(r18, r19, (Address::ScaleFactor)1, -0x4ee3d14), r30, false);", // IID703 + "__ eandq(r28, Address(r11, rbx, (Address::ScaleFactor)3, -0x28994bbf), r24, true);", // IID704 + "__ eandq(r30, Address(r22, +0x7d21c24), r30, true);", // IID705 + "__ eorq(r26, Address(r15, r19, (Address::ScaleFactor)3, +0x58c21792), r20, false);", // IID706 + "__ eorq(r13, Address(r10, r27, (Address::ScaleFactor)2, -0x2c70d333), r13, false);", // IID707 + "__ eorq(rbx, Address(r12, rbx, (Address::ScaleFactor)0, -0x1fb0f1bc), r26, true);", // IID708 + "__ eorq(r31, Address(r27, r31, (Address::ScaleFactor)1, +0x28d1756), r31, true);", // IID709 + "__ esubq(r24, Address(r28, r23, (Address::ScaleFactor)1, +0x6980f610), r27, false);", // IID710 + "__ esubq(r15, Address(r11, r30, (Address::ScaleFactor)3, -0x49777e7), r15, false);", // IID711 + "__ esubq(r17, Address(r25, r13, (Address::ScaleFactor)2, +0x31619e46), r31, true);", // IID712 + "__ esubq(r18, Address(r11, r10, (Address::ScaleFactor)2, +0x1922861a), r18, true);", // IID713 + "__ exorq(rbx, Address(r11, -0x4716d420), r21, false);", // IID714 + "__ exorq(r8, Address(rdx, r9, (Address::ScaleFactor)2, -0x4cfe39c), r8, false);", // IID715 + "__ exorq(r16, Address(r14, r27, (Address::ScaleFactor)0, +0x7c6654d9), r25, true);", // IID716 + "__ exorq(r29, Address(r15, -0x5efab479), r29, true);", // IID717 + "__ eaddq(r19, Address(r13, r22, (Address::ScaleFactor)2, +0x68b64559), 16777216, false);", // IID718 + "__ eaddq(r16, Address(r13, r31, (Address::ScaleFactor)3, -0x65143af5), 1, true);", // IID719 + "__ eandq(r31, Address(r24, r13, (Address::ScaleFactor)1, -0x25b16a0e), 1, false);", // IID720 + "__ eandq(r11, Address(r28, -0xf6d4b26), 65536, true);", // IID721 + "__ eimulq(rcx, Address(r18, r10, (Address::ScaleFactor)0, +0x46ec6da1), 16777216, false);", // IID722 + "__ eimulq(r15, Address(r9, r10, (Address::ScaleFactor)3, -0x7fc36af3), 16, true);", // IID723 + "__ eorq(r17, Address(r27, r30, (Address::ScaleFactor)0, +0x1b4cda2c), 1, false);", // IID724 + "__ eorq(rdx, Address(r25, r14, (Address::ScaleFactor)2, -0x59aa6b85), 4096, true);", // IID725 + "__ esalq(r17, Address(r26, r21, (Address::ScaleFactor)1, -0x6ab1f15f), 8, false);", // IID726 + "__ esalq(r12, Address(r22, r17, (Address::ScaleFactor)0, -0x43ac14ab), 2, true);", // IID727 + "__ esarq(r29, Address(r18, r16, (Address::ScaleFactor)0, -0x59dc0c61), 4, false);", // IID728 + "__ esarq(r16, Address(r11, -0x7bdd314), 4, true);", // IID729 + "__ eshrq(r26, Address(r23, r27, (Address::ScaleFactor)3, -0x55b92314), 16, false);", // IID730 + "__ eshrq(r23, Address(r16, r29, (Address::ScaleFactor)1, +0x71311a1d), 2, true);", // IID731 + "__ esubq(r25, Address(r9, -0x9532bac), 1048576, false);", // IID732 + "__ esubq(r17, Address(r8, r23, (Address::ScaleFactor)0, +0x55d06ca2), 1048576, true);", // IID733 + "__ exorq(r29, Address(r9, r24, (Address::ScaleFactor)0, -0x2c141c1), 1048576, false);", // IID734 + "__ exorq(r28, Address(r22, r19, (Address::ScaleFactor)1, -0x2d9d9abd), 16, true);", // IID735 + "__ eaddq(r22, r14, 16, false);", // IID736 + "__ eaddq(rax, r12, 16, false);", // IID737 + "__ eaddq(r24, r24, 65536, false);", // IID738 + "__ eaddq(r21, rbx, 65536, true);", // IID739 + "__ eaddq(rax, rbx, 65536, true);", // IID740 + "__ eaddq(r24, r24, 65536, true);", // IID741 + "__ eandq(r21, r27, 16777216, false);", // IID742 + "__ eandq(rax, r27, 16777216, false);", // IID743 + "__ eandq(r24, r24, 65536, false);", // IID744 + "__ eandq(r13, r31, 1048576, true);", // IID745 + "__ eandq(rax, r21, 1048576, true);", // IID746 + "__ eandq(r30, r30, 1048576, true);", // IID747 + "__ eimulq(r8, r13, 268435456, false);", // IID748 + "__ eimulq(rax, r31, 268435456, false);", // IID749 + "__ eimulq(r13, r13, 65536, false);", // IID750 + "__ eimulq(r14, r29, 1048576, true);", // IID751 + "__ eimulq(rax, r22, 1048576, true);", // IID752 + "__ eimulq(r8, r8, 268435456, true);", // IID753 + "__ eorq(r30, r15, 4096, false);", // IID754 + "__ eorq(rax, r28, 4096, false);", // IID755 + "__ eorq(r26, r26, 1048576, false);", // IID756 + "__ eorq(r16, r12, 268435456, true);", // IID757 + "__ eorq(rax, r9, 268435456, true);", // IID758 + "__ eorq(r23, r23, 256, true);", // IID759 + "__ erclq(r15, r9, 16);", // IID760 + "__ erclq(rax, r8, 16);", // IID761 + "__ erclq(r25, r25, 1);", // IID762 + "__ erolq(r9, r17, 16, false);", // IID763 + "__ erolq(rax, r20, 16, false);", // IID764 + "__ erolq(r27, r27, 1, false);", // IID765 + "__ erolq(r20, r31, 1, true);", // IID766 + "__ erolq(rax, r18, 1, true);", // IID767 + "__ erolq(r28, r28, 16, true);", // IID768 + "__ erorq(r26, r18, 16, false);", // IID769 + "__ erorq(rax, r24, 16, false);", // IID770 + "__ erorq(r22, r22, 16, false);", // IID771 + "__ erorq(r27, r29, 1, true);", // IID772 + "__ erorq(rax, r18, 1, true);", // IID773 + "__ erorq(r21, r21, 1, true);", // IID774 + "__ esalq(r12, rcx, 2, false);", // IID775 + "__ esalq(rax, r24, 2, false);", // IID776 + "__ esalq(r22, r22, 8, false);", // IID777 + "__ esalq(r17, r23, 8, true);", // IID778 + "__ esalq(rax, r27, 8, true);", // IID779 + "__ esalq(r23, r23, 1, true);", // IID780 + "__ esarq(r8, r25, 16, false);", // IID781 + "__ esarq(rax, r23, 16, false);", // IID782 + "__ esarq(r9, r9, 4, false);", // IID783 + "__ esarq(r22, r13, 1, true);", // IID784 + "__ esarq(rax, r11, 1, true);", // IID785 + "__ esarq(r12, r12, 2, true);", // IID786 + "__ eshlq(rcx, r30, 8, false);", // IID787 + "__ eshlq(rax, r19, 8, false);", // IID788 + "__ eshlq(r13, r13, 2, false);", // IID789 + "__ eshlq(r18, r11, 8, true);", // IID790 + "__ eshlq(rax, r9, 8, true);", // IID791 + "__ eshlq(rcx, rcx, 16, true);", // IID792 + "__ eshrq(r10, r22, 4, false);", // IID793 + "__ eshrq(rax, r9, 4, false);", // IID794 + "__ eshrq(r12, r12, 2, false);", // IID795 + "__ eshrq(r26, r31, 8, true);", // IID796 + "__ eshrq(rax, r12, 8, true);", // IID797 + "__ eshrq(r28, r28, 1, true);", // IID798 + "__ esubq(r15, r30, 65536, false);", // IID799 + "__ esubq(rax, rcx, 65536, false);", // IID800 + "__ esubq(r26, r26, 16, false);", // IID801 + "__ esubq(r12, r14, 1, true);", // IID802 + "__ esubq(rax, r21, 1, true);", // IID803 + "__ esubq(r20, r20, 1048576, true);", // IID804 + "__ exorq(r11, rbx, 16777216, false);", // IID805 + "__ exorq(rax, r23, 16777216, false);", // IID806 + "__ exorq(r31, r31, 268435456, false);", // IID807 + "__ exorq(r29, r28, 4096, true);", // IID808 + "__ exorq(rax, r19, 4096, true);", // IID809 + "__ exorq(rdx, rdx, 268435456, true);", // IID810 + "__ eorq_imm32(rdx, rdx, 1048576, false);", // IID811 + "__ eorq_imm32(rax, r22, 1048576, false);", // IID812 + "__ eorq_imm32(r29, r29, 1048576, false);", // IID813 + "__ eorq_imm32(r17, rcx, 4194304, false);", // IID814 + "__ eorq_imm32(rax, r25, 4194304, false);", // IID815 + "__ eorq_imm32(r27, r27, 1073741824, false);", // IID816 + "__ esubq_imm32(r16, r19, 4194304, false);", // IID817 + "__ esubq_imm32(rax, r31, 4194304, false);", // IID818 + "__ esubq_imm32(r26, r26, 262144, false);", // IID819 + "__ esubq_imm32(r17, r22, 1073741824, true);", // IID820 + "__ esubq_imm32(rax, r18, 1073741824, true);", // IID821 + "__ esubq_imm32(r23, r23, 268435456, true);", // IID822 + "__ eaddq(r13, r30, Address(r24, r19, (Address::ScaleFactor)1, +0x56ea3a3b), false);", // IID823 + "__ eaddq(r29, r15, Address(r26, r27, (Address::ScaleFactor)3, -0x4b113958), true);", // IID824 + "__ eandq(r12, r30, Address(r31, -0x46103c74), false);", // IID825 + "__ eandq(r27, r10, Address(r22, r25, (Address::ScaleFactor)1, +0x6a1ebee5), true);", // IID826 + "__ eorq(r30, r26, Address(r11, r18, (Address::ScaleFactor)2, -0x2b9fff29), false);", // IID827 + "__ eorq(r9, r12, Address(r18, r17, (Address::ScaleFactor)0, +0xb4859f6), true);", // IID828 + "__ eimulq(rdx, r17, Address(r24, rdx, (Address::ScaleFactor)2, +0x3d284cd8), false);", // IID829 + "__ eimulq(r29, r26, Address(r30, r12, (Address::ScaleFactor)1, +0x6e813124), true);", // IID830 + "__ esubq(rbx, r13, Address(r22, -0x702a289e), false);", // IID831 + "__ esubq(r23, r29, Address(r25, rdx, (Address::ScaleFactor)0, -0x6252a7ed), true);", // IID832 + "__ exorq(r8, r18, Address(r19, r14, (Address::ScaleFactor)2, -0xebfa697), false);", // IID833 + "__ exorq(r10, r28, Address(r26, +0x168381ca), true);", // IID834 + "__ eaddq(rcx, r18, r8, false);", // IID835 + "__ eaddq(rcx, rcx, r14, false);", // IID836 + "__ eaddq(r23, r10, r16, true);", // IID837 + "__ eaddq(r11, r11, r24, true);", // IID838 + "__ eadcxq(r9, r18, rdx);", // IID839 + "__ eadcxq(r8, r8, r15);", // IID840 + "__ eadoxq(r15, r22, r26);", // IID841 + "__ eadoxq(r11, r11, rdx);", // IID842 + "__ eandq(r19, rdx, r22, false);", // IID843 + "__ eandq(r29, r29, r17, false);", // IID844 + "__ eandq(r23, r27, r15, true);", // IID845 + "__ eandq(r9, r9, r13, true);", // IID846 + "__ eimulq(r18, r15, r16, false);", // IID847 + "__ eimulq(rcx, rcx, r17, false);", // IID848 + "__ eimulq(r23, r12, r20, true);", // IID849 + "__ eimulq(r10, r10, r9, true);", // IID850 + "__ eorq(rdx, r19, r14, false);", // IID851 + "__ eorq(rcx, rcx, r13, false);", // IID852 + "__ eorq(r9, r25, r29, true);", // IID853 + "__ eorq(rdx, rdx, r25, true);", // IID854 + "__ esubq(r23, r8, r16, false);", // IID855 + "__ esubq(r13, r13, r13, false);", // IID856 + "__ esubq(r19, r12, r15, true);", // IID857 + "__ esubq(r9, r9, rdx, true);", // IID858 + "__ exorq(r13, r16, r31, false);", // IID859 + "__ exorq(r17, r17, r30, false);", // IID860 + "__ exorq(r19, r30, r20, true);", // IID861 + "__ exorq(r31, r31, r13, true);", // IID862 + "__ eshldq(r22, r10, r13, 4, false);", // IID863 + "__ eshldq(r24, r24, r21, 16, false);", // IID864 + "__ eshldq(r20, r13, r27, 16, true);", // IID865 + "__ eshldq(r31, r31, r19, 2, true);", // IID866 + "__ eshrdq(r30, r20, r11, 8, false);", // IID867 + "__ eshrdq(rdx, rdx, r15, 1, false);", // IID868 + "__ eshrdq(r28, r30, r14, 2, true);", // IID869 + "__ eshrdq(r20, r20, r16, 1, true);", // IID870 + "__ ecmovq (Assembler::Condition::overflow, r21, r17, r28);", // IID871 + "__ ecmovq (Assembler::Condition::overflow, r15, r15, r30);", // IID872 + "__ ecmovq (Assembler::Condition::noOverflow, rcx, r15, r15);", // IID873 + "__ ecmovq (Assembler::Condition::noOverflow, rcx, rcx, r13);", // IID874 + "__ ecmovq (Assembler::Condition::below, rdx, r26, r26);", // IID875 + "__ ecmovq (Assembler::Condition::below, r28, r28, r15);", // IID876 + "__ ecmovq (Assembler::Condition::aboveEqual, r8, rdx, rcx);", // IID877 + "__ ecmovq (Assembler::Condition::aboveEqual, rcx, rcx, rcx);", // IID878 + "__ ecmovq (Assembler::Condition::zero, r10, r13, r9);", // IID879 + "__ ecmovq (Assembler::Condition::zero, r14, r14, r27);", // IID880 + "__ ecmovq (Assembler::Condition::notZero, r11, r23, r9);", // IID881 + "__ ecmovq (Assembler::Condition::notZero, r11, r11, rdx);", // IID882 + "__ ecmovq (Assembler::Condition::belowEqual, r31, r14, r25);", // IID883 + "__ ecmovq (Assembler::Condition::belowEqual, r20, r20, r12);", // IID884 + "__ ecmovq (Assembler::Condition::above, rdx, r10, r28);", // IID885 + "__ ecmovq (Assembler::Condition::above, r8, r8, r17);", // IID886 + "__ ecmovq (Assembler::Condition::negative, rcx, r30, r23);", // IID887 + "__ ecmovq (Assembler::Condition::negative, r26, r26, r18);", // IID888 + "__ ecmovq (Assembler::Condition::positive, rdx, rbx, r18);", // IID889 + "__ ecmovq (Assembler::Condition::positive, r21, r21, r13);", // IID890 + "__ ecmovq (Assembler::Condition::parity, r27, r28, r27);", // IID891 + "__ ecmovq (Assembler::Condition::parity, r11, r11, r30);", // IID892 + "__ ecmovq (Assembler::Condition::noParity, rcx, r21, r18);", // IID893 + "__ ecmovq (Assembler::Condition::noParity, rcx, rcx, r29);", // IID894 + "__ ecmovq (Assembler::Condition::less, rdx, r21, r12);", // IID895 + "__ ecmovq (Assembler::Condition::less, rdx, rdx, r26);", // IID896 + "__ ecmovq (Assembler::Condition::greaterEqual, r17, rbx, r22);", // IID897 + "__ ecmovq (Assembler::Condition::greaterEqual, rdx, rdx, r11);", // IID898 + "__ ecmovq (Assembler::Condition::lessEqual, rdx, r14, r8);", // IID899 + "__ ecmovq (Assembler::Condition::lessEqual, r14, r14, r8);", // IID900 + "__ ecmovq (Assembler::Condition::greater, r25, r29, r21);", // IID901 + "__ ecmovq (Assembler::Condition::greater, r26, r26, r30);", // IID902 + "__ ecmovq (Assembler::Condition::overflow, r24, r21, Address(r13, r11, (Address::ScaleFactor)1, +0x439c521e));", // IID903 + "__ ecmovq (Assembler::Condition::noOverflow, r11, r18, Address(r29, r16, (Address::ScaleFactor)0, +0x632127f));", // IID904 + "__ ecmovq (Assembler::Condition::below, r16, r8, Address(r8, r26, (Address::ScaleFactor)1, +0x10633def));", // IID905 + "__ ecmovq (Assembler::Condition::aboveEqual, r13, r14, Address(r18, -0x54f69e38));", // IID906 + "__ ecmovq (Assembler::Condition::zero, r12, r8, Address(r31, r26, (Address::ScaleFactor)1, -0x7a1e447a));", // IID907 + "__ ecmovq (Assembler::Condition::notZero, r29, r29, Address(r19, r11, (Address::ScaleFactor)2, -0x35d82dd2));", // IID908 + "__ ecmovq (Assembler::Condition::belowEqual, rcx, r18, Address(r25, r28, (Address::ScaleFactor)0, +0x30be64a0));", // IID909 + "__ ecmovq (Assembler::Condition::above, r28, r12, Address(r10, r16, (Address::ScaleFactor)1, -0x22b8fefa));", // IID910 + "__ ecmovq (Assembler::Condition::negative, r11, r8, Address(rbx, r11, (Address::ScaleFactor)3, +0x25cc9e96));", // IID911 + "__ ecmovq (Assembler::Condition::positive, r12, r27, Address(r11, -0xc2d70fe));", // IID912 + "__ ecmovq (Assembler::Condition::parity, r8, r26, Address(r19, rbx, (Address::ScaleFactor)1, -0x486db7ea));", // IID913 + "__ ecmovq (Assembler::Condition::noParity, r30, r10, Address(r14, r18, (Address::ScaleFactor)3, +0x14884884));", // IID914 + "__ ecmovq (Assembler::Condition::less, r27, r8, Address(r29, r14, (Address::ScaleFactor)2, +0x92b7a8));", // IID915 + "__ ecmovq (Assembler::Condition::greaterEqual, r14, r28, Address(r19, rdx, (Address::ScaleFactor)0, +0x9c2d45));", // IID916 + "__ ecmovq (Assembler::Condition::lessEqual, r25, r8, Address(rcx, r18, (Address::ScaleFactor)2, +0x6655c86b));", // IID917 + "__ ecmovq (Assembler::Condition::greater, r19, r21, Address(r10, r25, (Address::ScaleFactor)0, -0x1005430b));", // IID918 #endif // _LP64 }; // END Generated code -- do not edit diff --git a/test/hotspot/gtest/x86/test_assembler_x86.cpp b/test/hotspot/gtest/x86/test_assembler_x86.cpp index 32315e06fde..1382d0c243f 100644 --- a/test/hotspot/gtest/x86/test_assembler_x86.cpp +++ b/test/hotspot/gtest/x86/test_assembler_x86.cpp @@ -71,7 +71,7 @@ TEST_VM(AssemblerX86, validate) { VM_Version::set_evex_cpuFeatures(); VM_Version::set_avx_cpuFeatures(); VM_Version::set_apx_cpuFeatures(); - BufferBlob* b = BufferBlob::create("x64Test", 500000); + BufferBlob* b = BufferBlob::create("x64Test", 5000000); CodeBuffer code(b); MacroAssembler _masm(&code); address entry = __ pc(); diff --git a/test/hotspot/gtest/x86/x86-asmtest.py b/test/hotspot/gtest/x86/x86-asmtest.py index 51932988fb2..7081c64e604 100644 --- a/test/hotspot/gtest/x86/x86-asmtest.py +++ b/test/hotspot/gtest/x86/x86-asmtest.py @@ -30,6 +30,7 @@ OBJDUMP = "objdump" X86_AS = "as" X86_OBJCOPY = "objcopy" SEED = 1327 +TEST_DEMOTION = True random.seed(SEED) @@ -301,12 +302,18 @@ class CondRegRegRegInstruction(Instruction): self.reg3 = Register().generate(reg3, width) self.cond = cond self.generate_operands(self.reg1, self.reg2, self.reg3) + self.demote = True def cstr(self): return f'__ {self._name} (' + 'Assembler::Condition::' + self.cond + ', ' + ', '.join([reg.cstr() for reg in self.operands]) + ');' def astr(self): - return f'{self._aname}' + cond_to_suffix[self.cond] + ' ' + ', '.join([reg.astr() for reg in self.operands]) + operands = self.operands + if self.demote: + ops = [op.cstr() for op in self.operands] + if ops[0] == ops[1]: + operands = operands[1:] + return f'{self._aname}' + cond_to_suffix[self.cond] + ' ' + ', '.join([reg.astr() for reg in operands]) class CondRegRegMemInstruction(Instruction): def __init__(self, name, aname, width, cond, reg1, reg2, mem_base, mem_idx): @@ -316,12 +323,18 @@ class CondRegRegMemInstruction(Instruction): self.mem = Address().generate(mem_base, mem_idx, width) self.cond = cond self.generate_operands(self.reg1, self.reg2, self.mem) + self.demote = True def cstr(self): return f'__ {self._name} (' + 'Assembler::Condition::' + self.cond + ', ' + ', '.join([reg.cstr() for reg in self.operands]) + ');' def astr(self): - return f'{self._aname}' + cond_to_suffix[self.cond] + ' ' + ', '.join([reg.astr() for reg in self.operands]) + operands = self.operands + if self.demote: + ops = [op.cstr() for op in self.operands] + if ops[0] == ops[1]: + operands = operands[1:] + return f'{self._aname}' + cond_to_suffix[self.cond] + ' ' + ', '.join([reg.astr() for reg in operands]) class MoveRegMemInstruction(Instruction): def __init__(self, name, aname, width, mem_width, reg, mem_base, mem_idx): @@ -355,6 +368,15 @@ class RegRegNddInstruction(NFInstruction): self.reg1 = Register().generate(reg1, width) self.reg2 = Register().generate(reg2, width) self.generate_operands(self.reg1, self.reg2) + self.demote = True + + def astr(self): + if self.demote and self._aname not in ['popcnt', 'lzcnt', 'tzcnt']: + ops = [op.cstr() for op in self.operands] + if ops[0] == ops[1] and (not self.no_flag): + cl_str = (', cl' if self._name in shift_rot_ops and len(self.operands) == 2 else '') + return f'{self._aname} ' + ', '.join([op.astr() for op in self.operands[1:]]) + cl_str + return super().astr() class RegMemNddInstruction(NFInstruction): def __init__(self, name, aname, width, no_flag, reg, mem_base, mem_idx): @@ -386,6 +408,14 @@ class RegRegImmNddInstruction(NFInstruction): self.reg2 = Register().generate(reg2, width) self.imm = Immediate().generate(imm) self.generate_operands(self.reg1, self.reg2, self.imm) + self.demote = True + + def astr(self): + if self.demote and self._aname not in ['imul']: + ops = [op.cstr() for op in self.operands] + if ops[0] == ops[1] and (not self.no_flag): + return f'{self._aname} ' + ', '.join([op.astr() for op in self.operands[1:]]) + return super().astr() class RegRegMemNddInstruction(NFInstruction): def __init__(self, name, aname, width, no_flag, reg1, reg2, mem_base, mem_idx): @@ -394,6 +424,14 @@ class RegRegMemNddInstruction(NFInstruction): self.reg2 = Register().generate(reg2, width) self.mem = Address().generate(mem_base, mem_idx, width) self.generate_operands(self.reg1, self.reg2, self.mem) + self.demote = True + + def astr(self): + if self.demote: + ops = [op.cstr() for op in self.operands] + if ops[0] == ops[1] and (not self.no_flag): + return f'{self._aname} ' + ', '.join([op.astr() for op in self.operands[1:]]) + return super().astr() class RegRegRegNddInstruction(NFInstruction): def __init__(self, name, aname, width, no_flag, reg1, reg2, reg3): @@ -402,9 +440,15 @@ class RegRegRegNddInstruction(NFInstruction): self.reg2 = Register().generate(reg2, width) self.reg3 = Register().generate(reg3, width) self.generate_operands(self.reg1, self.reg2, self.reg3) + self.demote = True def astr(self): - return f'{{load}}' + super().astr() + hdr = f'{{load}}' + if self.demote: + ops = [op.cstr() for op in self.operands] + if ops[0] == ops[1] and (not self.no_flag): + return hdr + f'{self._aname} ' + ', '.join([op.astr() for op in self.operands[1:]]) + return hdr + super().astr() class RegRegRegImmNddInstruction(NFInstruction): def __init__(self, name, aname, width, no_flag, reg1, reg2, reg3, imm): @@ -414,6 +458,15 @@ class RegRegRegImmNddInstruction(NFInstruction): self.reg3 = Register().generate(reg3, width) self.imm = Immediate().generate(imm) self.generate_operands(self.reg1, self.reg2, self.reg3, self.imm) + self.demote = True + + def astr(self): + if self.demote: + ops = [op.cstr() for op in self.operands] + if ops[0] == ops[1] and (not self.no_flag): + return (f'{self._aname} ' + ', '.join([op.astr() for op in self.operands[1:]])) + return super().astr() + test_regs = [key for key in registers_mapping.keys() if key != 'rax'] @@ -499,36 +552,28 @@ def generate(RegOp, ops, print_lp64_flag=True, full_set=False): print_instruction(instr, lp64_flag, print_lp64_flag) elif RegOp in [TwoRegInstruction, MoveRegRegInstruction, RegRegNddInstruction]: - if full_set: - for i in range(len(test_regs)): - test_reg1 = test_regs[i] - test_reg2 = test_regs[(i + 1) % len(test_regs)] + demote_options = [False, True] if TEST_DEMOTION and RegOp in [RegRegNddInstruction] else [False] + for demote in demote_options: + for i in range(len(test_regs) if full_set else 1): + test_reg1 = test_regs[i] if full_set else random.choice(test_regs) + test_reg2 = test_reg1 if demote \ + else test_regs[(i + 1) % len(test_regs)] if full_set \ + else random.choice(test_regs) lp64_flag = handle_lp64_flag(lp64_flag, print_lp64_flag, test_reg1, test_reg2) instr = RegOp(*op, reg1=test_reg1, reg2=test_reg2) print_instruction(instr, lp64_flag, print_lp64_flag) - else: - test_reg1 = random.choice(test_regs) - test_reg2 = random.choice(test_regs) - lp64_flag = handle_lp64_flag(lp64_flag, print_lp64_flag, test_reg1, test_reg2) - instr = RegOp(*op, reg1=test_reg1, reg2=test_reg2) - print_instruction(instr, lp64_flag, print_lp64_flag) elif RegOp in [RegRegRegNddInstruction, CondRegRegRegInstruction]: - if full_set: - for i in range(len(test_regs)): - test_reg1 = test_regs[i] - test_reg2 = test_regs[(i + 1) % len(test_regs)] - test_reg3 = test_regs[(i + 2) % len(test_regs)] + for demote in [False, True] if TEST_DEMOTION else [False]: + for i in range(len(test_regs) if full_set else 1): + test_reg1 = test_regs[i] if full_set else random.choice(test_regs) + test_reg2 = test_reg1 if demote \ + else test_regs[(i + 1) % len(test_regs)] if full_set \ + else random.choice(test_regs) + test_reg3 = test_regs[(i + 2) % len(test_regs)] if full_set else random.choice(test_regs) lp64_flag = handle_lp64_flag(lp64_flag, print_lp64_flag, test_reg1, test_reg2, test_reg3) instr = RegOp(*op, reg1=test_reg1, reg2=test_reg2, reg3=test_reg3) print_instruction(instr, lp64_flag, print_lp64_flag) - else: - test_reg1 = random.choice(test_regs) - test_reg2 = random.choice(test_regs) - test_reg3 = random.choice(test_regs) - lp64_flag = handle_lp64_flag(lp64_flag, print_lp64_flag, test_reg1, test_reg2, test_reg3) - instr = RegOp(*op, reg1=test_reg1, reg2=test_reg2, reg3=test_reg3) - print_instruction(instr, lp64_flag, print_lp64_flag) elif RegOp in [MemRegInstruction, RegMemInstruction, MoveRegMemInstruction, CmpxchgInstruction, CondRegMemInstruction, RegMemNddInstruction]: if full_set: @@ -607,30 +652,28 @@ def generate(RegOp, ops, print_lp64_flag=True, full_set=False): print_instruction(instr, lp64_flag, print_lp64_flag) elif RegOp in [RegRegImmInstruction, RegRegImmNddInstruction]: - if full_set: + demote_options = [False, True] if TEST_DEMOTION and RegOp in [RegRegImmNddInstruction] else [False] + for demote in demote_options: imm_list = get_immediate_list(op_name, width) - for i in range(len(test_regs)): - test_reg1 = test_regs[i] - test_reg2 = test_regs[(i + 1) % len(test_regs)] + if not full_set: + imm_list = [random.choice(imm_list)] + for i in range(len(test_regs) if full_set else 1): + test_reg1 = test_regs[i] if full_set else random.choice(test_regs) + test_reg2 = test_reg1 if demote \ + else test_regs[(i + 1) % len(test_regs)] if full_set \ + else random.choice(test_regs) lp64_flag = handle_lp64_flag(lp64_flag, print_lp64_flag, test_reg1, test_reg2) for imm in imm_list: instr = RegOp(*op, reg1=test_reg1, reg2=test_reg2, imm=imm) print_instruction(instr, lp64_flag, print_lp64_flag) - else: - imm = random.choice(get_immediate_list(op_name, width)) - test_reg1 = random.choice(test_regs) - test_reg2 = random.choice(test_regs) - lp64_flag = handle_lp64_flag(lp64_flag, print_lp64_flag, test_reg1, test_reg2) - instr = RegOp(*op, reg1=test_reg1, reg2=test_reg2, imm=imm) - print_instruction(instr, lp64_flag, print_lp64_flag) - # additional tests with rax as destination - if RegOp in [RegRegImmNddInstruction]: - test_reg1 = 'rax' - test_reg2 = random.choice(test_regs) - lp64_flag = handle_lp64_flag(lp64_flag, print_lp64_flag, test_reg1, test_reg2) - instr = RegOp(*op, reg1=test_reg1, reg2=test_reg2, imm=imm) - print_instruction(instr, lp64_flag, print_lp64_flag) + # additional tests with rax as destination + if RegOp in [RegRegImmNddInstruction] and not demote and not full_set: + test_reg1 = 'rax' + test_reg2 = random.choice(test_regs) + lp64_flag = handle_lp64_flag(lp64_flag, print_lp64_flag, test_reg1, test_reg2) + instr = RegOp(*op, reg1=test_reg1, reg2=test_reg2, imm=imm) + print_instruction(instr, lp64_flag, print_lp64_flag) elif RegOp in [RegMemImmInstruction, RegMemImmNddInstruction]: if full_set: @@ -656,46 +699,37 @@ def generate(RegOp, ops, print_lp64_flag=True, full_set=False): print_instruction(instr, lp64_flag, print_lp64_flag) elif RegOp in [RegMemRegNddInstruction, RegRegMemNddInstruction, CondRegRegMemInstruction]: - if full_set: - for i in range(len(test_regs)): - test_reg1 = test_regs[i] - test_mem_base = test_regs[(i + 1) % len(test_regs)] - test_mem_idx = test_regs[(i + 2) % len(test_regs)] - test_reg2 = test_regs[(i + 3) % len(test_regs)] + demote_options = [False] if TEST_DEMOTION and RegOp not in [RegMemRegNddInstruction] else [False, True] + for demote in demote_options: + for i in range(len(test_regs) if full_set else 1): + test_reg1 = test_regs[i] if full_set else random.choice(test_regs) + test_mem_base = test_regs[(i + 1) % len(test_regs)] if full_set else random.choice(test_regs) + test_mem_idx = test_regs[(i + 2) % len(test_regs)] if full_set \ + else random.choice([reg for reg in test_regs if reg != 'rsp']) + test_reg2 = test_reg1 if demote \ + else test_regs[(i + 3) % len(test_regs)] if full_set \ + else random.choice(test_regs) if test_mem_idx == 'rsp': continue lp64_flag = handle_lp64_flag(lp64_flag, print_lp64_flag, test_reg1, test_mem_base, test_mem_idx, test_reg2) instr = RegOp(*op, reg1=test_reg1, mem_base=test_mem_base, mem_idx=test_mem_idx, reg2=test_reg2) print_instruction(instr, lp64_flag, print_lp64_flag) - else: - filtered_regs = [reg for reg in test_regs if reg != 'rsp'] - test_reg1 = random.choice(test_regs) - test_mem_base = random.choice(test_regs) - test_mem_idx = random.choice(filtered_regs) - test_reg2 = random.choice(test_regs) - lp64_flag = handle_lp64_flag(lp64_flag, print_lp64_flag, test_reg1, test_mem_base, test_mem_idx, test_reg2) - instr = RegOp(*op, reg1=test_reg1, mem_base=test_mem_base, mem_idx=test_mem_idx, reg2=test_reg2) - print_instruction(instr, lp64_flag, print_lp64_flag) - + elif RegOp in [RegRegRegImmNddInstruction]: - if full_set: + for demote in [False, True] if TEST_DEMOTION else [False]: imm_list = get_immediate_list(op_name, width) - for i in range(len(test_regs)): - test_reg1 = test_regs[i] - test_reg2 = test_regs[(i + 1) % len(test_regs)] - test_reg3 = test_regs[(i + 2) % len(test_regs)] + if not full_set: + imm_list = [random.choice(imm_list)] + for i in range(len(test_regs) if full_set else 1): + test_reg1 = test_regs[i] if full_set else random.choice(test_regs) + test_reg2 = test_reg1 if demote \ + else test_regs[(i + 1) % len(test_regs)] if full_set \ + else random.choice(test_regs) + test_reg3 = test_regs[(i + 2) % len(test_regs)] if full_set else random.choice(test_regs) lp64_flag = handle_lp64_flag(lp64_flag, print_lp64_flag, test_reg1, test_reg2, test_reg3) for imm in imm_list: instr = RegOp(*op, reg1=test_reg1, reg2=test_reg2, reg3=test_reg3, imm=imm) print_instruction(instr, lp64_flag, print_lp64_flag) - else: - imm = random.choice(get_immediate_list(op_name, width)) - test_reg1 = random.choice(test_regs) - test_reg2 = random.choice(test_regs) - test_reg3 = random.choice(test_regs) - lp64_flag = handle_lp64_flag(lp64_flag, print_lp64_flag, test_reg1, test_reg2, test_reg3) - instr = RegOp(*op, reg1=test_reg1, reg2=test_reg2, reg3=test_reg3, imm=imm) - print_instruction(instr, lp64_flag, print_lp64_flag) elif RegOp in [Push2Instruction, Pop2Instruction]: if full_set: @@ -936,7 +970,7 @@ instruction_set = { ('edecl', 'dec', 32, False), ('edecl', 'dec', 32, True), ('eincl', 'inc', 32, False), - ('eincl', 'inc', 32, True), + ('eincl', 'inc', 32, True), ('eshll', 'shl', 32, False), ('eshll', 'shl', 32, True), ('eshrl', 'shr', 32, False), @@ -1357,8 +1391,8 @@ instruction_set64 = { ('exorq', 'xor', 64, True), ('eorq_imm32', 'or', 64, False), ('eorq_imm32', 'or', 64, False), - ('esubq_imm32', 'sub', 64, False), - ('esubq_imm32', 'sub', 64, True), + ('esubq_imm32', 'sub', 64, False), + ('esubq_imm32', 'sub', 64, True), ], RegRegMemNddInstruction: [ ('eaddq', 'add', 64, False), @@ -1422,7 +1456,7 @@ if __name__ == "__main__": for RegOp, ops in instruction_set.items(): generate(RegOp, ops, True, full_set) - + if lp64_flag: lp64_flag = False print("#endif // _LP64")