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32 Commits

Author SHA1 Message Date
Hamlin Li
49d8e63833 8329083: RISC-V: Update profiles supported on riscv 
Reviewed-by: fyang
 2024-04-06 06:23:20 +00:00
Hamlin Li
a48f5966be 8322179: RISC-V: Implement SHA-1 intrinsic 
Reviewed-by: tonyp, fyang
 2024-02-27 08:17:33 +00:00
Hamlin Li
b363472265 8318227: RISC-V: C2 ConvHF2F 
Reviewed-by: fyang
 2024-01-15 18:41:53 +00:00
Ludovic Henry
4cf131a101 8319716: RISC-V: Add SHA-2 
Co-authored-by: Robbin Ehn <rehn@openjdk.org>
Reviewed-by: fyang, mli, luhenry
 2024-01-09 07:26:35 +00:00
Yuri Gaevsky
6359b4ec23 8318217: RISC-V: C2 VectorizedHashCode 
Reviewed-by: mli, fyang
 2023-12-12 06:35:09 +00:00
David Holmes
c75c38871e 8318776: Require supports_cx8 to always be true 
Reviewed-by: eosterlund, shade, dcubed
 2023-11-23 22:23:42 +00:00
ArsenyBochkarev
46e4028adf 8316592: RISC-V: implement poly1305 intrinsic 
Reviewed-by: fyang, luhenry, mli
 2023-11-21 07:36:55 +00:00
Hamlin Li
fac6b51699 8319781: RISC-V: Refactor UseRVV related checks 
Reviewed-by: rehn, fyang
 2023-11-15 09:51:14 +00:00
Hamlin Li
1c0e7b71b8 8319408: RISC-V: MaxVectorSize is not consistently checked in several situations 
Reviewed-by: fyang
 2023-11-07 09:50:51 +00:00
Ilya Gavrilin
5a97411f85 8317971: RISC-V: implement copySignF/D and signumF/D intrinsics 
Reviewed-by: fyang, vkempik
 2023-10-20 14:31:41 +00:00
Hamlin Li
8f8c45b54a 8315716: RISC-V: implement ChaCha20 intrinsic 
Reviewed-by: luhenry, fyang
 2023-10-11 14:48:28 +00:00
Ilya Gavrilin
750da00129 8316743: RISC-V: Change UseVectorizedMismatchIntrinsic option result to warning 
Reviewed-by: fyang, luhenry
 2023-09-27 17:07:10 +00:00
Ludovic Henry
a731a24c93 8315934: RISC-V: Disable conservative fences per vendor 
Reviewed-by: rehn, mli, fyang
 2023-09-13 14:54:43 +00:00
Ludovic Henry
35bccacb66 8315841: RISC-V: Check for hardware TSO support 
Reviewed-by: vkempik, rehn, fyang
 2023-09-11 09:02:40 +00:00
Gui Cao
a66b5df14a 8314618: RISC-V: -XX:MaxVectorSize does not work as expected 
Reviewed-by: fyang, dzhang
 2023-08-22 02:47:52 +00:00
Antonios Printezis
b093880acd 8313322: RISC-V: implement MD5 intrinsic 
Reviewed-by: luhenry, rehn
 2023-08-02 13:17:00 +00:00
Ludovic Henry
e8f66bf88c 8310949: RISC-V: Initialize UseUnalignedAccesses 
Reviewed-by: rehn, vkempik, fyang
 2023-07-15 06:50:21 +00:00
Dean Long
da0f8325de 8310606: Fix signed integer overflow, part 3 
Reviewed-by: kvn, thartmann
 2023-06-28 20:31:08 +00:00
Robbin Ehn
31b6fd775f 8309258: RISC-V: Add riscv_hwprobe syscall 
Reviewed-by: fjiang, stuefe, fyang, luhenry
 2023-06-20 15:12:46 +00:00
Johan Sjölen
d2ce04bb10 8301496: Replace NULL with nullptr in cpu/riscv 
Reviewed-by: dholmes, fyang
 2023-04-14 09:53:46 +00:00
Feilong Jiang
c09f83ec25 8304293: RISC-V: JDK-8276799 missed atomic intrinsic support for C1 
Reviewed-by: fyang, yzhu
 2023-03-20 00:53:52 +00:00
Vladimir Kozlov
8cfd74f76a 8302976: C2 intrinsification of Float.floatToFloat16 and Float.float16ToFloat yields different result than the interpreter 
Reviewed-by: sviswanathan, jbhateja, vlivanov
 2023-03-09 03:26:38 +00:00
Feilong Jiang
633e291cfc 8301067: RISC-V: better error message when reporting unsupported satp modes 
Reviewed-by: fyang, yadongwang
 2023-01-31 07:15:37 +00:00
Yadong Wang
af564e46b0 8299844: RISC-V: Implement _onSpinWait intrinsic 
Reviewed-by: fjiang, fyang, luhenry
 2023-01-28 02:17:44 +00:00
Yadong Wang
3a66737001 8299525: RISC-V: Add backend support for half float conversion intrinsics 
Reviewed-by: fyang, fjiang
 2023-01-10 02:43:14 +00:00
Feilong Jiang
f49acd5259 8297697: RISC-V: Add support for SATP mode detection 
Reviewed-by: fyang, luhenry
 2022-12-01 04:01:25 +00:00
Xiaolin Zheng
38eb80d4d8 8296975: RISC-V: Enable UseRVA20U64 profile by default 
Reviewed-by: fyang, vkempik
 2022-11-17 13:45:56 +00:00
Ludovic Henry
4465361ee9 8295948: Support for Zicbop/prefetch instructions on RISC-V 
Reviewed-by: fyang, yadongwang
 2022-11-10 13:37:41 +00:00
Ludovic Henry
e0c29307f7 8295282: Use Zicboz/cbo.zero to zero-out memory on RISC-V 
Reviewed-by: yadongwang, vkempik, fyang
 2022-10-25 20:11:48 +00:00
Ioi Lam
b6b0317f83 8290840: Refactor the "os" class 
Reviewed-by: dholmes, gziemski, stuefe, stefank
 2022-08-04 01:20:29 +00:00
Feilong Jiang
060a188733 8283865: riscv: Break down -XX:+UseRVB into seperate options for each bitmanip extension 
Reviewed-by: fyang, shade
 2022-04-02 02:55:50 +00:00
Fei Yang
5905b02c0e 8276799: Implementation of JEP 422: Linux/RISC-V Port 
Co-authored-by: Yadong Wang <yadonn.wang@huawei.com>
Co-authored-by: Yanhong Zhu <zhuyanhong2@huawei.com>
Co-authored-by: Feilong Jiang <jiangfeilong@huawei.com>
Co-authored-by: Kun Wang <wangkun49@huawei.com>
Co-authored-by: Zhuxuan Ni <nizhuxuan@huawei.com>
Co-authored-by: Taiping Guo <guotaiping1@huawei.com>
Co-authored-by: Kang He <hekang6@huawei.com>
Co-authored-by: Aleksey Shipilev <shade@openjdk.org>
Co-authored-by: Xiaolin Zheng <yunyao.zxl@alibaba-inc.com>
Co-authored-by: Kuai Wei <kuaiwei.kw@alibaba-inc.com>
Co-authored-by: Magnus Ihse Bursie <ihse@openjdk.org>
Reviewed-by: ihse, dholmes, rriggs, kvn, shade
 2022-03-24 09:22:46 +00:00