Hamlin Li
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1b6281d98c
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8321003: RISC-V: C2 MulReductionVI
8321004: RISC-V: C2 MulReductionVL
Reviewed-by: fyang, rehn
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2025-02-21 10:25:50 +00:00 |
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Hamlin Li
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4a83ca1202
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8349666: RISC-V: enable superwords tests for vector reductions
Reviewed-by: fyang, luhenry
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2025-02-10 11:25:20 +00:00 |
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Emanuel Peter
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06b0a5e038
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8302652: [SuperWord] Reduction should happen after loop, when possible
Reviewed-by: kvn, pli, jbhateja, sviswanathan
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2023-05-23 08:05:13 +00:00 |
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Daniel Skantz
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d20bde29f2
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8294715: Add IR checks to the reduction vectorization tests
Reviewed-by: rcastanedalo, epeter
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2023-03-13 07:33:46 +00:00 |
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Sandhya Viswanathan
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398ce2948c
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8240248: Extend superword reduction optimizations for x86
Add support for and, or, xor reduction
Co-authored-by: Shravya Rukmannagari <shravya.rukmannagari@intel.com>
Reviewed-by: vlivanov, thartmann
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2020-03-23 10:26:40 -07:00 |
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