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69 lines
2.5 KiB
C++
69 lines
2.5 KiB
C++
/*
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* Copyright (c) 1997, 2023, Oracle and/or its affiliates. All rights reserved.
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* Copyright (c) 2020, 2022, Huawei Technologies Co., Ltd. All rights reserved.
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* Copyright (c) 2023, Rivos Inc. All rights reserved.
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* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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*
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* This code is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 only, as
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* published by the Free Software Foundation.
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*
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* This code is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* version 2 for more details (a copy is included in the LICENSE file that
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* accompanied this code).
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*
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* You should have received a copy of the GNU General Public License version
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* 2 along with this work; if not, write to the Free Software Foundation,
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* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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*
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* Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
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* or visit www.oracle.com if you need additional information or have any
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* questions.
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*
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*/
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#include "precompiled.hpp"
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#include "asm/macroAssembler.hpp"
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#include "riscv_flush_icache.hpp"
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#include "runtime/java.hpp"
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#include "runtime/icache.hpp"
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#define __ _masm->
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static int icache_flush(address addr, int lines, int magic) {
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// To make a store to instruction memory visible to all RISC-V harts,
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// the writing hart has to execute a data FENCE before requesting that
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// all remote RISC-V harts execute a FENCE.I.
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// We need to make sure stores happens before the I/D cache synchronization.
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__asm__ volatile("fence rw, rw" : : : "memory");
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RiscvFlushIcache::flush((uintptr_t)addr, ((uintptr_t)lines) << ICache::log2_line_size);
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return magic;
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}
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void ICacheStubGenerator::generate_icache_flush(ICache::flush_icache_stub_t* flush_icache_stub) {
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// Only riscv_flush_icache is supported as I-cache synchronization.
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// We must make sure the VM can execute such without error.
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if (!RiscvFlushIcache::test()) {
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vm_exit_during_initialization("Unable to synchronize I-cache");
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}
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address start = (address)icache_flush;
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*flush_icache_stub = (ICache::flush_icache_stub_t)start;
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// ICache::invalidate_range() contains explicit condition that the first
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// call is invoked on the generated icache flush stub code range.
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ICache::invalidate_range(start, 0);
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{
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StubCodeMark mark(this, "ICache", "fake_stub_for_inlined_icache_flush");
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__ ret();
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}
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}
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#undef __
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