mirror of
https://github.com/openjdk/jdk.git
synced 2026-04-14 08:58:46 +00:00
dfe438d057
Co-authored-by: Stuart Monteith <smonteith@openjdk.org> Co-authored-by: Andrew Haley <aph@openjdk.org> Reviewed-by: aph, eastigeevich
1782 lines
132 KiB
C
1782 lines
132 KiB
C
// BEGIN Generated code -- do not edit
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// Generated by aarch64-asmtest.py
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Label back, forth;
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__ bind(back);
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// ArithOp
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__ add(r26, r23, r13, Assembler::LSL, 32); // add x26, x23, x13, LSL #32
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__ sub(r12, r24, r9, Assembler::LSR, 37); // sub x12, x24, x9, LSR #37
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__ adds(r28, r15, r8, Assembler::ASR, 39); // adds x28, x15, x8, ASR #39
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__ subs(r7, r28, r30, Assembler::ASR, 57); // subs x7, x28, x30, ASR #57
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__ addw(r9, r22, r27, Assembler::ASR, 15); // add w9, w22, w27, ASR #15
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__ subw(r3, r13, r17, Assembler::ASR, 30); // sub w3, w13, w17, ASR #30
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__ addsw(r14, r26, r8, Assembler::ASR, 17); // adds w14, w26, w8, ASR #17
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__ subsw(r0, r22, r12, Assembler::ASR, 21); // subs w0, w22, w12, ASR #21
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__ andr(r0, r15, r26, Assembler::LSL, 20); // and x0, x15, x26, LSL #20
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__ orr(r26, r5, r17, Assembler::LSL, 61); // orr x26, x5, x17, LSL #61
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__ eor(r24, r13, r2, Assembler::LSL, 32); // eor x24, x13, x2, LSL #32
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__ ands(r28, r3, r17, Assembler::ASR, 35); // ands x28, x3, x17, ASR #35
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__ andw(r25, r16, r29, Assembler::LSR, 18); // and w25, w16, w29, LSR #18
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__ orrw(r13, r17, r11, Assembler::LSR, 9); // orr w13, w17, w11, LSR #9
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__ eorw(r5, r5, r17, Assembler::LSR, 15); // eor w5, w5, w17, LSR #15
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__ andsw(r2, r23, r27, Assembler::ASR, 26); // ands w2, w23, w27, ASR #26
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__ bic(r27, r28, r16, Assembler::LSR, 45); // bic x27, x28, x16, LSR #45
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__ orn(r8, r25, r26, Assembler::ASR, 37); // orn x8, x25, x26, ASR #37
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__ eon(r29, r17, r13, Assembler::LSR, 63); // eon x29, x17, x13, LSR #63
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__ bics(r28, r24, r2, Assembler::LSR, 31); // bics x28, x24, x2, LSR #31
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__ bicw(r19, r26, r7, Assembler::ASR, 3); // bic w19, w26, w7, ASR #3
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__ ornw(r6, r24, r10, Assembler::ASR, 3); // orn w6, w24, w10, ASR #3
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__ eonw(r4, r21, r1, Assembler::LSR, 29); // eon w4, w21, w1, LSR #29
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__ bicsw(r16, r21, r0, Assembler::LSR, 19); // bics w16, w21, w0, LSR #19
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// AddSubImmOp
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__ addw(r17, r12, 379u); // add w17, w12, #379
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__ addsw(r30, r1, 22u); // adds w30, w1, #22
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__ subw(r29, r5, 126u); // sub w29, w5, #126
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__ subsw(r6, r24, 960u); // subs w6, w24, #960
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__ add(r0, r13, 104u); // add x0, x13, #104
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__ adds(r8, r6, 663u); // adds x8, x6, #663
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__ sub(r10, r5, 516u); // sub x10, x5, #516
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__ subs(r1, r3, 1012u); // subs x1, x3, #1012
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// LogicalImmOp
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__ andw(r6, r11, 4294049777ull); // and w6, w11, #0xfff1fff1
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__ orrw(r28, r5, 4294966791ull); // orr w28, w5, #0xfffffe07
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__ eorw(r1, r20, 134217216ull); // eor w1, w20, #0x7fffe00
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__ andsw(r7, r17, 1048576ull); // ands w7, w17, #0x100000
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__ andr(r14, r12, 9223372036854775808ull); // and x14, x12, #0x8000000000000000
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__ orr(r9, r11, 562675075514368ull); // orr x9, x11, #0x1ffc000000000
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__ eor(r17, r0, 18014398509481728ull); // eor x17, x0, #0x3fffffffffff00
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__ ands(r1, r8, 18446744073705357315ull); // ands x1, x8, #0xffffffffffc00003
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// AbsOp
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__ b(__ pc()); // b .
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__ b(back); // b back
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__ b(forth); // b forth
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__ bl(__ pc()); // bl .
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__ bl(back); // bl back
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__ bl(forth); // bl forth
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// RegAndAbsOp
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__ cbzw(r10, __ pc()); // cbz w10, .
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__ cbzw(r10, back); // cbz w10, back
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__ cbzw(r10, forth); // cbz w10, forth
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__ cbnzw(r8, __ pc()); // cbnz w8, .
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__ cbnzw(r8, back); // cbnz w8, back
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__ cbnzw(r8, forth); // cbnz w8, forth
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__ cbz(r11, __ pc()); // cbz x11, .
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__ cbz(r11, back); // cbz x11, back
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__ cbz(r11, forth); // cbz x11, forth
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__ cbnz(r29, __ pc()); // cbnz x29, .
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__ cbnz(r29, back); // cbnz x29, back
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__ cbnz(r29, forth); // cbnz x29, forth
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__ adr(r19, __ pc()); // adr x19, .
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__ adr(r19, back); // adr x19, back
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__ adr(r19, forth); // adr x19, forth
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__ _adrp(r19, __ pc()); // adrp x19, .
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// RegImmAbsOp
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__ tbz(r22, 6, __ pc()); // tbz x22, #6, .
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__ tbz(r22, 6, back); // tbz x22, #6, back
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__ tbz(r22, 6, forth); // tbz x22, #6, forth
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__ tbnz(r12, 11, __ pc()); // tbnz x12, #11, .
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__ tbnz(r12, 11, back); // tbnz x12, #11, back
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__ tbnz(r12, 11, forth); // tbnz x12, #11, forth
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// MoveWideImmOp
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__ movnw(r0, 6301, 0); // movn w0, #6301, lsl 0
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__ movzw(r7, 20886, 0); // movz w7, #20886, lsl 0
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__ movkw(r27, 18617, 0); // movk w27, #18617, lsl 0
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__ movn(r12, 22998, 16); // movn x12, #22998, lsl 16
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__ movz(r20, 1532, 16); // movz x20, #1532, lsl 16
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__ movk(r8, 5167, 32); // movk x8, #5167, lsl 32
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// BitfieldOp
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__ sbfm(r15, r17, 24, 28); // sbfm x15, x17, #24, #28
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__ bfmw(r15, r9, 14, 25); // bfm w15, w9, #14, #25
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__ ubfmw(r27, r25, 6, 31); // ubfm w27, w25, #6, #31
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__ sbfm(r19, r2, 23, 31); // sbfm x19, x2, #23, #31
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__ bfm(r12, r21, 10, 6); // bfm x12, x21, #10, #6
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__ ubfm(r22, r0, 26, 16); // ubfm x22, x0, #26, #16
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// ExtractOp
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__ extrw(r3, r3, r20, 27); // extr w3, w3, w20, #27
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__ extr(r8, r30, r3, 54); // extr x8, x30, x3, #54
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// CondBranchOp
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__ br(Assembler::EQ, __ pc()); // b.EQ .
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__ br(Assembler::EQ, back); // b.EQ back
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__ br(Assembler::EQ, forth); // b.EQ forth
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__ br(Assembler::NE, __ pc()); // b.NE .
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__ br(Assembler::NE, back); // b.NE back
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__ br(Assembler::NE, forth); // b.NE forth
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__ br(Assembler::HS, __ pc()); // b.HS .
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__ br(Assembler::HS, back); // b.HS back
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__ br(Assembler::HS, forth); // b.HS forth
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__ br(Assembler::CS, __ pc()); // b.CS .
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__ br(Assembler::CS, back); // b.CS back
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__ br(Assembler::CS, forth); // b.CS forth
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__ br(Assembler::LO, __ pc()); // b.LO .
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__ br(Assembler::LO, back); // b.LO back
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__ br(Assembler::LO, forth); // b.LO forth
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__ br(Assembler::CC, __ pc()); // b.CC .
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__ br(Assembler::CC, back); // b.CC back
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__ br(Assembler::CC, forth); // b.CC forth
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__ br(Assembler::MI, __ pc()); // b.MI .
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__ br(Assembler::MI, back); // b.MI back
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__ br(Assembler::MI, forth); // b.MI forth
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__ br(Assembler::PL, __ pc()); // b.PL .
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__ br(Assembler::PL, back); // b.PL back
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__ br(Assembler::PL, forth); // b.PL forth
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__ br(Assembler::VS, __ pc()); // b.VS .
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__ br(Assembler::VS, back); // b.VS back
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__ br(Assembler::VS, forth); // b.VS forth
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__ br(Assembler::VC, __ pc()); // b.VC .
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__ br(Assembler::VC, back); // b.VC back
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__ br(Assembler::VC, forth); // b.VC forth
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__ br(Assembler::HI, __ pc()); // b.HI .
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__ br(Assembler::HI, back); // b.HI back
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__ br(Assembler::HI, forth); // b.HI forth
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__ br(Assembler::LS, __ pc()); // b.LS .
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__ br(Assembler::LS, back); // b.LS back
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__ br(Assembler::LS, forth); // b.LS forth
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__ br(Assembler::GE, __ pc()); // b.GE .
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__ br(Assembler::GE, back); // b.GE back
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__ br(Assembler::GE, forth); // b.GE forth
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__ br(Assembler::LT, __ pc()); // b.LT .
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__ br(Assembler::LT, back); // b.LT back
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__ br(Assembler::LT, forth); // b.LT forth
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__ br(Assembler::GT, __ pc()); // b.GT .
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__ br(Assembler::GT, back); // b.GT back
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__ br(Assembler::GT, forth); // b.GT forth
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__ br(Assembler::LE, __ pc()); // b.LE .
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__ br(Assembler::LE, back); // b.LE back
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__ br(Assembler::LE, forth); // b.LE forth
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__ br(Assembler::AL, __ pc()); // b.AL .
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__ br(Assembler::AL, back); // b.AL back
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__ br(Assembler::AL, forth); // b.AL forth
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__ br(Assembler::NV, __ pc()); // b.NV .
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__ br(Assembler::NV, back); // b.NV back
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__ br(Assembler::NV, forth); // b.NV forth
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// ImmOp
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__ svc(12999); // svc #12999
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__ hvc(2665); // hvc #2665
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__ smc(9002); // smc #9002
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__ brk(14843); // brk #14843
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__ hlt(25964); // hlt #25964
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// Op
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__ nop(); // nop
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__ yield(); // yield
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__ wfe(); // wfe
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__ sev(); // sev
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__ sevl(); // sevl
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__ autia1716(); // autia1716
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__ autiasp(); // autiasp
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__ autiaz(); // autiaz
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__ autib1716(); // autib1716
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__ autibsp(); // autibsp
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__ autibz(); // autibz
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__ pacia1716(); // pacia1716
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__ paciasp(); // paciasp
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__ paciaz(); // paciaz
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__ pacib1716(); // pacib1716
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__ pacibsp(); // pacibsp
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__ pacibz(); // pacibz
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__ eret(); // eret
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__ drps(); // drps
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__ isb(); // isb
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__ sb(); // sb
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// OneRegOp
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__ wfet(r26); // wfet x26
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// PostfixExceptionOp
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__ wfi(); // wfi
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__ xpaclri(); // xpaclri
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// SystemOp
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__ dsb(Assembler::OSHST); // dsb OSHST
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__ dmb(Assembler::ISHLD); // dmb ISHLD
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// OneRegOp
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__ br(r20); // br x20
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__ blr(r10); // blr x10
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__ paciza(r27); // paciza x27
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__ pacizb(r8); // pacizb x8
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__ pacdza(r0); // pacdza x0
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__ pacdzb(r1); // pacdzb x1
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__ autiza(r21); // autiza x21
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__ autizb(r17); // autizb x17
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__ autdza(r29); // autdza x29
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__ autdzb(r29); // autdzb x29
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__ xpacd(r28); // xpacd x28
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__ braaz(r1); // braaz x1
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__ brabz(r23); // brabz x23
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__ blraaz(r21); // blraaz x21
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__ blrabz(r20); // blrabz x20
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// SystemOneRegOp
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__ msr(3, 4, 4, 1, r22); // msr fpsr, x22
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// SystemOneRegOp
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__ msr(3, 4, 2, 0, r27); // msr nzcv, x27
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// OneRegSystemOp
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__ mrs(3, 4, 4, 1, r19); // mrs x19, fpsr
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// OneRegSystemOp
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__ mrs(3, 4, 2, 0, r11); // mrs x11, nzcv
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// OneRegSystemOp
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__ mrs(3, 0, 0, 7, r16); // mrs x16, dczid_el0
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// OneRegSystemOp
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__ mrs(3, 0, 0, 1, r6); // mrs x6, ctr_el0
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// OneRegSystemOp
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__ mrs(3, 14, 0, 6, r17); // mrs x17, cntvctss_el0
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// PostfixExceptionOneRegOp
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__ xpaci(r0); // xpaci x0
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// LoadStoreExclusiveOp
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__ stxr(r4, r10, r24); // stxr w4, x10, [x24]
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__ stlxr(r22, r10, r19); // stlxr w22, x10, [x19]
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__ ldxr(r1, r5); // ldxr x1, [x5]
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__ ldaxr(r30, r8); // ldaxr x30, [x8]
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__ stlr(r12, r17); // stlr x12, [x17]
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__ ldar(r9, r14); // ldar x9, [x14]
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// LoadStoreExclusiveOp
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__ stxrw(r7, r1, r5); // stxr w7, w1, [x5]
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__ stlxrw(r16, r2, r12); // stlxr w16, w2, [x12]
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__ ldxrw(r10, r12); // ldxr w10, [x12]
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__ ldaxrw(r3, r28); // ldaxr w3, [x28]
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__ stlrw(r14, r26); // stlr w14, [x26]
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__ ldarw(r30, r10); // ldar w30, [x10]
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// LoadStoreExclusiveOp
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__ stxrh(r14, r21, r13); // stxrh w14, w21, [x13]
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__ stlxrh(r9, r22, r27); // stlxrh w9, w22, [x27]
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__ ldxrh(r28, r19); // ldxrh w28, [x19]
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__ ldaxrh(r11, r30); // ldaxrh w11, [x30]
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__ stlrh(r19, r2); // stlrh w19, [x2]
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__ ldarh(r2, r23); // ldarh w2, [x23]
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// LoadStoreExclusiveOp
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__ stxrb(r1, r0, r12); // stxrb w1, w0, [x12]
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__ stlxrb(r16, r13, r15); // stlxrb w16, w13, [x15]
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__ ldxrb(r17, r21); // ldxrb w17, [x21]
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__ ldaxrb(r13, r11); // ldaxrb w13, [x11]
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__ stlrb(r30, r8); // stlrb w30, [x8]
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__ ldarb(r24, r13); // ldarb w24, [x13]
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// LoadStoreExclusiveOp
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__ ldxp(r11, r1, r26); // ldxp x11, x1, [x26]
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__ ldaxp(r21, r27, r13); // ldaxp x21, x27, [x13]
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__ stxp(r20, r3, r12, r6); // stxp w20, x3, x12, [x6]
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__ stlxp(r1, r29, r6, r4); // stlxp w1, x29, x6, [x4]
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// LoadStoreExclusiveOp
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__ ldxpw(r6, r11, r16); // ldxp w6, w11, [x16]
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__ ldaxpw(r4, r30, r12); // ldaxp w4, w30, [x12]
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__ stxpw(r21, r27, r15, r28); // stxp w21, w27, w15, [x28]
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__ stlxpw(r9, r15, r20, r6); // stlxp w9, w15, w20, [x6]
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// base_plus_unscaled_offset
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// LoadStoreOp
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__ str(r24, Address(r17, -125)); // str x24, [x17, -125]
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__ strw(r1, Address(r26, 10)); // str w1, [x26, 10]
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__ strb(r15, Address(r0, -17)); // strb w15, [x0, -17]
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__ strh(r17, Address(r17, 13)); // strh w17, [x17, 13]
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__ ldr(r5, Address(r25, 49)); // ldr x5, [x25, 49]
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__ ldrw(r19, Address(r15, -116)); // ldr w19, [x15, -116]
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__ ldrb(r20, Address(r3, 7)); // ldrb w20, [x3, 7]
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__ ldrh(r19, Address(r4, -25)); // ldrh w19, [x4, -25]
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__ ldrsb(r14, Address(r19, -6)); // ldrsb x14, [x19, -6]
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__ ldrsh(r28, Address(r19, -53)); // ldrsh x28, [x19, -53]
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__ ldrshw(r14, Address(r27, 13)); // ldrsh w14, [x27, 13]
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__ ldrsw(r6, Address(r24, -120)); // ldrsw x6, [x24, -120]
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__ ldrd(v18, Address(r2, 87)); // ldr d18, [x2, 87]
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__ ldrs(v0, Address(r28, -48)); // ldr s0, [x28, -48]
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__ strd(v31, Address(r28, 23)); // str d31, [x28, 23]
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__ strs(v11, Address(r25, 43)); // str s11, [x25, 43]
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// pre
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// LoadStoreOp
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__ str(r14, Address(__ pre(r8, -185))); // str x14, [x8, -185]!
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__ strw(r25, Address(__ pre(r9, -93))); // str w25, [x9, -93]!
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__ strb(r16, Address(__ pre(r23, -12))); // strb w16, [x23, -12]!
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__ strh(r22, Address(__ pre(r9, -56))); // strh w22, [x9, -56]!
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__ ldr(r11, Address(__ pre(r24, 109))); // ldr x11, [x24, 109]!
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__ ldrw(r21, Address(__ pre(r19, 52))); // ldr w21, [x19, 52]!
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__ ldrb(r6, Address(__ pre(r23, -2))); // ldrb w6, [x23, -2]!
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__ ldrh(r7, Address(__ pre(r8, 21))); // ldrh w7, [x8, 21]!
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__ ldrsb(r4, Address(__ pre(r12, -31))); // ldrsb x4, [x12, -31]!
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__ ldrsh(r8, Address(__ pre(r11, -4))); // ldrsh x8, [x11, -4]!
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__ ldrshw(r14, Address(__ pre(r21, -28))); // ldrsh w14, [x21, -28]!
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__ ldrsw(r0, Address(__ pre(r15, -71))); // ldrsw x0, [x15, -71]!
|
|
__ ldrd(v27, Address(__ pre(r2, 29))); // ldr d27, [x2, 29]!
|
|
__ ldrs(v13, Address(__ pre(r21, 16))); // ldr s13, [x21, 16]!
|
|
__ strd(v12, Address(__ pre(r27, 16))); // str d12, [x27, 16]!
|
|
__ strs(v2, Address(__ pre(r25, -91))); // str s2, [x25, -91]!
|
|
|
|
// post
|
|
// LoadStoreOp
|
|
__ str(r10, Address(__ post(r13, -21))); // str x10, [x13], -21
|
|
__ strw(r7, Address(__ post(r1, 50))); // str w7, [x1], 50
|
|
__ strb(r10, Address(__ post(r3, 5))); // strb w10, [x3], 5
|
|
__ strh(r5, Address(__ post(r6, -33))); // strh w5, [x6], -33
|
|
__ ldr(r13, Address(__ post(r22, -158))); // ldr x13, [x22], -158
|
|
__ ldrw(r13, Address(__ post(r2, -106))); // ldr w13, [x2], -106
|
|
__ ldrb(r13, Address(__ post(r16, -24))); // ldrb w13, [x16], -24
|
|
__ ldrh(r24, Address(__ post(r2, -22))); // ldrh w24, [x2], -22
|
|
__ ldrsb(r3, Address(__ post(r23, -1))); // ldrsb x3, [x23], -1
|
|
__ ldrsh(r19, Address(__ post(r8, -43))); // ldrsh x19, [x8], -43
|
|
__ ldrshw(r2, Address(__ post(r23, -8))); // ldrsh w2, [x23], -8
|
|
__ ldrsw(r19, Address(__ post(r28, -87))); // ldrsw x19, [x28], -87
|
|
__ ldrd(v15, Address(__ post(r3, -81))); // ldr d15, [x3], -81
|
|
__ ldrs(v12, Address(__ post(r29, -79))); // ldr s12, [x29], -79
|
|
__ strd(v21, Address(__ post(r1, -124))); // str d21, [x1], -124
|
|
__ strs(v7, Address(__ post(r9, -99))); // str s7, [x9], -99
|
|
|
|
// base_plus_reg
|
|
// LoadStoreOp
|
|
__ str(r5, Address(r20, r2, Address::lsl(0))); // str x5, [x20, x2, lsl #0]
|
|
__ strw(r14, Address(r10, r30, Address::sxtw(2))); // str w14, [x10, w30, sxtw #2]
|
|
__ strb(r4, Address(r1, r28, Address::sxtw(0))); // strb w4, [x1, w28, sxtw #0]
|
|
__ strh(r5, Address(r10, r26, Address::sxtx(1))); // strh w5, [x10, x26, sxtx #1]
|
|
__ ldr(r22, Address(r2, r28, Address::lsl(3))); // ldr x22, [x2, x28, lsl #3]
|
|
__ ldrw(r12, Address(r0, r28, Address::lsl(2))); // ldr w12, [x0, x28, lsl #2]
|
|
__ ldrb(r8, Address(r8, r15, Address::sxtx(0))); // ldrb w8, [x8, x15, sxtx #0]
|
|
__ ldrh(r17, Address(r21, r14, Address::uxtw(1))); // ldrh w17, [x21, w14, uxtw #1]
|
|
__ ldrsb(r17, Address(r24, r8, Address::sxtx(0))); // ldrsb x17, [x24, x8, sxtx #0]
|
|
__ ldrsh(r10, Address(r10, r30, Address::sxtx(1))); // ldrsh x10, [x10, x30, sxtx #1]
|
|
__ ldrshw(r17, Address(r23, r0, Address::lsl(1))); // ldrsh w17, [x23, x0, lsl #1]
|
|
__ ldrsw(r25, Address(r30, r0, Address::lsl(2))); // ldrsw x25, [x30, x0, lsl #2]
|
|
__ ldrd(v5, Address(r24, r23, Address::uxtw(3))); // ldr d5, [x24, w23, uxtw #3]
|
|
__ ldrs(v22, Address(r3, r15, Address::lsl(2))); // ldr s22, [x3, x15, lsl #2]
|
|
__ strd(v4, Address(r29, r16, Address::sxtx(3))); // str d4, [x29, x16, sxtx #3]
|
|
__ strs(v7, Address(r20, r28, Address::sxtw(2))); // str s7, [x20, w28, sxtw #2]
|
|
|
|
// base_plus_scaled_offset
|
|
// LoadStoreOp
|
|
__ str(r27, Address(r0, 16360)); // str x27, [x0, 16360]
|
|
__ strw(r21, Address(r8, 7984)); // str w21, [x8, 7984]
|
|
__ strb(r17, Address(r29, 1795)); // strb w17, [x29, 1795]
|
|
__ strh(r27, Address(r2, 3636)); // strh w27, [x2, 3636]
|
|
__ ldr(r1, Address(r1, 12480)); // ldr x1, [x1, 12480]
|
|
__ ldrw(r29, Address(r17, 6320)); // ldr w29, [x17, 6320]
|
|
__ ldrb(r1, Address(r9, 1634)); // ldrb w1, [x9, 1634]
|
|
__ ldrh(r23, Address(r3, 3736)); // ldrh w23, [x3, 3736]
|
|
__ ldrsb(r21, Address(r19, 1857)); // ldrsb x21, [x19, 1857]
|
|
__ ldrsh(r19, Address(r7, 3180)); // ldrsh x19, [x7, 3180]
|
|
__ ldrshw(r10, Address(r1, 3560)); // ldrsh w10, [x1, 3560]
|
|
__ ldrsw(r10, Address(r20, 7428)); // ldrsw x10, [x20, 7428]
|
|
__ ldrd(v0, Address(r13, 14880)); // ldr d0, [x13, 14880]
|
|
__ ldrs(v11, Address(r27, 6356)); // ldr s11, [x27, 6356]
|
|
__ strd(v13, Address(r25, 13704)); // str d13, [x25, 13704]
|
|
__ strs(v20, Address(r0, 7580)); // str s20, [x0, 7580]
|
|
|
|
// pcrel
|
|
// LoadStoreOp
|
|
__ ldr(r26, __ pc()); // ldr x26, .
|
|
__ ldrw(r19, back); // ldr w19, back
|
|
|
|
// LoadStoreOp
|
|
__ prfm(Address(r8, -111)); // prfm PLDL1KEEP, [x8, -111]
|
|
|
|
// LoadStoreOp
|
|
__ prfm(forth); // prfm PLDL1KEEP, forth
|
|
|
|
// LoadStoreOp
|
|
__ prfm(Address(r7, r7, Address::uxtw(3))); // prfm PLDL1KEEP, [x7, w7, uxtw #3]
|
|
|
|
// LoadStoreOp
|
|
__ prfm(Address(r12, 12600)); // prfm PLDL1KEEP, [x12, 12600]
|
|
|
|
// AddSubCarryOp
|
|
__ adcw(r24, r20, r11); // adc w24, w20, w11
|
|
__ adcsw(r0, r13, r28); // adcs w0, w13, w28
|
|
__ sbcw(r10, r7, r4); // sbc w10, w7, w4
|
|
__ sbcsw(r15, r16, r2); // sbcs w15, w16, w2
|
|
__ adc(r12, r20, r29); // adc x12, x20, x29
|
|
__ adcs(r13, r13, r14); // adcs x13, x13, x14
|
|
__ sbc(r6, r12, r20); // sbc x6, x12, x20
|
|
__ sbcs(r12, r17, r25); // sbcs x12, x17, x25
|
|
|
|
// AddSubExtendedOp
|
|
__ addw(r30, r27, r11, ext::sxtb, 1); // add w30, w27, w11, sxtb #1
|
|
__ addsw(r14, r7, r1, ext::sxtw, 2); // adds w14, w7, w1, sxtw #2
|
|
__ sub(r29, r3, r27, ext::sxth, 1); // sub x29, x3, x27, sxth #1
|
|
__ subsw(r0, r13, r26, ext::sxtx, 2); // subs w0, w13, w26, sxtx #2
|
|
__ add(r22, r17, r5, ext::uxtx, 2); // add x22, x17, x5, uxtx #2
|
|
__ adds(r17, r30, r8, ext::sxtx, 3); // adds x17, x30, x8, sxtx #3
|
|
__ sub(r10, r19, r23, ext::sxtw, 3); // sub x10, x19, x23, sxtw #3
|
|
__ subs(r6, r29, r5, ext::uxtw, 3); // subs x6, x29, x5, uxtw #3
|
|
|
|
// ConditionalCompareOp
|
|
__ ccmnw(r19, r9, 4u, Assembler::HI); // ccmn w19, w9, #4, HI
|
|
__ ccmpw(r22, r10, 2u, Assembler::VC); // ccmp w22, w10, #2, VC
|
|
__ ccmn(r13, r12, 10u, Assembler::LS); // ccmn x13, x12, #10, LS
|
|
__ ccmp(r24, r16, 3u, Assembler::HS); // ccmp x24, x16, #3, HS
|
|
|
|
// ConditionalCompareImmedOp
|
|
__ ccmnw(r7, 11, 13, Assembler::VS); // ccmn w7, #11, #13, VS
|
|
__ ccmpw(r27, 10, 11, Assembler::LS); // ccmp w27, #10, #11, LS
|
|
__ ccmn(r3, 13, 13, Assembler::LE); // ccmn x3, #13, #13, LE
|
|
__ ccmp(r26, 16, 5, Assembler::GT); // ccmp x26, #16, #5, GT
|
|
|
|
// ConditionalSelectOp
|
|
__ cselw(r10, r21, r28, Assembler::LE); // csel w10, w21, w28, LE
|
|
__ csincw(r23, r9, r27, Assembler::LE); // csinc w23, w9, w27, LE
|
|
__ csinvw(r10, r29, r15, Assembler::LE); // csinv w10, w29, w15, LE
|
|
__ csnegw(r30, r25, r21, Assembler::HS); // csneg w30, w25, w21, HS
|
|
__ csel(r0, r17, r21, Assembler::GT); // csel x0, x17, x21, GT
|
|
__ csinc(r16, r21, r20, Assembler::CS); // csinc x16, x21, x20, CS
|
|
__ csinv(r19, r30, r3, Assembler::LS); // csinv x19, x30, x3, LS
|
|
__ csneg(r19, r11, r24, Assembler::EQ); // csneg x19, x11, x24, EQ
|
|
|
|
// TwoRegOp
|
|
__ rbitw(r27, r25); // rbit w27, w25
|
|
__ rev16w(r14, r3); // rev16 w14, w3
|
|
__ revw(r14, r17); // rev w14, w17
|
|
__ clzw(r7, r15); // clz w7, w15
|
|
__ clsw(r24, r28); // cls w24, w28
|
|
__ rbit(r17, r25); // rbit x17, x25
|
|
__ rev16(r2, r26); // rev16 x2, x26
|
|
__ rev32(r28, r5); // rev32 x28, x5
|
|
__ rev(r25, r26); // rev x25, x26
|
|
__ clz(r27, r16); // clz x27, x16
|
|
__ cls(r17, r6); // cls x17, x6
|
|
__ pacia(r21, r12); // pacia x21, x12
|
|
__ pacib(r0, r4); // pacib x0, x4
|
|
__ pacda(r12, r27); // pacda x12, x27
|
|
__ pacdb(r17, r28); // pacdb x17, x28
|
|
__ autia(r28, r2); // autia x28, x2
|
|
__ autib(r17, r10); // autib x17, x10
|
|
__ autda(r15, r14); // autda x15, x14
|
|
__ autdb(r14, r3); // autdb x14, x3
|
|
__ braa(r25, r15); // braa x25, x15
|
|
__ brab(r19, r14); // brab x19, x14
|
|
__ blraa(r5, r16); // blraa x5, x16
|
|
__ blrab(r4, r26); // blrab x4, x26
|
|
|
|
// ThreeRegOp
|
|
__ udivw(r25, r4, r2); // udiv w25, w4, w2
|
|
__ sdivw(r2, r12, r29); // sdiv w2, w12, w29
|
|
__ lslvw(r17, r8, r7); // lslv w17, w8, w7
|
|
__ lsrvw(r3, r4, r25); // lsrv w3, w4, w25
|
|
__ asrvw(r4, r26, r25); // asrv w4, w26, w25
|
|
__ rorvw(r4, r17, r0); // rorv w4, w17, w0
|
|
__ udiv(r26, r17, r23); // udiv x26, x17, x23
|
|
__ sdiv(r15, r21, r28); // sdiv x15, x21, x28
|
|
__ lslv(r17, r27, r10); // lslv x17, x27, x10
|
|
__ lsrv(r3, r0, r7); // lsrv x3, x0, x7
|
|
__ asrv(r25, r9, r6); // asrv x25, x9, x6
|
|
__ rorv(r15, r29, r15); // rorv x15, x29, x15
|
|
__ umulh(r10, r2, r17); // umulh x10, x2, x17
|
|
__ smulh(r7, r11, r11); // smulh x7, x11, x11
|
|
|
|
// FourRegMulOp
|
|
__ maddw(r23, r7, r29, r23); // madd w23, w7, w29, w23
|
|
__ msubw(r14, r27, r11, r11); // msub w14, w27, w11, w11
|
|
__ madd(r4, r24, r12, r15); // madd x4, x24, x12, x15
|
|
__ msub(r14, r20, r11, r28); // msub x14, x20, x11, x28
|
|
__ smaddl(r13, r11, r12, r23); // smaddl x13, w11, w12, x23
|
|
__ smsubl(r30, r26, r14, r9); // smsubl x30, w26, w14, x9
|
|
__ umaddl(r13, r10, r7, r5); // umaddl x13, w10, w7, x5
|
|
__ umsubl(r29, r15, r3, r11); // umsubl x29, w15, w3, x11
|
|
|
|
// ThreeRegFloatOp
|
|
__ fabdh(v12, v16, v31); // fabd h12, h16, h31
|
|
__ fmulh(v31, v18, v19); // fmul h31, h18, h19
|
|
__ fdivh(v21, v16, v15); // fdiv h21, h16, h15
|
|
__ faddh(v10, v21, v2); // fadd h10, h21, h2
|
|
__ fsubh(v10, v28, v7); // fsub h10, h28, h7
|
|
__ fmaxh(v30, v31, v18); // fmax h30, h31, h18
|
|
__ fminh(v1, v2, v6); // fmin h1, h2, h6
|
|
__ fnmulh(v10, v3, v25); // fnmul h10, h3, h25
|
|
__ fabds(v11, v7, v1); // fabd s11, s7, s1
|
|
__ fmuls(v12, v0, v3); // fmul s12, s0, s3
|
|
__ fdivs(v19, v29, v6); // fdiv s19, s29, s6
|
|
__ fadds(v23, v6, v0); // fadd s23, s6, s0
|
|
__ fsubs(v28, v27, v2); // fsub s28, s27, s2
|
|
__ fmaxs(v5, v7, v29); // fmax s5, s7, s29
|
|
__ fmins(v12, v25, v13); // fmin s12, s25, s13
|
|
__ fnmuls(v12, v24, v19); // fnmul s12, s24, s19
|
|
__ fabdd(v8, v18, v22); // fabd d8, d18, d22
|
|
__ fmuld(v26, v21, v20); // fmul d26, d21, d20
|
|
__ fdivd(v19, v2, v30); // fdiv d19, d2, d30
|
|
__ faddd(v22, v8, v22); // fadd d22, d8, d22
|
|
__ fsubd(v19, v21, v12); // fsub d19, d21, d12
|
|
__ fmaxd(v18, v21, v6); // fmax d18, d21, d6
|
|
__ fmind(v16, v3, v3); // fmin d16, d3, d3
|
|
__ fnmuld(v29, v3, v28); // fnmul d29, d3, d28
|
|
|
|
// FourRegFloatOp
|
|
__ fmaddh(v15, v14, v10, v13); // fmadd h15, h14, h10, h13
|
|
__ fmadds(v12, v18, v10, v26); // fmadd s12, s18, s10, s26
|
|
__ fmsubs(v7, v7, v15, v29); // fmsub s7, s7, s15, s29
|
|
__ fnmadds(v0, v23, v0, v12); // fnmadd s0, s23, s0, s12
|
|
__ fnmadds(v24, v14, v13, v8); // fnmadd s24, s14, s13, s8
|
|
__ fmaddd(v15, v7, v9, v20); // fmadd d15, d7, d9, d20
|
|
__ fmsubd(v19, v29, v31, v16); // fmsub d19, d29, d31, d16
|
|
__ fnmaddd(v2, v9, v16, v21); // fnmadd d2, d9, d16, d21
|
|
__ fnmaddd(v30, v4, v1, v27); // fnmadd d30, d4, d1, d27
|
|
|
|
// TwoRegFloatOp
|
|
__ fmovs(v25, v24); // fmov s25, s24
|
|
__ fabss(v14, v21); // fabs s14, s21
|
|
__ fnegs(v13, v6); // fneg s13, s6
|
|
__ fsqrts(v12, v25); // fsqrt s12, s25
|
|
__ fcvts(v25, v30); // fcvt d25, s30
|
|
__ fcvtsh(v28, v21); // fcvt h28, s21
|
|
__ fcvths(v16, v23); // fcvt s16, h23
|
|
__ fmovd(v5, v29); // fmov d5, d29
|
|
__ fabsd(v22, v19); // fabs d22, d19
|
|
__ fnegd(v13, v20); // fneg d13, d20
|
|
__ fsqrtd(v19, v28); // fsqrt d19, d28
|
|
__ fcvtd(v18, v6); // fcvt s18, d6
|
|
__ fsqrth(v14, v7); // fsqrt h14, h7
|
|
|
|
// FloatConvertOp
|
|
__ fcvtzsw(r28, v26); // fcvtzs w28, s26
|
|
__ fcvtzs(r17, v6); // fcvtzs x17, s6
|
|
__ fcvtzdw(r1, v4); // fcvtzs w1, d4
|
|
__ fcvtzd(r13, v21); // fcvtzs x13, d21
|
|
__ scvtfws(v7, r21); // scvtf s7, w21
|
|
__ scvtfs(v27, r23); // scvtf s27, x23
|
|
__ scvtfwd(v13, r20); // scvtf d13, w20
|
|
__ scvtfd(v31, r27); // scvtf d31, x27
|
|
__ fcvtassw(r10, v21); // fcvtas w10, s21
|
|
__ fcvtasd(r5, v17); // fcvtas x5, d17
|
|
__ fcvtmssw(r11, v14); // fcvtms w11, s14
|
|
__ fcvtmsd(r13, v21); // fcvtms x13, d21
|
|
__ fmovs(r26, v14); // fmov w26, s14
|
|
__ fmovd(r4, v24); // fmov x4, d24
|
|
__ fmovs(v24, r29); // fmov s24, w29
|
|
__ fmovd(v12, r14); // fmov d12, x14
|
|
|
|
// TwoRegFloatOp
|
|
__ fcmps(v17, v28); // fcmp s17, s28
|
|
__ fcmpd(v22, v0); // fcmp d22, d0
|
|
__ fcmps(v6, 0.0); // fcmp s6, #0.0
|
|
__ fcmpd(v27, 0.0); // fcmp d27, #0.0
|
|
|
|
// LoadStorePairOp
|
|
__ stpw(r27, r12, Address(r6, -32)); // stp w27, w12, [x6, #-32]
|
|
__ ldpw(r14, r11, Address(r19, -256)); // ldp w14, w11, [x19, #-256]
|
|
__ ldpsw(r0, r12, Address(r15, -48)); // ldpsw x0, x12, [x15, #-48]
|
|
__ stp(r9, r23, Address(r23, 32)); // stp x9, x23, [x23, #32]
|
|
__ ldp(r15, r4, Address(r26, -176)); // ldp x15, x4, [x26, #-176]
|
|
|
|
// LoadStorePairOp
|
|
__ stpw(r17, r8, Address(__ pre(r6, -160))); // stp w17, w8, [x6, #-160]!
|
|
__ ldpw(r7, r2, Address(__ pre(r4, -112))); // ldp w7, w2, [x4, #-112]!
|
|
__ ldpsw(r14, r9, Address(__ pre(r22, -16))); // ldpsw x14, x9, [x22, #-16]!
|
|
__ stp(r13, r20, Address(__ pre(r24, -256))); // stp x13, x20, [x24, #-256]!
|
|
__ ldp(r8, r11, Address(__ pre(r10, 96))); // ldp x8, x11, [x10, #96]!
|
|
|
|
// LoadStorePairOp
|
|
__ stpw(r24, r5, Address(__ post(r16, -112))); // stp w24, w5, [x16], #-112
|
|
__ ldpw(r0, r26, Address(__ post(r9, -128))); // ldp w0, w26, [x9], #-128
|
|
__ ldpsw(r24, r2, Address(__ post(r17, -128))); // ldpsw x24, x2, [x17], #-128
|
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__ stp(r26, r17, Address(__ post(r14, -48))); // stp x26, x17, [x14], #-48
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__ ldp(r30, r21, Address(__ post(r29, 48))); // ldp x30, x21, [x29], #48
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// LoadStorePairOp
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__ stnpw(r17, r23, Address(r10, -112)); // stnp w17, w23, [x10, #-112]
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__ ldnpw(r26, r6, Address(r30, -160)); // ldnp w26, w6, [x30, #-160]
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__ stnp(r30, r8, Address(r20, 64)); // stnp x30, x8, [x20, #64]
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__ ldnp(r22, r29, Address(r9, 48)); // ldnp x22, x29, [x9, #48]
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// LdStNEONOp
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__ ld1(v13, __ T8B, Address(r1)); // ld1 {v13.8B}, [x1]
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__ ld1(v1, v2, __ T16B, Address(__ post(r16, 32))); // ld1 {v1.16B, v2.16B}, [x16], 32
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__ ld1(v22, v23, v24, __ T1D, Address(__ post(r25, r19))); // ld1 {v22.1D, v23.1D, v24.1D}, [x25], x19
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__ ld1(v25, v26, v27, v28, __ T8H, Address(__ post(r26, 64))); // ld1 {v25.8H, v26.8H, v27.8H, v28.8H}, [x26], 64
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__ ld1r(v9, __ T8B, Address(r15)); // ld1r {v9.8B}, [x15]
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__ ld1r(v12, __ T4S, Address(__ post(r25, 4))); // ld1r {v12.4S}, [x25], 4
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__ ld1r(v4, __ T1D, Address(__ post(r14, r29))); // ld1r {v4.1D}, [x14], x29
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__ ld2(v17, v18, __ T2D, Address(r17)); // ld2 {v17.2D, v18.2D}, [x17]
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__ ld2(v23, v24, __ T4H, Address(__ post(r27, 16))); // ld2 {v23.4H, v24.4H}, [x27], 16
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__ ld2r(v2, v3, __ T16B, Address(r24)); // ld2r {v2.16B, v3.16B}, [x24]
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__ ld2r(v11, v12, __ T2S, Address(__ post(r0, 8))); // ld2r {v11.2S, v12.2S}, [x0], 8
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__ ld2r(v2, v3, __ T2D, Address(__ post(r12, r22))); // ld2r {v2.2D, v3.2D}, [x12], x22
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__ ld3(v21, v22, v23, __ T4S, Address(__ post(r13, r13))); // ld3 {v21.4S, v22.4S, v23.4S}, [x13], x13
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__ ld3(v12, v13, v14, __ T2S, Address(r11)); // ld3 {v12.2S, v13.2S, v14.2S}, [x11]
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__ ld3r(v18, v19, v20, __ T8H, Address(r14)); // ld3r {v18.8H, v19.8H, v20.8H}, [x14]
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__ ld3r(v25, v26, v27, __ T4S, Address(__ post(r21, 12))); // ld3r {v25.4S, v26.4S, v27.4S}, [x21], 12
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__ ld3r(v20, v21, v22, __ T1D, Address(__ post(r16, r27))); // ld3r {v20.1D, v21.1D, v22.1D}, [x16], x27
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__ ld4(v0, v1, v2, v3, __ T8H, Address(__ post(r1, 64))); // ld4 {v0.8H, v1.8H, v2.8H, v3.8H}, [x1], 64
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__ ld4(v0, v1, v2, v3, __ T8B, Address(__ post(r27, r29))); // ld4 {v0.8B, v1.8B, v2.8B, v3.8B}, [x27], x29
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__ ld4r(v18, v19, v20, v21, __ T8B, Address(r17)); // ld4r {v18.8B, v19.8B, v20.8B, v21.8B}, [x17]
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__ ld4r(v5, v6, v7, v8, __ T4H, Address(__ post(r24, 8))); // ld4r {v5.4H, v6.4H, v7.4H, v8.4H}, [x24], 8
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__ ld4r(v28, v29, v30, v31, __ T2S, Address(__ post(r5, r20))); // ld4r {v28.2S, v29.2S, v30.2S, v31.2S}, [x5], x20
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// NEONReduceInstruction
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__ addv(v1, __ T8B, v2); // addv b1, v2.8B
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__ addv(v20, __ T16B, v21); // addv b20, v21.16B
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__ addv(v29, __ T4H, v30); // addv h29, v30.4H
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__ addv(v16, __ T8H, v17); // addv h16, v17.8H
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__ addv(v13, __ T4S, v14); // addv s13, v14.4S
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__ smaxv(v10, __ T8B, v11); // smaxv b10, v11.8B
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__ smaxv(v29, __ T16B, v30); // smaxv b29, v30.16B
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__ smaxv(v29, __ T4H, v30); // smaxv h29, v30.4H
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__ smaxv(v19, __ T8H, v20); // smaxv h19, v20.8H
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__ smaxv(v22, __ T4S, v23); // smaxv s22, v23.4S
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__ fmaxv(v10, __ T4S, v11); // fmaxv s10, v11.4S
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__ sminv(v4, __ T8B, v5); // sminv b4, v5.8B
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__ uminv(v31, __ T8B, v0); // uminv b31, v0.8B
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__ sminv(v21, __ T16B, v22); // sminv b21, v22.16B
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__ uminv(v8, __ T16B, v9); // uminv b8, v9.16B
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__ sminv(v31, __ T4H, v0); // sminv h31, v0.4H
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__ uminv(v19, __ T4H, v20); // uminv h19, v20.4H
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__ sminv(v10, __ T8H, v11); // sminv h10, v11.8H
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__ uminv(v28, __ T8H, v29); // uminv h28, v29.8H
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__ sminv(v2, __ T4S, v3); // sminv s2, v3.4S
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__ uminv(v25, __ T4S, v26); // uminv s25, v26.4S
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__ fminv(v5, __ T4S, v6); // fminv s5, v6.4S
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__ fmaxp(v3, v4, __ S); // fmaxp s3, v4.2S
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__ fmaxp(v8, v9, __ D); // fmaxp d8, v9.2D
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__ fminp(v22, v23, __ S); // fminp s22, v23.2S
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__ fminp(v19, v20, __ D); // fminp d19, v20.2D
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// NEONFloatCompareWithZero
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__ fcm(Assembler::GT, v13, __ T2S, v14); // fcmgt v13.2S, v14.2S, #0.0
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__ fcm(Assembler::GT, v5, __ T4S, v6); // fcmgt v5.4S, v6.4S, #0.0
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__ fcm(Assembler::GT, v29, __ T2D, v30); // fcmgt v29.2D, v30.2D, #0.0
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__ fcm(Assembler::GE, v24, __ T2S, v25); // fcmge v24.2S, v25.2S, #0.0
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__ fcm(Assembler::GE, v21, __ T4S, v22); // fcmge v21.4S, v22.4S, #0.0
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__ fcm(Assembler::GE, v26, __ T2D, v27); // fcmge v26.2D, v27.2D, #0.0
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__ fcm(Assembler::EQ, v24, __ T2S, v25); // fcmeq v24.2S, v25.2S, #0.0
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__ fcm(Assembler::EQ, v3, __ T4S, v4); // fcmeq v3.4S, v4.4S, #0.0
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__ fcm(Assembler::EQ, v24, __ T2D, v25); // fcmeq v24.2D, v25.2D, #0.0
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__ fcm(Assembler::LT, v26, __ T2S, v27); // fcmlt v26.2S, v27.2S, #0.0
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__ fcm(Assembler::LT, v23, __ T4S, v24); // fcmlt v23.4S, v24.4S, #0.0
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__ fcm(Assembler::LT, v15, __ T2D, v16); // fcmlt v15.2D, v16.2D, #0.0
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__ fcm(Assembler::LE, v21, __ T2S, v22); // fcmle v21.2S, v22.2S, #0.0
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__ fcm(Assembler::LE, v3, __ T4S, v4); // fcmle v3.4S, v4.4S, #0.0
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__ fcm(Assembler::LE, v24, __ T2D, v25); // fcmle v24.2D, v25.2D, #0.0
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// TwoRegNEONOp
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__ absr(v8, __ T8B, v9); // abs v8.8B, v9.8B
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__ absr(v25, __ T16B, v26); // abs v25.16B, v26.16B
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__ absr(v20, __ T4H, v21); // abs v20.4H, v21.4H
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__ absr(v16, __ T8H, v17); // abs v16.8H, v17.8H
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__ absr(v17, __ T2S, v18); // abs v17.2S, v18.2S
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__ absr(v2, __ T4S, v3); // abs v2.4S, v3.4S
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__ absr(v1, __ T2D, v2); // abs v1.2D, v2.2D
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__ fabs(v0, __ T2S, v1); // fabs v0.2S, v1.2S
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__ fabs(v24, __ T4S, v25); // fabs v24.4S, v25.4S
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__ fabs(v4, __ T2D, v5); // fabs v4.2D, v5.2D
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__ fabs(v3, __ T4H, v4); // fabs v3.4H, v4.4H
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__ fabs(v12, __ T8H, v13); // fabs v12.8H, v13.8H
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__ fneg(v31, __ T2S, v0); // fneg v31.2S, v0.2S
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__ fneg(v28, __ T4S, v29); // fneg v28.4S, v29.4S
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__ fneg(v10, __ T2D, v11); // fneg v10.2D, v11.2D
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__ fneg(v26, __ T4H, v27); // fneg v26.4H, v27.4H
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__ fneg(v2, __ T8H, v3); // fneg v2.8H, v3.8H
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__ fsqrt(v12, __ T2S, v13); // fsqrt v12.2S, v13.2S
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__ fsqrt(v18, __ T4S, v19); // fsqrt v18.4S, v19.4S
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__ fsqrt(v31, __ T2D, v0); // fsqrt v31.2D, v0.2D
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__ fsqrt(v1, __ T4H, v2); // fsqrt v1.4H, v2.4H
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__ fsqrt(v13, __ T8H, v14); // fsqrt v13.8H, v14.8H
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__ notr(v29, __ T8B, v30); // not v29.8B, v30.8B
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__ notr(v0, __ T16B, v1); // not v0.16B, v1.16B
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// ThreeRegNEONOp
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__ andr(v19, __ T8B, v20, v21); // and v19.8B, v20.8B, v21.8B
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__ andr(v12, __ T16B, v13, v14); // and v12.16B, v13.16B, v14.16B
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__ orr(v17, __ T8B, v18, v19); // orr v17.8B, v18.8B, v19.8B
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__ orr(v22, __ T16B, v23, v24); // orr v22.16B, v23.16B, v24.16B
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__ eor(v13, __ T8B, v14, v15); // eor v13.8B, v14.8B, v15.8B
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__ eor(v28, __ T16B, v29, v30); // eor v28.16B, v29.16B, v30.16B
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__ addv(v30, __ T8B, v31, v0); // add v30.8B, v31.8B, v0.8B
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__ addv(v31, __ T16B, v0, v1); // add v31.16B, v0.16B, v1.16B
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__ addv(v1, __ T4H, v2, v3); // add v1.4H, v2.4H, v3.4H
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__ addv(v26, __ T8H, v27, v28); // add v26.8H, v27.8H, v28.8H
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__ addv(v28, __ T2S, v29, v30); // add v28.2S, v29.2S, v30.2S
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__ addv(v4, __ T4S, v5, v6); // add v4.4S, v5.4S, v6.4S
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__ addv(v30, __ T2D, v31, v0); // add v30.2D, v31.2D, v0.2D
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__ sqaddv(v4, __ T8B, v5, v6); // sqadd v4.8B, v5.8B, v6.8B
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__ sqaddv(v6, __ T16B, v7, v8); // sqadd v6.16B, v7.16B, v8.16B
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__ sqaddv(v30, __ T4H, v31, v0); // sqadd v30.4H, v31.4H, v0.4H
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__ sqaddv(v26, __ T8H, v27, v28); // sqadd v26.8H, v27.8H, v28.8H
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__ sqaddv(v18, __ T2S, v19, v20); // sqadd v18.2S, v19.2S, v20.2S
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__ sqaddv(v9, __ T4S, v10, v11); // sqadd v9.4S, v10.4S, v11.4S
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__ sqaddv(v8, __ T2D, v9, v10); // sqadd v8.2D, v9.2D, v10.2D
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__ uqaddv(v12, __ T8B, v13, v14); // uqadd v12.8B, v13.8B, v14.8B
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__ uqaddv(v0, __ T16B, v1, v2); // uqadd v0.16B, v1.16B, v2.16B
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__ uqaddv(v20, __ T4H, v21, v22); // uqadd v20.4H, v21.4H, v22.4H
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__ uqaddv(v1, __ T8H, v2, v3); // uqadd v1.8H, v2.8H, v3.8H
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__ uqaddv(v24, __ T2S, v25, v26); // uqadd v24.2S, v25.2S, v26.2S
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__ uqaddv(v2, __ T4S, v3, v4); // uqadd v2.4S, v3.4S, v4.4S
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__ uqaddv(v0, __ T2D, v1, v2); // uqadd v0.2D, v1.2D, v2.2D
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__ fadd(v9, __ T2S, v10, v11); // fadd v9.2S, v10.2S, v11.2S
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__ fadd(v24, __ T4S, v25, v26); // fadd v24.4S, v25.4S, v26.4S
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__ fadd(v26, __ T2D, v27, v28); // fadd v26.2D, v27.2D, v28.2D
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__ fadd(v16, __ T4H, v17, v18); // fadd v16.4H, v17.4H, v18.4H
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__ fadd(v30, __ T8H, v31, v0); // fadd v30.8H, v31.8H, v0.8H
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__ subv(v3, __ T8B, v4, v5); // sub v3.8B, v4.8B, v5.8B
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__ subv(v10, __ T16B, v11, v12); // sub v10.16B, v11.16B, v12.16B
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__ subv(v23, __ T4H, v24, v25); // sub v23.4H, v24.4H, v25.4H
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__ subv(v10, __ T8H, v11, v12); // sub v10.8H, v11.8H, v12.8H
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__ subv(v4, __ T2S, v5, v6); // sub v4.2S, v5.2S, v6.2S
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__ subv(v18, __ T4S, v19, v20); // sub v18.4S, v19.4S, v20.4S
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__ subv(v2, __ T2D, v3, v4); // sub v2.2D, v3.2D, v4.2D
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__ sqsubv(v11, __ T8B, v12, v13); // sqsub v11.8B, v12.8B, v13.8B
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__ sqsubv(v8, __ T16B, v9, v10); // sqsub v8.16B, v9.16B, v10.16B
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__ sqsubv(v10, __ T4H, v11, v12); // sqsub v10.4H, v11.4H, v12.4H
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__ sqsubv(v15, __ T8H, v16, v17); // sqsub v15.8H, v16.8H, v17.8H
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__ sqsubv(v17, __ T2S, v18, v19); // sqsub v17.2S, v18.2S, v19.2S
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__ sqsubv(v2, __ T4S, v3, v4); // sqsub v2.4S, v3.4S, v4.4S
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__ sqsubv(v10, __ T2D, v11, v12); // sqsub v10.2D, v11.2D, v12.2D
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__ uqsubv(v12, __ T8B, v13, v14); // uqsub v12.8B, v13.8B, v14.8B
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__ uqsubv(v12, __ T16B, v13, v14); // uqsub v12.16B, v13.16B, v14.16B
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__ uqsubv(v15, __ T4H, v16, v17); // uqsub v15.4H, v16.4H, v17.4H
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__ uqsubv(v13, __ T8H, v14, v15); // uqsub v13.8H, v14.8H, v15.8H
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__ uqsubv(v2, __ T2S, v3, v4); // uqsub v2.2S, v3.2S, v4.2S
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__ uqsubv(v7, __ T4S, v8, v9); // uqsub v7.4S, v8.4S, v9.4S
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__ uqsubv(v20, __ T2D, v21, v22); // uqsub v20.2D, v21.2D, v22.2D
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__ fsub(v26, __ T2S, v27, v28); // fsub v26.2S, v27.2S, v28.2S
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__ fsub(v16, __ T4S, v17, v18); // fsub v16.4S, v17.4S, v18.4S
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__ fsub(v4, __ T2D, v5, v6); // fsub v4.2D, v5.2D, v6.2D
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__ fsub(v2, __ T4H, v3, v4); // fsub v2.4H, v3.4H, v4.4H
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__ fsub(v4, __ T8H, v5, v6); // fsub v4.8H, v5.8H, v6.8H
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__ mulv(v12, __ T8B, v13, v14); // mul v12.8B, v13.8B, v14.8B
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__ mulv(v18, __ T16B, v19, v20); // mul v18.16B, v19.16B, v20.16B
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__ mulv(v21, __ T4H, v22, v23); // mul v21.4H, v22.4H, v23.4H
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__ mulv(v16, __ T8H, v17, v18); // mul v16.8H, v17.8H, v18.8H
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__ mulv(v18, __ T2S, v19, v20); // mul v18.2S, v19.2S, v20.2S
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__ mulv(v11, __ T4S, v12, v13); // mul v11.4S, v12.4S, v13.4S
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__ fabd(v21, __ T2S, v22, v23); // fabd v21.2S, v22.2S, v23.2S
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__ fabd(v23, __ T4S, v24, v25); // fabd v23.4S, v24.4S, v25.4S
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__ fabd(v12, __ T2D, v13, v14); // fabd v12.2D, v13.2D, v14.2D
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__ fabd(v26, __ T4H, v27, v28); // fabd v26.4H, v27.4H, v28.4H
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__ fabd(v23, __ T8H, v24, v25); // fabd v23.8H, v24.8H, v25.8H
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__ faddp(v28, __ T2S, v29, v30); // faddp v28.2S, v29.2S, v30.2S
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__ faddp(v14, __ T4S, v15, v16); // faddp v14.4S, v15.4S, v16.4S
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__ faddp(v11, __ T2D, v12, v13); // faddp v11.2D, v12.2D, v13.2D
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__ faddp(v24, __ T4H, v25, v26); // faddp v24.4H, v25.4H, v26.4H
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__ faddp(v1, __ T8H, v2, v3); // faddp v1.8H, v2.8H, v3.8H
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__ fmul(v12, __ T2S, v13, v14); // fmul v12.2S, v13.2S, v14.2S
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__ fmul(v31, __ T4S, v0, v1); // fmul v31.4S, v0.4S, v1.4S
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__ fmul(v10, __ T2D, v11, v12); // fmul v10.2D, v11.2D, v12.2D
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__ fmul(v16, __ T4H, v17, v18); // fmul v16.4H, v17.4H, v18.4H
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__ fmul(v7, __ T8H, v8, v9); // fmul v7.8H, v8.8H, v9.8H
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__ mlav(v2, __ T4H, v3, v4); // mla v2.4H, v3.4H, v4.4H
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__ mlav(v3, __ T8H, v4, v5); // mla v3.8H, v4.8H, v5.8H
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__ mlav(v13, __ T2S, v14, v15); // mla v13.2S, v14.2S, v15.2S
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__ mlav(v19, __ T4S, v20, v21); // mla v19.4S, v20.4S, v21.4S
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__ fmla(v17, __ T2S, v18, v19); // fmla v17.2S, v18.2S, v19.2S
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__ fmla(v16, __ T4S, v17, v18); // fmla v16.4S, v17.4S, v18.4S
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__ fmla(v3, __ T2D, v4, v5); // fmla v3.2D, v4.2D, v5.2D
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__ fmla(v1, __ T4H, v2, v3); // fmla v1.4H, v2.4H, v3.4H
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__ fmla(v11, __ T8H, v12, v13); // fmla v11.8H, v12.8H, v13.8H
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__ mlsv(v30, __ T4H, v31, v0); // mls v30.4H, v31.4H, v0.4H
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__ mlsv(v5, __ T8H, v6, v7); // mls v5.8H, v6.8H, v7.8H
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__ mlsv(v8, __ T2S, v9, v10); // mls v8.2S, v9.2S, v10.2S
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__ mlsv(v15, __ T4S, v16, v17); // mls v15.4S, v16.4S, v17.4S
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__ fmls(v29, __ T2S, v30, v31); // fmls v29.2S, v30.2S, v31.2S
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__ fmls(v30, __ T4S, v31, v0); // fmls v30.4S, v31.4S, v0.4S
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__ fmls(v0, __ T2D, v1, v2); // fmls v0.2D, v1.2D, v2.2D
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__ fmls(v20, __ T4H, v21, v22); // fmls v20.4H, v21.4H, v22.4H
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__ fmls(v7, __ T8H, v8, v9); // fmls v7.8H, v8.8H, v9.8H
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__ fdiv(v20, __ T2S, v21, v22); // fdiv v20.2S, v21.2S, v22.2S
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__ fdiv(v23, __ T4S, v24, v25); // fdiv v23.4S, v24.4S, v25.4S
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__ fdiv(v28, __ T2D, v29, v30); // fdiv v28.2D, v29.2D, v30.2D
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__ fdiv(v21, __ T4H, v22, v23); // fdiv v21.4H, v22.4H, v23.4H
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__ fdiv(v27, __ T8H, v28, v29); // fdiv v27.8H, v28.8H, v29.8H
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__ maxv(v25, __ T8B, v26, v27); // smax v25.8B, v26.8B, v27.8B
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__ maxv(v5, __ T16B, v6, v7); // smax v5.16B, v6.16B, v7.16B
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__ maxv(v1, __ T4H, v2, v3); // smax v1.4H, v2.4H, v3.4H
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__ maxv(v23, __ T8H, v24, v25); // smax v23.8H, v24.8H, v25.8H
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__ maxv(v16, __ T2S, v17, v18); // smax v16.2S, v17.2S, v18.2S
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__ maxv(v31, __ T4S, v0, v1); // smax v31.4S, v0.4S, v1.4S
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__ umaxv(v5, __ T8B, v6, v7); // umax v5.8B, v6.8B, v7.8B
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__ umaxv(v12, __ T16B, v13, v14); // umax v12.16B, v13.16B, v14.16B
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__ umaxv(v9, __ T4H, v10, v11); // umax v9.4H, v10.4H, v11.4H
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__ umaxv(v28, __ T8H, v29, v30); // umax v28.8H, v29.8H, v30.8H
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__ umaxv(v15, __ T2S, v16, v17); // umax v15.2S, v16.2S, v17.2S
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__ umaxv(v29, __ T4S, v30, v31); // umax v29.4S, v30.4S, v31.4S
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__ smaxp(v22, __ T8B, v23, v24); // smaxp v22.8B, v23.8B, v24.8B
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__ smaxp(v31, __ T16B, v0, v1); // smaxp v31.16B, v0.16B, v1.16B
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__ smaxp(v19, __ T4H, v20, v21); // smaxp v19.4H, v20.4H, v21.4H
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__ smaxp(v31, __ T8H, v0, v1); // smaxp v31.8H, v0.8H, v1.8H
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__ smaxp(v5, __ T2S, v6, v7); // smaxp v5.2S, v6.2S, v7.2S
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__ smaxp(v14, __ T4S, v15, v16); // smaxp v14.4S, v15.4S, v16.4S
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__ fmax(v18, __ T2S, v19, v20); // fmax v18.2S, v19.2S, v20.2S
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__ fmax(v31, __ T4S, v0, v1); // fmax v31.4S, v0.4S, v1.4S
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__ fmax(v18, __ T2D, v19, v20); // fmax v18.2D, v19.2D, v20.2D
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__ fmax(v27, __ T4H, v28, v29); // fmax v27.4H, v28.4H, v29.4H
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__ fmax(v20, __ T8H, v21, v22); // fmax v20.8H, v21.8H, v22.8H
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__ minv(v16, __ T8B, v17, v18); // smin v16.8B, v17.8B, v18.8B
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__ minv(v12, __ T16B, v13, v14); // smin v12.16B, v13.16B, v14.16B
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__ minv(v11, __ T4H, v12, v13); // smin v11.4H, v12.4H, v13.4H
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__ minv(v9, __ T8H, v10, v11); // smin v9.8H, v10.8H, v11.8H
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__ minv(v6, __ T2S, v7, v8); // smin v6.2S, v7.2S, v8.2S
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__ minv(v30, __ T4S, v31, v0); // smin v30.4S, v31.4S, v0.4S
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__ uminv(v17, __ T8B, v18, v19); // umin v17.8B, v18.8B, v19.8B
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__ uminv(v27, __ T16B, v28, v29); // umin v27.16B, v28.16B, v29.16B
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__ uminv(v28, __ T4H, v29, v30); // umin v28.4H, v29.4H, v30.4H
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__ uminv(v30, __ T8H, v31, v0); // umin v30.8H, v31.8H, v0.8H
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__ uminv(v7, __ T2S, v8, v9); // umin v7.2S, v8.2S, v9.2S
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__ uminv(v10, __ T4S, v11, v12); // umin v10.4S, v11.4S, v12.4S
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__ sminp(v20, __ T8B, v21, v22); // sminp v20.8B, v21.8B, v22.8B
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__ sminp(v10, __ T16B, v11, v12); // sminp v10.16B, v11.16B, v12.16B
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__ sminp(v4, __ T4H, v5, v6); // sminp v4.4H, v5.4H, v6.4H
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__ sminp(v24, __ T8H, v25, v26); // sminp v24.8H, v25.8H, v26.8H
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__ sminp(v17, __ T2S, v18, v19); // sminp v17.2S, v18.2S, v19.2S
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__ sminp(v17, __ T4S, v18, v19); // sminp v17.4S, v18.4S, v19.4S
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__ uminp(v22, __ T8B, v23, v24); // uminp v22.8B, v23.8B, v24.8B
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__ uminp(v3, __ T16B, v4, v5); // uminp v3.16B, v4.16B, v5.16B
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__ uminp(v29, __ T4H, v30, v31); // uminp v29.4H, v30.4H, v31.4H
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__ uminp(v15, __ T8H, v16, v17); // uminp v15.8H, v16.8H, v17.8H
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__ uminp(v22, __ T2S, v23, v24); // uminp v22.2S, v23.2S, v24.2S
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__ uminp(v19, __ T4S, v20, v21); // uminp v19.4S, v20.4S, v21.4S
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__ umaxp(v19, __ T8B, v20, v21); // umaxp v19.8B, v20.8B, v21.8B
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__ umaxp(v22, __ T16B, v23, v24); // umaxp v22.16B, v23.16B, v24.16B
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__ umaxp(v2, __ T4H, v3, v4); // umaxp v2.4H, v3.4H, v4.4H
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__ umaxp(v15, __ T8H, v16, v17); // umaxp v15.8H, v16.8H, v17.8H
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__ umaxp(v6, __ T2S, v7, v8); // umaxp v6.2S, v7.2S, v8.2S
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__ umaxp(v12, __ T4S, v13, v14); // umaxp v12.4S, v13.4S, v14.4S
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__ sqdmulh(v16, __ T4H, v17, v18); // sqdmulh v16.4H, v17.4H, v18.4H
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__ sqdmulh(v11, __ T8H, v12, v13); // sqdmulh v11.8H, v12.8H, v13.8H
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__ sqdmulh(v13, __ T2S, v14, v15); // sqdmulh v13.2S, v14.2S, v15.2S
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__ sqdmulh(v23, __ T4S, v24, v25); // sqdmulh v23.4S, v24.4S, v25.4S
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__ shsubv(v1, __ T8B, v2, v3); // shsub v1.8B, v2.8B, v3.8B
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__ shsubv(v30, __ T16B, v31, v0); // shsub v30.16B, v31.16B, v0.16B
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__ shsubv(v19, __ T4H, v20, v21); // shsub v19.4H, v20.4H, v21.4H
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__ shsubv(v5, __ T8H, v6, v7); // shsub v5.8H, v6.8H, v7.8H
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__ shsubv(v17, __ T2S, v18, v19); // shsub v17.2S, v18.2S, v19.2S
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__ shsubv(v2, __ T4S, v3, v4); // shsub v2.4S, v3.4S, v4.4S
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__ fmin(v16, __ T2S, v17, v18); // fmin v16.2S, v17.2S, v18.2S
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__ fmin(v22, __ T4S, v23, v24); // fmin v22.4S, v23.4S, v24.4S
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__ fmin(v13, __ T2D, v14, v15); // fmin v13.2D, v14.2D, v15.2D
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__ fmin(v10, __ T4H, v11, v12); // fmin v10.4H, v11.4H, v12.4H
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__ fmin(v21, __ T8H, v22, v23); // fmin v21.8H, v22.8H, v23.8H
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__ facgt(v29, __ T2S, v30, v31); // facgt v29.2S, v30.2S, v31.2S
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__ facgt(v27, __ T4S, v28, v29); // facgt v27.4S, v28.4S, v29.4S
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__ facgt(v12, __ T2D, v13, v14); // facgt v12.2D, v13.2D, v14.2D
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__ facgt(v27, __ T4H, v28, v29); // facgt v27.4H, v28.4H, v29.4H
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__ facgt(v3, __ T8H, v4, v5); // facgt v3.8H, v4.8H, v5.8H
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|
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// VectorScalarNEONInstruction
|
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__ fmlavs(v15, __ T2S, v0, v1, 0); // fmla v15.2S, v0.2S, v1.S[0]
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__ mulvs(v9, __ T4S, v10, v11, 3); // mul v9.4S, v10.4S, v11.S[3]
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__ fmlavs(v4, __ T2D, v5, v6, 1); // fmla v4.2D, v5.2D, v6.D[1]
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__ fmlsvs(v13, __ T2S, v14, v15, 1); // fmls v13.2S, v14.2S, v15.S[1]
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__ mulvs(v3, __ T4S, v4, v5, 1); // mul v3.4S, v4.4S, v5.S[1]
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__ fmlsvs(v11, __ T2D, v12, v13, 1); // fmls v11.2D, v12.2D, v13.D[1]
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__ fmulxvs(v12, __ T2S, v13, v14, 1); // fmulx v12.2S, v13.2S, v14.S[1]
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__ mulvs(v15, __ T4S, v0, v1, 0); // mul v15.4S, v0.4S, v1.S[0]
|
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__ fmulxvs(v9, __ T2D, v10, v11, 1); // fmulx v9.2D, v10.2D, v11.D[1]
|
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__ mulvs(v11, __ T4H, v12, v13, 1); // mul v11.4H, v12.4H, v13.H[1]
|
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__ mulvs(v1, __ T8H, v2, v3, 4); // mul v1.8H, v2.8H, v3.H[4]
|
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__ mulvs(v0, __ T2S, v1, v2, 1); // mul v0.2S, v1.2S, v2.S[1]
|
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__ mulvs(v13, __ T4S, v14, v15, 3); // mul v13.4S, v14.4S, v15.S[3]
|
|
|
|
// NEONVectorCompare
|
|
__ cm(Assembler::GT, v23, __ T8B, v24, v25); // cmgt v23.8B, v24.8B, v25.8B
|
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__ cm(Assembler::GT, v2, __ T16B, v3, v4); // cmgt v2.16B, v3.16B, v4.16B
|
|
__ cm(Assembler::GT, v18, __ T4H, v19, v20); // cmgt v18.4H, v19.4H, v20.4H
|
|
__ cm(Assembler::GT, v12, __ T8H, v13, v14); // cmgt v12.8H, v13.8H, v14.8H
|
|
__ cm(Assembler::GT, v4, __ T2S, v5, v6); // cmgt v4.2S, v5.2S, v6.2S
|
|
__ cm(Assembler::GT, v28, __ T4S, v29, v30); // cmgt v28.4S, v29.4S, v30.4S
|
|
__ cm(Assembler::GT, v30, __ T2D, v31, v0); // cmgt v30.2D, v31.2D, v0.2D
|
|
__ cm(Assembler::GE, v29, __ T8B, v30, v31); // cmge v29.8B, v30.8B, v31.8B
|
|
__ cm(Assembler::GE, v16, __ T16B, v17, v18); // cmge v16.16B, v17.16B, v18.16B
|
|
__ cm(Assembler::GE, v27, __ T4H, v28, v29); // cmge v27.4H, v28.4H, v29.4H
|
|
__ cm(Assembler::GE, v6, __ T8H, v7, v8); // cmge v6.8H, v7.8H, v8.8H
|
|
__ cm(Assembler::GE, v9, __ T2S, v10, v11); // cmge v9.2S, v10.2S, v11.2S
|
|
__ cm(Assembler::GE, v29, __ T4S, v30, v31); // cmge v29.4S, v30.4S, v31.4S
|
|
__ cm(Assembler::GE, v18, __ T2D, v19, v20); // cmge v18.2D, v19.2D, v20.2D
|
|
__ cm(Assembler::EQ, v7, __ T8B, v8, v9); // cmeq v7.8B, v8.8B, v9.8B
|
|
__ cm(Assembler::EQ, v4, __ T16B, v5, v6); // cmeq v4.16B, v5.16B, v6.16B
|
|
__ cm(Assembler::EQ, v7, __ T4H, v8, v9); // cmeq v7.4H, v8.4H, v9.4H
|
|
__ cm(Assembler::EQ, v15, __ T8H, v16, v17); // cmeq v15.8H, v16.8H, v17.8H
|
|
__ cm(Assembler::EQ, v9, __ T2S, v10, v11); // cmeq v9.2S, v10.2S, v11.2S
|
|
__ cm(Assembler::EQ, v23, __ T4S, v24, v25); // cmeq v23.4S, v24.4S, v25.4S
|
|
__ cm(Assembler::EQ, v8, __ T2D, v9, v10); // cmeq v8.2D, v9.2D, v10.2D
|
|
__ cm(Assembler::HI, v2, __ T8B, v3, v4); // cmhi v2.8B, v3.8B, v4.8B
|
|
__ cm(Assembler::HI, v28, __ T16B, v29, v30); // cmhi v28.16B, v29.16B, v30.16B
|
|
__ cm(Assembler::HI, v21, __ T4H, v22, v23); // cmhi v21.4H, v22.4H, v23.4H
|
|
__ cm(Assembler::HI, v31, __ T8H, v0, v1); // cmhi v31.8H, v0.8H, v1.8H
|
|
__ cm(Assembler::HI, v5, __ T2S, v6, v7); // cmhi v5.2S, v6.2S, v7.2S
|
|
__ cm(Assembler::HI, v27, __ T4S, v28, v29); // cmhi v27.4S, v28.4S, v29.4S
|
|
__ cm(Assembler::HI, v0, __ T2D, v1, v2); // cmhi v0.2D, v1.2D, v2.2D
|
|
__ cm(Assembler::HS, v17, __ T8B, v18, v19); // cmhs v17.8B, v18.8B, v19.8B
|
|
__ cm(Assembler::HS, v15, __ T16B, v16, v17); // cmhs v15.16B, v16.16B, v17.16B
|
|
__ cm(Assembler::HS, v4, __ T4H, v5, v6); // cmhs v4.4H, v5.4H, v6.4H
|
|
__ cm(Assembler::HS, v26, __ T8H, v27, v28); // cmhs v26.8H, v27.8H, v28.8H
|
|
__ cm(Assembler::HS, v8, __ T2S, v9, v10); // cmhs v8.2S, v9.2S, v10.2S
|
|
__ cm(Assembler::HS, v28, __ T4S, v29, v30); // cmhs v28.4S, v29.4S, v30.4S
|
|
__ cm(Assembler::HS, v22, __ T2D, v23, v24); // cmhs v22.2D, v23.2D, v24.2D
|
|
__ fcm(Assembler::EQ, v27, __ T2S, v28, v29); // fcmeq v27.2S, v28.2S, v29.2S
|
|
__ fcm(Assembler::EQ, v27, __ T4S, v28, v29); // fcmeq v27.4S, v28.4S, v29.4S
|
|
__ fcm(Assembler::EQ, v25, __ T2D, v26, v27); // fcmeq v25.2D, v26.2D, v27.2D
|
|
__ fcm(Assembler::GT, v23, __ T2S, v24, v25); // fcmgt v23.2S, v24.2S, v25.2S
|
|
__ fcm(Assembler::GT, v0, __ T4S, v1, v2); // fcmgt v0.4S, v1.4S, v2.4S
|
|
__ fcm(Assembler::GT, v4, __ T2D, v5, v6); // fcmgt v4.2D, v5.2D, v6.2D
|
|
__ fcm(Assembler::GE, v6, __ T2S, v7, v8); // fcmge v6.2S, v7.2S, v8.2S
|
|
__ fcm(Assembler::GE, v18, __ T4S, v19, v20); // fcmge v18.4S, v19.4S, v20.4S
|
|
__ fcm(Assembler::GE, v0, __ T2D, v1, v2); // fcmge v0.2D, v1.2D, v2.2D
|
|
|
|
// SVEComparisonWithZero
|
|
__ sve_fcm(Assembler::EQ, p2, __ S, p2, z15, 0.0); // fcmeq p2.s, p2/z, z15.s, #0.0
|
|
__ sve_fcm(Assembler::GT, p3, __ S, p7, z5, 0.0); // fcmgt p3.s, p7/z, z5.s, #0.0
|
|
__ sve_fcm(Assembler::GE, p3, __ D, p5, z20, 0.0); // fcmge p3.d, p5/z, z20.d, #0.0
|
|
__ sve_fcm(Assembler::LT, p3, __ S, p4, z11, 0.0); // fcmlt p3.s, p4/z, z11.s, #0.0
|
|
__ sve_fcm(Assembler::LE, p15, __ D, p0, z6, 0.0); // fcmle p15.d, p0/z, z6.d, #0.0
|
|
__ sve_fcm(Assembler::NE, p6, __ D, p0, z30, 0.0); // fcmne p6.d, p0/z, z30.d, #0.0
|
|
|
|
// SVEComparisonWithImm
|
|
__ sve_cmp(Assembler::EQ, p13, __ D, p3, z22, -3); // cmpeq p13.d, p3/z, z22.d, #-3
|
|
__ sve_cmp(Assembler::GT, p14, __ D, p1, z17, -14); // cmpgt p14.d, p1/z, z17.d, #-14
|
|
__ sve_cmp(Assembler::GE, p7, __ S, p2, z10, 11); // cmpge p7.s, p2/z, z10.s, #11
|
|
__ sve_cmp(Assembler::LT, p11, __ B, p5, z12, 1); // cmplt p11.b, p5/z, z12.b, #1
|
|
__ sve_cmp(Assembler::LE, p2, __ S, p4, z1, 2); // cmple p2.s, p4/z, z1.s, #2
|
|
__ sve_cmp(Assembler::NE, p6, __ H, p0, z14, 1); // cmpne p6.h, p0/z, z14.h, #1
|
|
__ sve_cmp(Assembler::HS, p1, __ S, p1, z21, 25); // cmphs p1.s, p1/z, z21.s, #25
|
|
__ sve_cmp(Assembler::HI, p3, __ H, p7, z19, 70); // cmphi p3.h, p7/z, z19.h, #70
|
|
__ sve_cmp(Assembler::LS, p8, __ B, p7, z6, 12); // cmpls p8.b, p7/z, z6.b, #12
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__ sve_cmp(Assembler::LO, p2, __ S, p5, z6, 55); // cmplo p2.s, p5/z, z6.s, #55
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// SpecialCases
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__ ccmn(zr, zr, 3u, Assembler::LE); // ccmn xzr, xzr, #3, LE
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__ ccmnw(zr, zr, 5u, Assembler::EQ); // ccmn wzr, wzr, #5, EQ
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__ ccmp(zr, 1, 4u, Assembler::NE); // ccmp xzr, 1, #4, NE
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__ ccmpw(zr, 2, 2, Assembler::GT); // ccmp wzr, 2, #2, GT
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__ extr(zr, zr, zr, 0); // extr xzr, xzr, xzr, 0
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__ stlxp(r0, zr, zr, sp); // stlxp w0, xzr, xzr, [sp]
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__ stlxpw(r2, zr, zr, r3); // stlxp w2, wzr, wzr, [x3]
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__ stxp(r4, zr, zr, r5); // stxp w4, xzr, xzr, [x5]
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__ stxpw(r6, zr, zr, sp); // stxp w6, wzr, wzr, [sp]
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__ dup(v0, __ T16B, zr); // dup v0.16b, wzr
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__ dup(v0, __ S, v1); // dup s0, v1.s[0]
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__ mov(v1, __ D, 0, zr); // mov v1.d[0], xzr
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__ mov(v1, __ S, 1, zr); // mov v1.s[1], wzr
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__ mov(v1, __ H, 2, zr); // mov v1.h[2], wzr
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__ mov(v1, __ B, 3, zr); // mov v1.b[3], wzr
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__ smov(r0, v1, __ S, 0); // smov x0, v1.s[0]
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__ smov(r0, v1, __ H, 1); // smov x0, v1.h[1]
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__ smov(r0, v1, __ B, 2); // smov x0, v1.b[2]
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__ umov(r0, v1, __ D, 0); // umov x0, v1.d[0]
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__ umov(r0, v1, __ S, 1); // umov w0, v1.s[1]
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__ umov(r0, v1, __ H, 2); // umov w0, v1.h[2]
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__ umov(r0, v1, __ B, 3); // umov w0, v1.b[3]
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__ fmovhid(r0, v1); // fmov x0, v1.d[1]
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__ fmovs(v9, __ T2S, 0.5f); // fmov v9.2s, 0.5
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__ fmovd(v14, __ T2D, 0.5f); // fmov v14.2d, 0.5
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__ ld1(v31, v0, __ T2D, Address(__ post(r1, r0))); // ld1 {v31.2d, v0.2d}, [x1], x0
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__ fcvtzs(v0, __ T2S, v1); // fcvtzs v0.2s, v1.2s
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__ fcvtzs(v0, __ T4H, v1); // fcvtzs v0.4h, v1.4h
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__ fcvtzs(v0, __ T8H, v1); // fcvtzs v0.8h, v1.8h
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__ fcvtas(v2, __ T4S, v3); // fcvtas v2.4s, v3.4s
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__ fcvtas(v2, __ T4H, v3); // fcvtas v2.4h, v3.4h
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__ fcvtas(v2, __ T8H, v3); // fcvtas v2.8h, v3.8h
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__ fcvtms(v4, __ T2D, v5); // fcvtms v4.2d, v5.2d
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__ fcvtms(v4, __ T4H, v5); // fcvtms v4.4h, v5.4h
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__ fcvtms(v4, __ T8H, v5); // fcvtms v4.8h, v5.8h
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__ sve_cpy(z0, __ S, p0, v1); // mov z0.s, p0/m, s1
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__ sve_cpy(z0, __ B, p0, 127, true); // mov z0.b, p0/m, 127
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__ sve_cpy(z1, __ H, p0, -128, true); // mov z1.h, p0/m, -128
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__ sve_cpy(z2, __ S, p0, 32512, true); // mov z2.s, p0/m, 32512
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__ sve_cpy(z5, __ D, p0, -32768, false); // mov z5.d, p0/z, -32768
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__ sve_cpy(z10, __ B, p0, -1, false); // mov z10.b, p0/z, -1
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__ sve_cpy(z11, __ S, p0, -1, false); // mov z11.s, p0/z, -1
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__ sve_cpy(z11, __ S, p0, 0.5); // fcpy z11.s, p0/m, #0.5
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__ sve_cpy(z11, __ S, p0, -1.0); // fcpy z11.s, p0/m, #-1.0
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__ sve_inc(r0, __ S); // incw x0
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__ sve_dec(r1, __ H); // dech x1
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__ sve_lsl(z0, __ B, z1, 7); // lsl z0.b, z1.b, #7
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__ sve_lsl(z21, __ H, z1, 15); // lsl z21.h, z1.h, #15
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__ sve_lsl(z0, __ S, z1, 31); // lsl z0.s, z1.s, #31
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__ sve_lsl(z0, __ D, z1, 63); // lsl z0.d, z1.d, #63
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__ sve_lsr(z0, __ B, z1, 7); // lsr z0.b, z1.b, #7
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__ sve_asr(z0, __ H, z11, 15); // asr z0.h, z11.h, #15
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__ sve_lsr(z30, __ S, z1, 31); // lsr z30.s, z1.s, #31
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__ sve_asr(z0, __ D, z1, 63); // asr z0.d, z1.d, #63
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__ sve_lsl(z0, __ B, p0, 0); // lsl z0.b, p0/m, z0.b, #0
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__ sve_lsl(z0, __ B, p0, 5); // lsl z0.b, p0/m, z0.b, #5
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__ sve_lsl(z1, __ H, p1, 15); // lsl z1.h, p1/m, z1.h, #15
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__ sve_lsl(z2, __ S, p2, 31); // lsl z2.s, p2/m, z2.s, #31
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__ sve_lsl(z3, __ D, p3, 63); // lsl z3.d, p3/m, z3.d, #63
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__ sve_lsr(z0, __ B, p0, 1); // lsr z0.b, p0/m, z0.b, #1
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__ sve_lsr(z0, __ B, p0, 8); // lsr z0.b, p0/m, z0.b, #8
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__ sve_lsr(z1, __ H, p1, 15); // lsr z1.h, p1/m, z1.h, #15
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__ sve_lsr(z2, __ S, p2, 7); // lsr z2.s, p2/m, z2.s, #7
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__ sve_lsr(z2, __ S, p2, 31); // lsr z2.s, p2/m, z2.s, #31
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__ sve_lsr(z3, __ D, p3, 63); // lsr z3.d, p3/m, z3.d, #63
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__ sve_asr(z0, __ B, p0, 1); // asr z0.b, p0/m, z0.b, #1
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__ sve_asr(z0, __ B, p0, 7); // asr z0.b, p0/m, z0.b, #7
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__ sve_asr(z1, __ H, p1, 5); // asr z1.h, p1/m, z1.h, #5
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__ sve_asr(z1, __ H, p1, 15); // asr z1.h, p1/m, z1.h, #15
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__ sve_asr(z2, __ S, p2, 31); // asr z2.s, p2/m, z2.s, #31
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__ sve_asr(z3, __ D, p3, 63); // asr z3.d, p3/m, z3.d, #63
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__ sve_addvl(sp, r0, 31); // addvl sp, x0, #31
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__ sve_addpl(r1, sp, -32); // addpl x1, sp, -32
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__ sve_cntp(r8, __ B, p0, p1); // cntp x8, p0, p1.b
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__ sve_dup(z0, __ B, 127); // dup z0.b, 127
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__ sve_dup(z1, __ H, -128); // dup z1.h, -128
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__ sve_dup(z2, __ S, 32512); // dup z2.s, 32512
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__ sve_dup(z7, __ D, -32768); // dup z7.d, -32768
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__ sve_dup(z10, __ B, -1); // dup z10.b, -1
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__ sve_dup(z11, __ S, -1); // dup z11.s, -1
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__ sve_ld1b(z0, __ B, p0, Address(sp)); // ld1b {z0.b}, p0/z, [sp]
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__ sve_ld1b(z0, __ H, p1, Address(sp)); // ld1b {z0.h}, p1/z, [sp]
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__ sve_ld1b(z0, __ S, p2, Address(sp, r8)); // ld1b {z0.s}, p2/z, [sp, x8]
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__ sve_ld1b(z0, __ D, p3, Address(sp, 7)); // ld1b {z0.d}, p3/z, [sp, #7, MUL VL]
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__ sve_ld1h(z10, __ H, p1, Address(sp, -8)); // ld1h {z10.h}, p1/z, [sp, #-8, MUL VL]
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__ sve_ld1w(z20, __ S, p2, Address(r0, 7)); // ld1w {z20.s}, p2/z, [x0, #7, MUL VL]
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__ sve_ld1b(z30, __ B, p3, Address(sp, r8)); // ld1b {z30.b}, p3/z, [sp, x8]
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__ sve_ld1w(z0, __ S, p4, Address(sp, r28)); // ld1w {z0.s}, p4/z, [sp, x28, LSL #2]
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__ sve_ld1d(z11, __ D, p5, Address(r0, r1)); // ld1d {z11.d}, p5/z, [x0, x1, LSL #3]
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__ sve_st1b(z22, __ B, p6, Address(sp)); // st1b {z22.b}, p6, [sp]
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__ sve_st1b(z31, __ B, p7, Address(sp, -8)); // st1b {z31.b}, p7, [sp, #-8, MUL VL]
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__ sve_st1b(z0, __ H, p1, Address(sp)); // st1b {z0.h}, p1, [sp]
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__ sve_st1b(z0, __ S, p2, Address(sp, r8)); // st1b {z0.s}, p2, [sp, x8]
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__ sve_st1b(z0, __ D, p3, Address(sp)); // st1b {z0.d}, p3, [sp]
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__ sve_st1w(z0, __ S, p1, Address(r0, 7)); // st1w {z0.s}, p1, [x0, #7, MUL VL]
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__ sve_st1b(z0, __ B, p2, Address(sp, r1)); // st1b {z0.b}, p2, [sp, x1]
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__ sve_st1h(z0, __ H, p3, Address(sp, r8)); // st1h {z0.h}, p3, [sp, x8, LSL #1]
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__ sve_st1d(z0, __ D, p4, Address(r0, r17)); // st1d {z0.d}, p4, [x0, x17, LSL #3]
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__ sve_ldr(z0, Address(sp)); // ldr z0, [sp]
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__ sve_ldr(z31, Address(sp, -256)); // ldr z31, [sp, #-256, MUL VL]
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__ sve_str(z8, Address(r8, 255)); // str z8, [x8, #255, MUL VL]
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__ sve_cntb(r9); // cntb x9
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__ sve_cnth(r10); // cnth x10
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__ sve_cntw(r11); // cntw x11
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__ sve_cntd(r12); // cntd x12
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__ sve_brka(p2, p0, p2, false); // brka p2.b, p0/z, p2.b
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__ sve_brka(p1, p2, p3, true); // brka p1.b, p2/m, p3.b
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__ sve_brkb(p1, p2, p3, false); // brkb p1.b, p2/z, p3.b
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__ sve_brkb(p2, p3, p4, true); // brkb p2.b, p3/m, p4.b
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__ sve_rev(p0, __ B, p1); // rev p0.b, p1.b
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__ sve_rev(p1, __ H, p2); // rev p1.h, p2.h
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__ sve_rev(p2, __ S, p3); // rev p2.s, p3.s
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__ sve_rev(p3, __ D, p4); // rev p3.d, p4.d
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__ sve_incp(r0, __ B, p2); // incp x0, p2.b
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__ sve_whilelt(p0, __ B, r1, r28); // whilelt p0.b, x1, x28
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__ sve_whilele(p2, __ H, r11, r8); // whilele p2.h, x11, x8
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__ sve_whilelo(p3, __ S, r7, r2); // whilelo p3.s, x7, x2
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__ sve_whilels(p4, __ D, r17, r10); // whilels p4.d, x17, x10
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__ sve_whileltw(p1, __ B, r1, r28); // whilelt p1.b, w1, w28
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__ sve_whilelew(p2, __ H, r11, r8); // whilele p2.h, w11, w8
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__ sve_whilelow(p3, __ S, r7, r2); // whilelo p3.s, w7, w2
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__ sve_whilelsw(p4, __ D, r17, r10); // whilels p4.d, w17, w10
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__ sve_sel(z0, __ B, p0, z1, z2); // sel z0.b, p0, z1.b, z2.b
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__ sve_sel(z4, __ D, p0, z5, z6); // sel z4.d, p0, z5.d, z6.d
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__ sve_cmp(Assembler::EQ, p1, __ B, p0, z0, z1); // cmpeq p1.b, p0/z, z0.b, z1.b
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__ sve_cmp(Assembler::NE, p1, __ H, p0, z2, z3); // cmpne p1.h, p0/z, z2.h, z3.h
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__ sve_cmp(Assembler::GE, p1, __ S, p2, z4, z5); // cmpge p1.s, p2/z, z4.s, z5.s
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__ sve_cmp(Assembler::GT, p1, __ D, p3, z6, z7); // cmpgt p1.d, p3/z, z6.d, z7.d
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__ sve_cmp(Assembler::HI, p1, __ S, p2, z4, z5); // cmphi p1.s, p2/z, z4.s, z5.s
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__ sve_cmp(Assembler::HS, p1, __ D, p3, z6, z7); // cmphs p1.d, p3/z, z6.d, z7.d
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__ sve_cmp(Assembler::EQ, p1, __ B, p4, z0, 15); // cmpeq p1.b, p4/z, z0.b, #15
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__ sve_cmp(Assembler::NE, p1, __ H, p0, z2, -16); // cmpne p1.h, p0/z, z2.h, #-16
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__ sve_cmp(Assembler::LE, p1, __ S, p1, z4, 0); // cmple p1.s, p1/z, z4.s, #0
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__ sve_cmp(Assembler::LT, p1, __ D, p2, z6, -1); // cmplt p1.d, p2/z, z6.d, #-1
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__ sve_cmp(Assembler::GE, p1, __ S, p3, z4, 5); // cmpge p1.s, p3/z, z4.s, #5
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__ sve_cmp(Assembler::GT, p1, __ B, p4, z6, -2); // cmpgt p1.b, p4/z, z6.b, #-2
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__ sve_fcm(Assembler::EQ, p1, __ S, p0, z0, z1); // fcmeq p1.s, p0/z, z0.s, z1.s
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__ sve_fcm(Assembler::NE, p1, __ D, p0, z2, z3); // fcmne p1.d, p0/z, z2.d, z3.d
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__ sve_fcm(Assembler::GT, p1, __ S, p2, z4, z5); // fcmgt p1.s, p2/z, z4.s, z5.s
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__ sve_fcm(Assembler::GE, p1, __ D, p3, z6, z7); // fcmge p1.d, p3/z, z6.d, z7.d
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__ sve_uunpkhi(z0, __ H, z1); // uunpkhi z0.h, z1.b
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__ sve_uunpklo(z4, __ S, z5); // uunpklo z4.s, z5.h
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__ sve_sunpkhi(z6, __ D, z7); // sunpkhi z6.d, z7.s
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__ sve_sunpklo(z10, __ H, z11); // sunpklo z10.h, z11.b
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__ sve_scvtf(z1, __ D, p0, z0, __ S); // scvtf z1.d, p0/m, z0.s
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__ sve_scvtf(z3, __ D, p1, z2, __ D); // scvtf z3.d, p1/m, z2.d
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__ sve_scvtf(z6, __ S, p2, z1, __ D); // scvtf z6.s, p2/m, z1.d
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__ sve_scvtf(z6, __ S, p3, z1, __ S); // scvtf z6.s, p3/m, z1.s
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__ sve_scvtf(z6, __ H, p3, z1, __ S); // scvtf z6.h, p3/m, z1.s
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__ sve_scvtf(z6, __ H, p3, z1, __ D); // scvtf z6.h, p3/m, z1.d
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__ sve_scvtf(z6, __ H, p3, z1, __ H); // scvtf z6.h, p3/m, z1.h
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__ sve_fcvt(z5, __ D, p3, z4, __ S); // fcvt z5.d, p3/m, z4.s
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__ sve_fcvt(z1, __ S, p3, z0, __ D); // fcvt z1.s, p3/m, z0.d
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__ sve_fcvt(z5, __ S, p3, z4, __ H); // fcvt z5.s, p3/m, z4.h
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__ sve_fcvt(z1, __ H, p3, z0, __ S); // fcvt z1.h, p3/m, z0.s
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__ sve_fcvt(z5, __ D, p3, z4, __ H); // fcvt z5.d, p3/m, z4.h
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__ sve_fcvt(z1, __ H, p3, z0, __ D); // fcvt z1.h, p3/m, z0.d
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__ sve_fcvtzs(z19, __ D, p2, z1, __ D); // fcvtzs z19.d, p2/m, z1.d
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__ sve_fcvtzs(z9, __ S, p1, z8, __ S); // fcvtzs z9.s, p1/m, z8.s
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__ sve_fcvtzs(z1, __ S, p2, z0, __ D); // fcvtzs z1.s, p2/m, z0.d
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__ sve_fcvtzs(z1, __ D, p3, z0, __ S); // fcvtzs z1.d, p3/m, z0.s
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__ sve_fcvtzs(z1, __ S, p4, z18, __ H); // fcvtzs z1.s, p4/m, z18.h
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__ sve_lasta(r0, __ B, p0, z15); // lasta w0, p0, z15.b
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__ sve_lastb(r1, __ B, p1, z16); // lastb w1, p1, z16.b
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__ sve_lasta(v0, __ B, p0, z15); // lasta b0, p0, z15.b
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__ sve_lastb(v1, __ B, p1, z16); // lastb b1, p1, z16.b
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__ sve_index(z6, __ S, 1, 1); // index z6.s, #1, #1
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__ sve_index(z6, __ B, r5, 2); // index z6.b, w5, #2
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__ sve_index(z6, __ H, r5, 3); // index z6.h, w5, #3
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__ sve_index(z6, __ S, r5, 4); // index z6.s, w5, #4
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__ sve_index(z7, __ D, r5, 5); // index z7.d, x5, #5
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__ sve_cpy(z7, __ H, p3, r5); // cpy z7.h, p3/m, w5
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__ sve_tbl(z16, __ S, z17, z18); // tbl z16.s, {z17.s}, z18.s
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__ sve_tbl(z16, __ B, z17, z18, z16); // tbl z16.b, {z17.b, z18.b}, z16.b
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__ sve_tbl(z16, __ H, z17, z18, z16); // tbl z16.h, {z17.h, z18.h}, z16.h
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__ sve_tbl(z16, __ S, z17, z18, z16); // tbl z16.s, {z17.s, z18.s}, z16.s
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__ sve_tbl(z16, __ D, z17, z18, z16); // tbl z16.d, {z17.d, z18.d}, z16.d
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__ sve_ld1w_gather(z15, p0, r5, z16); // ld1w {z15.s}, p0/z, [x5, z16.s, uxtw #2]
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__ sve_ld1d_gather(z15, p0, r5, z16); // ld1d {z15.d}, p0/z, [x5, z16.d, uxtw #3]
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__ sve_st1w_scatter(z15, p0, r5, z16); // st1w {z15.s}, p0, [x5, z16.s, uxtw #2]
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__ sve_st1d_scatter(z15, p0, r5, z16); // st1d {z15.d}, p0, [x5, z16.d, uxtw #3]
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__ sve_and(p0, p1, p2, p3); // and p0.b, p1/z, p2.b, p3.b
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__ sve_ands(p4, p5, p6, p0); // ands p4.b, p5/z, p6.b, p0.b
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__ sve_eor(p0, p1, p2, p3); // eor p0.b, p1/z, p2.b, p3.b
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__ sve_eors(p5, p6, p0, p1); // eors p5.b, p6/z, p0.b, p1.b
|
|
__ sve_orr(p0, p1, p2, p3); // orr p0.b, p1/z, p2.b, p3.b
|
|
__ sve_orrs(p9, p1, p4, p5); // orrs p9.b, p1/z, p4.b, p5.b
|
|
__ sve_bic(p10, p7, p9, p11); // bic p10.b, p7/z, p9.b, p11.b
|
|
__ sve_ptest(p7, p1); // ptest p7, p1.b
|
|
__ sve_ptrue(p1, __ B); // ptrue p1.b
|
|
__ sve_ptrue(p1, __ B, 0b00001); // ptrue p1.b, vl1
|
|
__ sve_ptrue(p1, __ B, 0b00101); // ptrue p1.b, vl5
|
|
__ sve_ptrue(p1, __ B, 0b01001); // ptrue p1.b, vl16
|
|
__ sve_ptrue(p1, __ B, 0b01101); // ptrue p1.b, vl256
|
|
__ sve_ptrue(p2, __ H); // ptrue p2.h
|
|
__ sve_ptrue(p2, __ H, 0b00010); // ptrue p2.h, vl2
|
|
__ sve_ptrue(p2, __ H, 0b00110); // ptrue p2.h, vl6
|
|
__ sve_ptrue(p2, __ H, 0b01010); // ptrue p2.h, vl32
|
|
__ sve_ptrue(p3, __ S); // ptrue p3.s
|
|
__ sve_ptrue(p3, __ S, 0b00011); // ptrue p3.s, vl3
|
|
__ sve_ptrue(p3, __ S, 0b00111); // ptrue p3.s, vl7
|
|
__ sve_ptrue(p3, __ S, 0b01011); // ptrue p3.s, vl64
|
|
__ sve_ptrue(p4, __ D); // ptrue p4.d
|
|
__ sve_ptrue(p4, __ D, 0b00100); // ptrue p4.d, vl4
|
|
__ sve_ptrue(p4, __ D, 0b01000); // ptrue p4.d, vl8
|
|
__ sve_ptrue(p4, __ D, 0b01100); // ptrue p4.d, vl128
|
|
__ sve_pfalse(p7); // pfalse p7.b
|
|
__ sve_uzp1(p0, __ B, p0, p1); // uzp1 p0.b, p0.b, p1.b
|
|
__ sve_uzp1(p0, __ H, p0, p1); // uzp1 p0.h, p0.h, p1.h
|
|
__ sve_uzp1(p0, __ S, p0, p1); // uzp1 p0.s, p0.s, p1.s
|
|
__ sve_uzp1(p0, __ D, p0, p1); // uzp1 p0.d, p0.d, p1.d
|
|
__ sve_uzp2(p0, __ B, p0, p1); // uzp2 p0.b, p0.b, p1.b
|
|
__ sve_uzp2(p0, __ H, p0, p1); // uzp2 p0.h, p0.h, p1.h
|
|
__ sve_uzp2(p0, __ S, p0, p1); // uzp2 p0.s, p0.s, p1.s
|
|
__ sve_uzp2(p0, __ D, p0, p1); // uzp2 p0.d, p0.d, p1.d
|
|
__ sve_punpklo(p1, p0); // punpklo p1.h, p0.b
|
|
__ sve_punpkhi(p1, p0); // punpkhi p1.h, p0.b
|
|
__ sve_compact(z16, __ S, z16, p1); // compact z16.s, p1, z16.s
|
|
__ sve_compact(z16, __ D, z16, p1); // compact z16.d, p1, z16.d
|
|
__ sve_movprfx(z17, z1); // movprfx z17, z1
|
|
__ sve_ext(z17, z16, 63); // ext z17.b, z17.b, z16.b, #63
|
|
__ sve_fac(Assembler::GT, p1, __ H, p2, z4, z5); // facgt p1.h, p2/z, z4.h, z5.h
|
|
__ sve_fac(Assembler::GT, p1, __ S, p2, z4, z5); // facgt p1.s, p2/z, z4.s, z5.s
|
|
__ sve_fac(Assembler::GT, p1, __ D, p2, z4, z5); // facgt p1.d, p2/z, z4.d, z5.d
|
|
__ sve_fac(Assembler::GE, p1, __ H, p2, z4, z5); // facge p1.h, p2/z, z4.h, z5.h
|
|
__ sve_fac(Assembler::GE, p1, __ S, p2, z4, z5); // facge p1.s, p2/z, z4.s, z5.s
|
|
__ sve_fac(Assembler::GE, p1, __ D, p2, z4, z5); // facge p1.d, p2/z, z4.d, z5.d
|
|
__ sve_splice(z0, __ B, p0, z1); // splice z0.b, p0, z0.b, z1.b
|
|
__ sve_splice(z0, __ H, p0, z1); // splice z0.h, p0, z0.h, z1.h
|
|
__ sve_splice(z0, __ S, p0, z1); // splice z0.s, p0, z0.s, z1.s
|
|
__ sve_splice(z0, __ D, p0, z1); // splice z0.d, p0, z0.d, z1.d
|
|
__ sve_histcnt(z16, __ S, p0, z16, z16); // histcnt z16.s, p0/z, z16.s, z16.s
|
|
__ sve_histcnt(z17, __ D, p0, z17, z17); // histcnt z17.d, p0/z, z17.d, z17.d
|
|
|
|
// FloatImmediateOp
|
|
__ fmovd(v0, 2.0); // fmov d0, #2.0
|
|
__ fmovd(v0, 2.125); // fmov d0, #2.125
|
|
__ fmovd(v0, 4.0); // fmov d0, #4.0
|
|
__ fmovd(v0, 4.25); // fmov d0, #4.25
|
|
__ fmovd(v0, 8.0); // fmov d0, #8.0
|
|
__ fmovd(v0, 8.5); // fmov d0, #8.5
|
|
__ fmovd(v0, 16.0); // fmov d0, #16.0
|
|
__ fmovd(v0, 17.0); // fmov d0, #17.0
|
|
__ fmovd(v0, 0.125); // fmov d0, #0.125
|
|
__ fmovd(v0, 0.1328125); // fmov d0, #0.1328125
|
|
__ fmovd(v0, 0.25); // fmov d0, #0.25
|
|
__ fmovd(v0, 0.265625); // fmov d0, #0.265625
|
|
__ fmovd(v0, 0.5); // fmov d0, #0.5
|
|
__ fmovd(v0, 0.53125); // fmov d0, #0.53125
|
|
__ fmovd(v0, 1.0); // fmov d0, #1.0
|
|
__ fmovd(v0, 1.0625); // fmov d0, #1.0625
|
|
__ fmovd(v0, -2.0); // fmov d0, #-2.0
|
|
__ fmovd(v0, -2.125); // fmov d0, #-2.125
|
|
__ fmovd(v0, -4.0); // fmov d0, #-4.0
|
|
__ fmovd(v0, -4.25); // fmov d0, #-4.25
|
|
__ fmovd(v0, -8.0); // fmov d0, #-8.0
|
|
__ fmovd(v0, -8.5); // fmov d0, #-8.5
|
|
__ fmovd(v0, -16.0); // fmov d0, #-16.0
|
|
__ fmovd(v0, -17.0); // fmov d0, #-17.0
|
|
__ fmovd(v0, -0.125); // fmov d0, #-0.125
|
|
__ fmovd(v0, -0.1328125); // fmov d0, #-0.1328125
|
|
__ fmovd(v0, -0.25); // fmov d0, #-0.25
|
|
__ fmovd(v0, -0.265625); // fmov d0, #-0.265625
|
|
__ fmovd(v0, -0.5); // fmov d0, #-0.5
|
|
__ fmovd(v0, -0.53125); // fmov d0, #-0.53125
|
|
__ fmovd(v0, -1.0); // fmov d0, #-1.0
|
|
__ fmovd(v0, -1.0625); // fmov d0, #-1.0625
|
|
|
|
// LSEOp
|
|
__ swp(Assembler::xword, r12, r20, r8); // swp x12, x20, [x8]
|
|
__ ldadd(Assembler::xword, r25, r20, r19); // ldadd x25, x20, [x19]
|
|
__ ldbic(Assembler::xword, r0, r11, r24); // ldclr x0, x11, [x24]
|
|
__ ldeor(Assembler::xword, r6, r20, sp); // ldeor x6, x20, [sp]
|
|
__ ldorr(Assembler::xword, r14, r16, r6); // ldset x14, x16, [x6]
|
|
__ ldsmin(Assembler::xword, r0, r7, r15); // ldsmin x0, x7, [x15]
|
|
__ ldsmax(Assembler::xword, r19, r26, r9); // ldsmax x19, x26, [x9]
|
|
__ ldumin(Assembler::xword, r10, r23, r21); // ldumin x10, x23, [x21]
|
|
__ ldumax(Assembler::xword, r22, r28, r2); // ldumax x22, x28, [x2]
|
|
|
|
// LSEOp
|
|
__ swpa(Assembler::xword, r3, r15, r19); // swpa x3, x15, [x19]
|
|
__ ldadda(Assembler::xword, r20, r7, r4); // ldadda x20, x7, [x4]
|
|
__ ldbica(Assembler::xword, r29, r7, r0); // ldclra x29, x7, [x0]
|
|
__ ldeora(Assembler::xword, r9, r16, r20); // ldeora x9, x16, [x20]
|
|
__ ldorra(Assembler::xword, r23, r4, r16); // ldseta x23, x4, [x16]
|
|
__ ldsmina(Assembler::xword, r10, r23, r11); // ldsmina x10, x23, [x11]
|
|
__ ldsmaxa(Assembler::xword, r25, r6, sp); // ldsmaxa x25, x6, [sp]
|
|
__ ldumina(Assembler::xword, r16, r13, r23); // ldumina x16, x13, [x23]
|
|
__ ldumaxa(Assembler::xword, r12, r1, r14); // ldumaxa x12, x1, [x14]
|
|
|
|
// LSEOp
|
|
__ swpal(Assembler::xword, r9, r21, r16); // swpal x9, x21, [x16]
|
|
__ ldaddal(Assembler::xword, r26, r15, r4); // ldaddal x26, x15, [x4]
|
|
__ ldbical(Assembler::xword, r4, r16, r8); // ldclral x4, x16, [x8]
|
|
__ ldeoral(Assembler::xword, r6, r30, r4); // ldeoral x6, x30, [x4]
|
|
__ ldorral(Assembler::xword, r29, r17, r29); // ldsetal x29, x17, [x29]
|
|
__ ldsminal(Assembler::xword, r26, r9, r15); // ldsminal x26, x9, [x15]
|
|
__ ldsmaxal(Assembler::xword, r2, r11, r29); // ldsmaxal x2, x11, [x29]
|
|
__ lduminal(Assembler::xword, r3, r7, r1); // lduminal x3, x7, [x1]
|
|
__ ldumaxal(Assembler::xword, r27, r21, r15); // ldumaxal x27, x21, [x15]
|
|
|
|
// LSEOp
|
|
__ swpl(Assembler::xword, r14, r8, r15); // swpl x14, x8, [x15]
|
|
__ ldaddl(Assembler::xword, r22, r25, r5); // ldaddl x22, x25, [x5]
|
|
__ ldbicl(Assembler::xword, r20, r21, r15); // ldclrl x20, x21, [x15]
|
|
__ ldeorl(Assembler::xword, r23, r16, r30); // ldeorl x23, x16, [x30]
|
|
__ ldorrl(Assembler::xword, r20, r20, r0); // ldsetl x20, x20, [x0]
|
|
__ ldsminl(Assembler::xword, r4, r19, r24); // ldsminl x4, x19, [x24]
|
|
__ ldsmaxl(Assembler::xword, r4, r20, r4); // ldsmaxl x4, x20, [x4]
|
|
__ lduminl(Assembler::xword, r24, r26, r19); // lduminl x24, x26, [x19]
|
|
__ ldumaxl(Assembler::xword, r2, r8, r8); // ldumaxl x2, x8, [x8]
|
|
|
|
// LSEOp
|
|
__ swp(Assembler::word, r14, r24, r15); // swp w14, w24, [x15]
|
|
__ ldadd(Assembler::word, zr, r22, r4); // ldadd wzr, w22, [x4]
|
|
__ ldbic(Assembler::word, zr, r1, r10); // ldclr wzr, w1, [x10]
|
|
__ ldeor(Assembler::word, r20, r12, r0); // ldeor w20, w12, [x0]
|
|
__ ldorr(Assembler::word, r9, r7, r24); // ldset w9, w7, [x24]
|
|
__ ldsmin(Assembler::word, r16, r4, r27); // ldsmin w16, w4, [x27]
|
|
__ ldsmax(Assembler::word, r6, r10, r27); // ldsmax w6, w10, [x27]
|
|
__ ldumin(Assembler::word, r24, r13, r16); // ldumin w24, w13, [x16]
|
|
__ ldumax(Assembler::word, zr, r22, r22); // ldumax wzr, w22, [x22]
|
|
|
|
// LSEOp
|
|
__ swpa(Assembler::word, r20, zr, r29); // swpa w20, wzr, [x29]
|
|
__ ldadda(Assembler::word, r9, r14, r20); // ldadda w9, w14, [x20]
|
|
__ ldbica(Assembler::word, r7, r20, r28); // ldclra w7, w20, [x28]
|
|
__ ldeora(Assembler::word, r9, r11, r14); // ldeora w9, w11, [x14]
|
|
__ ldorra(Assembler::word, r12, r20, r1); // ldseta w12, w20, [x1]
|
|
__ ldsmina(Assembler::word, r24, r9, r19); // ldsmina w24, w9, [x19]
|
|
__ ldsmaxa(Assembler::word, r13, r19, r15); // ldsmaxa w13, w19, [x15]
|
|
__ ldumina(Assembler::word, r16, r5, r0); // ldumina w16, w5, [x0]
|
|
__ ldumaxa(Assembler::word, r3, r12, r8); // ldumaxa w3, w12, [x8]
|
|
|
|
// LSEOp
|
|
__ swpal(Assembler::word, r15, r15, r16); // swpal w15, w15, [x16]
|
|
__ ldaddal(Assembler::word, r4, r15, r30); // ldaddal w4, w15, [x30]
|
|
__ ldbical(Assembler::word, r5, r0, r10); // ldclral w5, w0, [x10]
|
|
__ ldeoral(Assembler::word, r22, r27, r3); // ldeoral w22, w27, [x3]
|
|
__ ldorral(Assembler::word, r0, r9, r19); // ldsetal w0, w9, [x19]
|
|
__ ldsminal(Assembler::word, r29, r10, r24); // ldsminal w29, w10, [x24]
|
|
__ ldsmaxal(Assembler::word, r4, r20, r7); // ldsmaxal w4, w20, [x7]
|
|
__ lduminal(Assembler::word, r24, r29, r14); // lduminal w24, w29, [x14]
|
|
__ ldumaxal(Assembler::word, r21, r11, r27); // ldumaxal w21, w11, [x27]
|
|
|
|
// LSEOp
|
|
__ swpl(Assembler::word, r13, r16, sp); // swpl w13, w16, [sp]
|
|
__ ldaddl(Assembler::word, r17, r14, r3); // ldaddl w17, w14, [x3]
|
|
__ ldbicl(Assembler::word, r30, r16, r22); // ldclrl w30, w16, [x22]
|
|
__ ldeorl(Assembler::word, r20, r7, r20); // ldeorl w20, w7, [x20]
|
|
__ ldorrl(Assembler::word, r3, r1, r26); // ldsetl w3, w1, [x26]
|
|
__ ldsminl(Assembler::word, r19, r9, r16); // ldsminl w19, w9, [x16]
|
|
__ ldsmaxl(Assembler::word, r17, r21, r0); // ldsmaxl w17, w21, [x0]
|
|
__ lduminl(Assembler::word, r4, r2, r24); // lduminl w4, w2, [x24]
|
|
__ ldumaxl(Assembler::word, r14, r6, r11); // ldumaxl w14, w6, [x11]
|
|
|
|
// SHA3SIMDOp
|
|
__ bcax(v21, __ T16B, v14, v17, v30); // bcax v21.16B, v14.16B, v17.16B, v30.16B
|
|
__ eor3(v12, __ T16B, v3, v3, v23); // eor3 v12.16B, v3.16B, v3.16B, v23.16B
|
|
__ rax1(v9, __ T2D, v3, v24); // rax1 v9.2D, v3.2D, v24.2D
|
|
__ xar(v28, __ T2D, v3, v19, 47); // xar v28.2D, v3.2D, v19.2D, #47
|
|
|
|
// SHA512SIMDOp
|
|
__ sha512h(v7, __ T2D, v26, v21); // sha512h q7, q26, v21.2D
|
|
__ sha512h2(v14, __ T2D, v5, v8); // sha512h2 q14, q5, v8.2D
|
|
__ sha512su0(v26, __ T2D, v5); // sha512su0 v26.2D, v5.2D
|
|
__ sha512su1(v22, __ T2D, v18, v17); // sha512su1 v22.2D, v18.2D, v17.2D
|
|
|
|
// SVEBinaryImmOp
|
|
__ sve_add(z0, __ B, 79u); // add z0.b, z0.b, #0x4f
|
|
__ sve_sub(z20, __ H, 65u); // sub z20.h, z20.h, #0x41
|
|
__ sve_and(z12, __ H, 33279u); // and z12.h, z12.h, #0x81ff
|
|
__ sve_eor(z11, __ H, 49663u); // eor z11.h, z11.h, #0xc1ff
|
|
__ sve_orr(z31, __ S, 2147484159u); // orr z31.s, z31.s, #0x800001ff
|
|
|
|
// SVEBinaryImmOp
|
|
__ sve_add(z15, __ D, 188u); // add z15.d, z15.d, #0xbc
|
|
__ sve_sub(z28, __ S, 64u); // sub z28.s, z28.s, #0x40
|
|
__ sve_and(z8, __ B, 243u); // and z8.b, z8.b, #0xf3
|
|
__ sve_eor(z10, __ B, 239u); // eor z10.b, z10.b, #0xef
|
|
__ sve_orr(z22, __ S, 32768u); // orr z22.s, z22.s, #0x8000
|
|
|
|
// SVEBinaryImmOp
|
|
__ sve_add(z23, __ D, 46u); // add z23.d, z23.d, #0x2e
|
|
__ sve_sub(z26, __ D, 154u); // sub z26.d, z26.d, #0x9a
|
|
__ sve_and(z17, __ B, 128u); // and z17.b, z17.b, #0x80
|
|
__ sve_eor(z30, __ H, 49663u); // eor z30.h, z30.h, #0xc1ff
|
|
__ sve_orr(z2, __ D, 18444492273897963519u); // orr z2.d, z2.d, #0xfff80000001fffff
|
|
|
|
// SVEBinaryImmOp
|
|
__ sve_add(z22, __ D, 103u); // add z22.d, z22.d, #0x67
|
|
__ sve_sub(z8, __ B, 5u); // sub z8.b, z8.b, #0x5
|
|
__ sve_and(z15, __ S, 1u); // and z15.s, z15.s, #0x1
|
|
__ sve_eor(z19, __ D, 18446532967477018623u); // eor z19.d, z19.d, #0xffff3fffffffffff
|
|
__ sve_orr(z13, __ S, 7168u); // orr z13.s, z13.s, #0x1c00
|
|
|
|
// SVEBinaryImmOp
|
|
__ sve_add(z1, __ H, 164u); // add z1.h, z1.h, #0xa4
|
|
__ sve_sub(z12, __ S, 194u); // sub z12.s, z12.s, #0xc2
|
|
__ sve_and(z24, __ H, 33279u); // and z24.h, z24.h, #0x81ff
|
|
__ sve_eor(z20, __ S, 917504u); // eor z20.s, z20.s, #0xe0000
|
|
__ sve_orr(z21, __ H, 57343u); // orr z21.h, z21.h, #0xdfff
|
|
|
|
// SVEBinaryImmOp
|
|
__ sve_add(z31, __ D, 213u); // add z31.d, z31.d, #0xd5
|
|
__ sve_sub(z18, __ S, 120u); // sub z18.s, z18.s, #0x78
|
|
__ sve_and(z11, __ H, 51199u); // and z11.h, z11.h, #0xc7ff
|
|
__ sve_eor(z5, __ B, 128u); // eor z5.b, z5.b, #0x80
|
|
__ sve_orr(z2, __ B, 124u); // orr z2.b, z2.b, #0x7c
|
|
|
|
// SVEVectorOp
|
|
__ sve_add(z19, __ H, z4, z26); // add z19.h, z4.h, z26.h
|
|
__ sve_sub(z2, __ B, z3, z30); // sub z2.b, z3.b, z30.b
|
|
__ sve_fadd(z20, __ D, z5, z20); // fadd z20.d, z5.d, z20.d
|
|
__ sve_fmul(z29, __ S, z13, z13); // fmul z29.s, z13.s, z13.s
|
|
__ sve_fsub(z14, __ S, z30, z1); // fsub z14.s, z30.s, z1.s
|
|
__ sve_sqadd(z28, __ D, z3, z3); // sqadd z28.d, z3.d, z3.d
|
|
__ sve_sqsub(z9, __ B, z25, z9); // sqsub z9.b, z25.b, z9.b
|
|
__ sve_uqadd(z26, __ B, z10, z14); // uqadd z26.b, z10.b, z14.b
|
|
__ sve_uqsub(z20, __ D, z26, z7); // uqsub z20.d, z26.d, z7.d
|
|
__ sve_abs(z20, __ D, p4, z6); // abs z20.d, p4/m, z6.d
|
|
__ sve_add(z13, __ H, p0, z29); // add z13.h, p0/m, z13.h, z29.h
|
|
__ sve_and(z9, __ B, p0, z1); // and z9.b, p0/m, z9.b, z1.b
|
|
__ sve_asr(z27, __ B, p6, z15); // asr z27.b, p6/m, z27.b, z15.b
|
|
__ sve_bic(z4, __ D, p7, z17); // bic z4.d, p7/m, z4.d, z17.d
|
|
__ sve_clz(z2, __ B, p0, z24); // clz z2.b, p0/m, z24.b
|
|
__ sve_cnt(z26, __ B, p7, z13); // cnt z26.b, p7/m, z13.b
|
|
__ sve_eor(z22, __ D, p3, z16); // eor z22.d, p3/m, z22.d, z16.d
|
|
__ sve_lsl(z17, __ D, p1, z11); // lsl z17.d, p1/m, z17.d, z11.d
|
|
__ sve_lsr(z16, __ B, p0, z16); // lsr z16.b, p0/m, z16.b, z16.b
|
|
__ sve_mul(z28, __ D, p1, z23); // mul z28.d, p1/m, z28.d, z23.d
|
|
__ sve_neg(z28, __ S, p4, z10); // neg z28.s, p4/m, z10.s
|
|
__ sve_not(z17, __ S, p7, z7); // not z17.s, p7/m, z7.s
|
|
__ sve_orr(z4, __ H, p3, z24); // orr z4.h, p3/m, z4.h, z24.h
|
|
__ sve_rbit(z9, __ B, p2, z11); // rbit z9.b, p2/m, z11.b
|
|
__ sve_revb(z4, __ S, p5, z22); // revb z4.s, p5/m, z22.s
|
|
__ sve_smax(z4, __ H, p0, z15); // smax z4.h, p0/m, z4.h, z15.h
|
|
__ sve_smin(z4, __ D, p7, z26); // smin z4.d, p7/m, z4.d, z26.d
|
|
__ sve_umax(z5, __ H, p5, z26); // umax z5.h, p5/m, z5.h, z26.h
|
|
__ sve_umin(z31, __ B, p0, z25); // umin z31.b, p0/m, z31.b, z25.b
|
|
__ sve_sub(z8, __ S, p1, z3); // sub z8.s, p1/m, z8.s, z3.s
|
|
__ sve_fabs(z7, __ D, p6, z24); // fabs z7.d, p6/m, z24.d
|
|
__ sve_fadd(z24, __ S, p7, z17); // fadd z24.s, p7/m, z24.s, z17.s
|
|
__ sve_fdiv(z10, __ S, p3, z30); // fdiv z10.s, p3/m, z10.s, z30.s
|
|
__ sve_fmax(z8, __ S, p6, z29); // fmax z8.s, p6/m, z8.s, z29.s
|
|
__ sve_fmin(z31, __ D, p5, z31); // fmin z31.d, p5/m, z31.d, z31.d
|
|
__ sve_fmul(z0, __ D, p5, z7); // fmul z0.d, p5/m, z0.d, z7.d
|
|
__ sve_fneg(z29, __ S, p6, z22); // fneg z29.s, p6/m, z22.s
|
|
__ sve_frintm(z29, __ S, p6, z20); // frintm z29.s, p6/m, z20.s
|
|
__ sve_frintn(z6, __ S, p4, z18); // frintn z6.s, p4/m, z18.s
|
|
__ sve_frintp(z26, __ S, p5, z8); // frintp z26.s, p5/m, z8.s
|
|
__ sve_fsqrt(z19, __ S, p2, z28); // fsqrt z19.s, p2/m, z28.s
|
|
__ sve_fsub(z17, __ D, p1, z30); // fsub z17.d, p1/m, z17.d, z30.d
|
|
__ sve_fmad(z24, __ S, p7, z14, z17); // fmad z24.s, p7/m, z14.s, z17.s
|
|
__ sve_fmla(z19, __ D, p2, z26, z11); // fmla z19.d, p2/m, z26.d, z11.d
|
|
__ sve_fmls(z0, __ D, p2, z15, z28); // fmls z0.d, p2/m, z15.d, z28.d
|
|
__ sve_fmsb(z23, __ D, p5, z28, z23); // fmsb z23.d, p5/m, z28.d, z23.d
|
|
__ sve_fnmad(z29, __ S, p6, z0, z27); // fnmad z29.s, p6/m, z0.s, z27.s
|
|
__ sve_fnmsb(z23, __ S, p3, z12, z4); // fnmsb z23.s, p3/m, z12.s, z4.s
|
|
__ sve_fnmla(z31, __ S, p6, z23, z20); // fnmla z31.s, p6/m, z23.s, z20.s
|
|
__ sve_fnmls(z2, __ D, p7, z29, z0); // fnmls z2.d, p7/m, z29.d, z0.d
|
|
__ sve_mla(z23, __ H, p0, z4, z5); // mla z23.h, p0/m, z4.h, z5.h
|
|
__ sve_mls(z28, __ H, p3, z17, z13); // mls z28.h, p3/m, z17.h, z13.h
|
|
__ sve_and(z8, z10, z8); // and z8.d, z10.d, z8.d
|
|
__ sve_eor(z19, z0, z29); // eor z19.d, z0.d, z29.d
|
|
__ sve_orr(z16, z13, z23); // orr z16.d, z13.d, z23.d
|
|
__ sve_bic(z23, z30, z13); // bic z23.d, z30.d, z13.d
|
|
__ sve_uzp1(z25, __ H, z22, z0); // uzp1 z25.h, z22.h, z0.h
|
|
__ sve_uzp2(z25, __ H, z30, z11); // uzp2 z25.h, z30.h, z11.h
|
|
__ sve_fabd(z14, __ S, p5, z22); // fabd z14.s, p5/m, z14.s, z22.s
|
|
__ sve_bext(z5, __ H, z18, z0); // bext z5.h, z18.h, z0.h
|
|
__ sve_bdep(z9, __ D, z2, z3); // bdep z9.d, z2.d, z3.d
|
|
__ sve_eor3(z14, z4, z29); // eor3 z14.d, z14.d, z4.d, z29.d
|
|
__ sve_sqadd(z14, __ D, p5, z4); // sqadd z14.d, p5/m, z14.d, z4.d
|
|
__ sve_sqsub(z27, __ S, p3, z22); // sqsub z27.s, p3/m, z27.s, z22.s
|
|
__ sve_uqadd(z31, __ S, p6, z11); // uqadd z31.s, p6/m, z31.s, z11.s
|
|
__ sve_uqsub(z12, __ B, p4, z28); // uqsub z12.b, p4/m, z12.b, z28.b
|
|
|
|
// SVEReductionOp
|
|
__ sve_andv(v28, __ D, p4, z4); // andv d28, p4, z4.d
|
|
__ sve_orv(v6, __ S, p0, z15); // orv s6, p0, z15.s
|
|
__ sve_eorv(v1, __ S, p5, z18); // eorv s1, p5, z18.s
|
|
__ sve_smaxv(v2, __ H, p2, z4); // smaxv h2, p2, z4.h
|
|
__ sve_sminv(v11, __ S, p2, z28); // sminv s11, p2, z28.s
|
|
__ sve_umaxv(v3, __ H, p5, z31); // umaxv h3, p5, z31.h
|
|
__ sve_uminv(v24, __ H, p5, z15); // uminv h24, p5, z15.h
|
|
__ sve_fminv(v6, __ S, p3, z8); // fminv s6, p3, z8.s
|
|
__ sve_fmaxv(v21, __ D, p7, z4); // fmaxv d21, p7, z4.d
|
|
__ sve_fadda(v24, __ S, p5, z6); // fadda s24, p5, s24, z6.s
|
|
__ sve_uaddv(v4, __ D, p2, z9); // uaddv d4, p2, z9.d
|
|
|
|
// AddWideNEONOp
|
|
__ saddwv(v10, v11, __ T8H, v12, __ T8B); // saddw v10.8H, v11.8H, v12.8B
|
|
__ saddwv2(v5, v6, __ T8H, v7, __ T16B); // saddw2 v5.8H, v6.8H, v7.16B
|
|
__ saddwv(v31, v0, __ T4S, v1, __ T4H); // saddw v31.4S, v0.4S, v1.4H
|
|
__ saddwv2(v22, v23, __ T4S, v24, __ T8H); // saddw2 v22.4S, v23.4S, v24.8H
|
|
__ saddwv(v25, v26, __ T2D, v27, __ T2S); // saddw v25.2D, v26.2D, v27.2S
|
|
__ saddwv2(v15, v16, __ T2D, v17, __ T4S); // saddw2 v15.2D, v16.2D, v17.4S
|
|
__ uaddwv(v3, v4, __ T8H, v5, __ T8B); // uaddw v3.8H, v4.8H, v5.8B
|
|
__ uaddwv2(v18, v19, __ T8H, v20, __ T16B); // uaddw2 v18.8H, v19.8H, v20.16B
|
|
__ uaddwv(v14, v15, __ T4S, v16, __ T4H); // uaddw v14.4S, v15.4S, v16.4H
|
|
__ uaddwv2(v10, v11, __ T4S, v12, __ T8H); // uaddw2 v10.4S, v11.4S, v12.8H
|
|
__ uaddwv(v2, v3, __ T2D, v4, __ T2S); // uaddw v2.2D, v3.2D, v4.2S
|
|
__ uaddwv2(v10, v11, __ T2D, v12, __ T4S); // uaddw2 v10.2D, v11.2D, v12.4S
|
|
|
|
__ bind(forth);
|
|
|
|
/*
|
|
*/
|
|
|
|
static const unsigned int insns[] =
|
|
{
|
|
0x8b0d82fa, 0xcb49970c, 0xab889dfc, 0xeb9ee787,
|
|
0x0b9b3ec9, 0x4b9179a3, 0x2b88474e, 0x6b8c56c0,
|
|
0x8a1a51e0, 0xaa11f4ba, 0xca0281b8, 0xea918c7c,
|
|
0x0a5d4a19, 0x2a4b262d, 0x4a513ca5, 0x6a9b6ae2,
|
|
0x8a70b79b, 0xaaba9728, 0xca6dfe3d, 0xea627f1c,
|
|
0x0aa70f53, 0x2aaa0f06, 0x4a6176a4, 0x6a604eb0,
|
|
0x1105ed91, 0x3100583e, 0x5101f8bd, 0x710f0306,
|
|
0x9101a1a0, 0xb10a5cc8, 0xd10810aa, 0xf10fd061,
|
|
0x120cb166, 0x321764bc, 0x52174681, 0x720c0227,
|
|
0x9241018e, 0xb25a2969, 0xd278b411, 0xf26aad01,
|
|
0x14000000, 0x17ffffd7, 0x140004cb, 0x94000000,
|
|
0x97ffffd4, 0x940004c8, 0x3400000a, 0x34fffa2a,
|
|
0x340098aa, 0x35000008, 0x35fff9c8, 0x35009848,
|
|
0xb400000b, 0xb4fff96b, 0xb40097eb, 0xb500001d,
|
|
0xb5fff91d, 0xb500979d, 0x10000013, 0x10fff8b3,
|
|
0x10009733, 0x90000013, 0x36300016, 0x3637f836,
|
|
0x363096b6, 0x3758000c, 0x375ff7cc, 0x3758964c,
|
|
0x128313a0, 0x528a32c7, 0x7289173b, 0x92ab3acc,
|
|
0xd2a0bf94, 0xf2c285e8, 0x9358722f, 0x330e652f,
|
|
0x53067f3b, 0x93577c53, 0xb34a1aac, 0xd35a4016,
|
|
0x13946c63, 0x93c3dbc8, 0x54000000, 0x54fff5a0,
|
|
0x54009420, 0x54000001, 0x54fff541, 0x540093c1,
|
|
0x54000002, 0x54fff4e2, 0x54009362, 0x54000002,
|
|
0x54fff482, 0x54009302, 0x54000003, 0x54fff423,
|
|
0x540092a3, 0x54000003, 0x54fff3c3, 0x54009243,
|
|
0x54000004, 0x54fff364, 0x540091e4, 0x54000005,
|
|
0x54fff305, 0x54009185, 0x54000006, 0x54fff2a6,
|
|
0x54009126, 0x54000007, 0x54fff247, 0x540090c7,
|
|
0x54000008, 0x54fff1e8, 0x54009068, 0x54000009,
|
|
0x54fff189, 0x54009009, 0x5400000a, 0x54fff12a,
|
|
0x54008faa, 0x5400000b, 0x54fff0cb, 0x54008f4b,
|
|
0x5400000c, 0x54fff06c, 0x54008eec, 0x5400000d,
|
|
0x54fff00d, 0x54008e8d, 0x5400000e, 0x54ffefae,
|
|
0x54008e2e, 0x5400000f, 0x54ffef4f, 0x54008dcf,
|
|
0xd40658e1, 0xd4014d22, 0xd4046543, 0xd4273f60,
|
|
0xd44cad80, 0xd503201f, 0xd503203f, 0xd503205f,
|
|
0xd503209f, 0xd50320bf, 0xd503219f, 0xd50323bf,
|
|
0xd503239f, 0xd50321df, 0xd50323ff, 0xd50323df,
|
|
0xd503211f, 0xd503233f, 0xd503231f, 0xd503215f,
|
|
0xd503237f, 0xd503235f, 0xd69f03e0, 0xd6bf03e0,
|
|
0xd5033fdf, 0xd50330ff, 0xd503101a, 0xd503207f,
|
|
0xd50320ff, 0xd503329f, 0xd50339bf, 0xd61f0280,
|
|
0xd63f0140, 0xdac123fb, 0xdac127e8, 0xdac12be0,
|
|
0xdac12fe1, 0xdac133f5, 0xdac137f1, 0xdac13bfd,
|
|
0xdac13ffd, 0xdac147fc, 0xd61f083f, 0xd61f0eff,
|
|
0xd63f0abf, 0xd63f0e9f, 0xd51b4436, 0xd51b421b,
|
|
0xd53b4433, 0xd53b420b, 0xd53b00f0, 0xd53b0026,
|
|
0xd53be0d1, 0xdac143e0, 0xc8047f0a, 0xc816fe6a,
|
|
0xc85f7ca1, 0xc85ffd1e, 0xc89ffe2c, 0xc8dffdc9,
|
|
0x88077ca1, 0x8810fd82, 0x885f7d8a, 0x885fff83,
|
|
0x889fff4e, 0x88dffd5e, 0x480e7db5, 0x4809ff76,
|
|
0x485f7e7c, 0x485fffcb, 0x489ffc53, 0x48dffee2,
|
|
0x08017d80, 0x0810fded, 0x085f7eb1, 0x085ffd6d,
|
|
0x089ffd1e, 0x08dffdb8, 0xc87f074b, 0xc87fedb5,
|
|
0xc83430c3, 0xc821989d, 0x887f2e06, 0x887ff984,
|
|
0x88353f9b, 0x8829d0cf, 0xf8183238, 0xb800a341,
|
|
0x381ef00f, 0x7800d231, 0xf8431325, 0xb858c1f3,
|
|
0x39401c74, 0x785e7093, 0x389fa26e, 0x789cb27c,
|
|
0x78c0d36e, 0xb8988306, 0xfc457052, 0xbc5d0380,
|
|
0xfc01739f, 0xbc02b32b, 0xf8147d0e, 0xb81a3d39,
|
|
0x381f4ef0, 0x781c8d36, 0xf846df0b, 0xb8434e75,
|
|
0x385feee6, 0x78415d07, 0x389e1d84, 0x789fcd68,
|
|
0x78de4eae, 0xb89b9de0, 0xfc41dc5b, 0xbc410ead,
|
|
0xfc010f6c, 0xbc1a5f22, 0xf81eb5aa, 0xb8032427,
|
|
0x3800546a, 0x781df4c5, 0xf85626cd, 0xb859644d,
|
|
0x385e860d, 0x785ea458, 0x389ff6e3, 0x789d5513,
|
|
0x78df86e2, 0xb89a9793, 0xfc5af46f, 0xbc5b17ac,
|
|
0xfc184435, 0xbc19d527, 0xf8226a85, 0xb83ed94e,
|
|
0x383cd824, 0x783af945, 0xf87c7856, 0xb87c780c,
|
|
0x386ff908, 0x786e5ab1, 0x38a8fb11, 0x78bef94a,
|
|
0x78e07af1, 0xb8a07bd9, 0xfc775b05, 0xbc6f7876,
|
|
0xfc30fba4, 0xbc3cda87, 0xf91ff41b, 0xb91f3115,
|
|
0x391c0fb1, 0x791c685b, 0xf9586021, 0xb958b23d,
|
|
0x39598921, 0x795d3077, 0x399d0675, 0x7998d8f3,
|
|
0x79dbd02a, 0xb99d068a, 0xfd5d11a0, 0xbd58d76b,
|
|
0xfd1ac72d, 0xbd1d9c14, 0x5800001a, 0x18ffda33,
|
|
0xf8991100, 0xd8007880, 0xf8a758e0, 0xf9989d80,
|
|
0x1a0b0298, 0x3a1c01a0, 0x5a0400ea, 0x7a02020f,
|
|
0x9a1d028c, 0xba0e01ad, 0xda140186, 0xfa19022c,
|
|
0x0b2b877e, 0x2b21c8ee, 0xcb3ba47d, 0x6b3ae9a0,
|
|
0x8b256a36, 0xab28efd1, 0xcb37ce6a, 0xeb254fa6,
|
|
0x3a498264, 0x7a4a72c2, 0xba4c91aa, 0xfa502303,
|
|
0x3a4b68ed, 0x7a4a9b6b, 0xba4dd86d, 0xfa50cb45,
|
|
0x1a9cd2aa, 0x1a9bd537, 0x5a8fd3aa, 0x5a95273e,
|
|
0x9a95c220, 0x9a9426b0, 0xda8393d3, 0xda980573,
|
|
0x5ac0033b, 0x5ac0046e, 0x5ac00a2e, 0x5ac011e7,
|
|
0x5ac01798, 0xdac00331, 0xdac00742, 0xdac008bc,
|
|
0xdac00f59, 0xdac0121b, 0xdac014d1, 0xdac10195,
|
|
0xdac10480, 0xdac10b6c, 0xdac10f91, 0xdac1105c,
|
|
0xdac11551, 0xdac119cf, 0xdac11c6e, 0xd71f0b2f,
|
|
0xd71f0e6e, 0xd73f08b0, 0xd73f0c9a, 0x1ac20899,
|
|
0x1add0d82, 0x1ac72111, 0x1ad92483, 0x1ad92b44,
|
|
0x1ac02e24, 0x9ad70a3a, 0x9adc0eaf, 0x9aca2371,
|
|
0x9ac72403, 0x9ac62939, 0x9acf2faf, 0x9bd17c4a,
|
|
0x9b4b7d67, 0x1b1d5cf7, 0x1b0baf6e, 0x9b0c3f04,
|
|
0x9b0bf28e, 0x9b2c5d6d, 0x9b2ea75e, 0x9ba7154d,
|
|
0x9ba3adfd, 0x7edf160c, 0x1ef30a5f, 0x1eef1a15,
|
|
0x1ee22aaa, 0x1ee73b8a, 0x1ef24bfe, 0x1ee65841,
|
|
0x1ef9886a, 0x7ea1d4eb, 0x1e23080c, 0x1e261bb3,
|
|
0x1e2028d7, 0x1e223b7c, 0x1e3d48e5, 0x1e2d5b2c,
|
|
0x1e338b0c, 0x7ef6d648, 0x1e740aba, 0x1e7e1853,
|
|
0x1e762916, 0x1e6c3ab3, 0x1e664ab2, 0x1e635870,
|
|
0x1e7c887d, 0x1fca35cf, 0x1f0a6a4c, 0x1f0ff4e7,
|
|
0x1f2032e0, 0x1f2d21d8, 0x1f4950ef, 0x1f5fc3b3,
|
|
0x1f705522, 0x1f616c9e, 0x1e204319, 0x1e20c2ae,
|
|
0x1e2140cd, 0x1e21c32c, 0x1e22c3d9, 0x1e23c2bc,
|
|
0x1ee242f0, 0x1e6043a5, 0x1e60c276, 0x1e61428d,
|
|
0x1e61c393, 0x1e6240d2, 0x1ee1c0ee, 0x1e38035c,
|
|
0x9e3800d1, 0x1e780081, 0x9e7802ad, 0x1e2202a7,
|
|
0x9e2202fb, 0x1e62028d, 0x9e62037f, 0x1e2402aa,
|
|
0x9e640225, 0x1e3001cb, 0x9e7002ad, 0x1e2601da,
|
|
0x9e660304, 0x1e2703b8, 0x9e6701cc, 0x1e3c2220,
|
|
0x1e6022c0, 0x1e2020c8, 0x1e602368, 0x293c30db,
|
|
0x29602e6e, 0x697a31e0, 0xa9025ee9, 0xa975134f,
|
|
0x29ac20d1, 0x29f20887, 0x69fe26ce, 0xa9b0530d,
|
|
0xa9c62d48, 0x28b21618, 0x28f06920, 0x68f00a38,
|
|
0xa8bd45da, 0xa8c357be, 0x28325d51, 0x286c1bda,
|
|
0xa804229e, 0xa8437536, 0x0c40702d, 0x4cdfa201,
|
|
0x0cd36f36, 0x4cdf2759, 0x0d40c1e9, 0x4ddfcb2c,
|
|
0x0dddcdc4, 0x4c408e31, 0x0cdf8777, 0x4d60c302,
|
|
0x0dffc80b, 0x4df6cd82, 0x4ccd49b5, 0x0c40496c,
|
|
0x4d40e5d2, 0x4ddfeab9, 0x0ddbee14, 0x4cdf0420,
|
|
0x0cdd0360, 0x0d60e232, 0x0dffe705, 0x0df4e8bc,
|
|
0x0e31b841, 0x4e31bab4, 0x0e71bbdd, 0x4e71ba30,
|
|
0x4eb1b9cd, 0x0e30a96a, 0x4e30abdd, 0x0e70abdd,
|
|
0x4e70aa93, 0x4eb0aaf6, 0x6e30f96a, 0x0e31a8a4,
|
|
0x2e31a81f, 0x4e31aad5, 0x6e31a928, 0x0e71a81f,
|
|
0x2e71aa93, 0x4e71a96a, 0x6e71abbc, 0x4eb1a862,
|
|
0x6eb1ab59, 0x6eb0f8c5, 0x7e30f883, 0x7e70f928,
|
|
0x7eb0faf6, 0x7ef0fa93, 0x0ea0c9cd, 0x4ea0c8c5,
|
|
0x4ee0cbdd, 0x2ea0cb38, 0x6ea0cad5, 0x6ee0cb7a,
|
|
0x0ea0db38, 0x4ea0d883, 0x4ee0db38, 0x0ea0eb7a,
|
|
0x4ea0eb17, 0x4ee0ea0f, 0x2ea0dad5, 0x6ea0d883,
|
|
0x6ee0db38, 0x0e20b928, 0x4e20bb59, 0x0e60bab4,
|
|
0x4e60ba30, 0x0ea0ba51, 0x4ea0b862, 0x4ee0b841,
|
|
0x0ea0f820, 0x4ea0fb38, 0x4ee0f8a4, 0x0ef8f883,
|
|
0x4ef8f9ac, 0x2ea0f81f, 0x6ea0fbbc, 0x6ee0f96a,
|
|
0x2ef8fb7a, 0x6ef8f862, 0x2ea1f9ac, 0x6ea1fa72,
|
|
0x6ee1f81f, 0x2ef9f841, 0x6ef9f9cd, 0x2e205bdd,
|
|
0x6e205820, 0x0e351e93, 0x4e2e1dac, 0x0eb31e51,
|
|
0x4eb81ef6, 0x2e2f1dcd, 0x6e3e1fbc, 0x0e2087fe,
|
|
0x4e21841f, 0x0e638441, 0x4e7c877a, 0x0ebe87bc,
|
|
0x4ea684a4, 0x4ee087fe, 0x0e260ca4, 0x4e280ce6,
|
|
0x0e600ffe, 0x4e7c0f7a, 0x0eb40e72, 0x4eab0d49,
|
|
0x4eea0d28, 0x2e2e0dac, 0x6e220c20, 0x2e760eb4,
|
|
0x6e630c41, 0x2eba0f38, 0x6ea40c62, 0x6ee20c20,
|
|
0x0e2bd549, 0x4e3ad738, 0x4e7cd77a, 0x0e521630,
|
|
0x4e4017fe, 0x2e258483, 0x6e2c856a, 0x2e798717,
|
|
0x6e6c856a, 0x2ea684a4, 0x6eb48672, 0x6ee48462,
|
|
0x0e2d2d8b, 0x4e2a2d28, 0x0e6c2d6a, 0x4e712e0f,
|
|
0x0eb32e51, 0x4ea42c62, 0x4eec2d6a, 0x2e2e2dac,
|
|
0x6e2e2dac, 0x2e712e0f, 0x6e6f2dcd, 0x2ea42c62,
|
|
0x6ea92d07, 0x6ef62eb4, 0x0ebcd77a, 0x4eb2d630,
|
|
0x4ee6d4a4, 0x0ec41462, 0x4ec614a4, 0x0e2e9dac,
|
|
0x4e349e72, 0x0e779ed5, 0x4e729e30, 0x0eb49e72,
|
|
0x4ead9d8b, 0x2eb7d6d5, 0x6eb9d717, 0x6eeed5ac,
|
|
0x2edc177a, 0x6ed91717, 0x2e3ed7bc, 0x6e30d5ee,
|
|
0x6e6dd58b, 0x2e5a1738, 0x6e431441, 0x2e2eddac,
|
|
0x6e21dc1f, 0x6e6cdd6a, 0x2e521e30, 0x6e491d07,
|
|
0x0e649462, 0x4e659483, 0x0eaf95cd, 0x4eb59693,
|
|
0x0e33ce51, 0x4e32ce30, 0x4e65cc83, 0x0e430c41,
|
|
0x4e4d0d8b, 0x2e6097fe, 0x6e6794c5, 0x2eaa9528,
|
|
0x6eb1960f, 0x0ebfcfdd, 0x4ea0cffe, 0x4ee2cc20,
|
|
0x0ed60eb4, 0x4ec90d07, 0x2e36feb4, 0x6e39ff17,
|
|
0x6e7effbc, 0x2e573ed5, 0x6e5d3f9b, 0x0e3b6759,
|
|
0x4e2764c5, 0x0e636441, 0x4e796717, 0x0eb26630,
|
|
0x4ea1641f, 0x2e2764c5, 0x6e2e65ac, 0x2e6b6549,
|
|
0x6e7e67bc, 0x2eb1660f, 0x6ebf67dd, 0x0e38a6f6,
|
|
0x4e21a41f, 0x0e75a693, 0x4e61a41f, 0x0ea7a4c5,
|
|
0x4eb0a5ee, 0x0e34f672, 0x4e21f41f, 0x4e74f672,
|
|
0x0e5d379b, 0x4e5636b4, 0x0e326e30, 0x4e2e6dac,
|
|
0x0e6d6d8b, 0x4e6b6d49, 0x0ea86ce6, 0x4ea06ffe,
|
|
0x2e336e51, 0x6e3d6f9b, 0x2e7e6fbc, 0x6e606ffe,
|
|
0x2ea96d07, 0x6eac6d6a, 0x0e36aeb4, 0x4e2cad6a,
|
|
0x0e66aca4, 0x4e7aaf38, 0x0eb3ae51, 0x4eb3ae51,
|
|
0x2e38aef6, 0x6e25ac83, 0x2e7fafdd, 0x6e71ae0f,
|
|
0x2eb8aef6, 0x6eb5ae93, 0x2e35a693, 0x6e38a6f6,
|
|
0x2e64a462, 0x6e71a60f, 0x2ea8a4e6, 0x6eaea5ac,
|
|
0x0e72b630, 0x4e6db58b, 0x0eafb5cd, 0x4eb9b717,
|
|
0x0e232441, 0x4e2027fe, 0x0e752693, 0x4e6724c5,
|
|
0x0eb32651, 0x4ea42462, 0x0eb2f630, 0x4eb8f6f6,
|
|
0x4eeff5cd, 0x0ecc356a, 0x4ed736d5, 0x2ebfefdd,
|
|
0x6ebdef9b, 0x6eeeedac, 0x2edd2f9b, 0x6ec52c83,
|
|
0x0f81100f, 0x4fab8949, 0x4fc618a4, 0x0faf51cd,
|
|
0x4fa58083, 0x4fcd598b, 0x2fae91ac, 0x4f81800f,
|
|
0x6fcb9949, 0x0f5d818b, 0x4f438841, 0x0fa28020,
|
|
0x4faf89cd, 0x0e393717, 0x4e243462, 0x0e743672,
|
|
0x4e6e35ac, 0x0ea634a4, 0x4ebe37bc, 0x4ee037fe,
|
|
0x0e3f3fdd, 0x4e323e30, 0x0e7d3f9b, 0x4e683ce6,
|
|
0x0eab3d49, 0x4ebf3fdd, 0x4ef43e72, 0x2e298d07,
|
|
0x6e268ca4, 0x2e698d07, 0x6e718e0f, 0x2eab8d49,
|
|
0x6eb98f17, 0x6eea8d28, 0x2e243462, 0x6e3e37bc,
|
|
0x2e7736d5, 0x6e61341f, 0x2ea734c5, 0x6ebd379b,
|
|
0x6ee23420, 0x2e333e51, 0x6e313e0f, 0x2e663ca4,
|
|
0x6e7c3f7a, 0x2eaa3d28, 0x6ebe3fbc, 0x6ef83ef6,
|
|
0x0e3de79b, 0x4e3de79b, 0x4e7be759, 0x2eb9e717,
|
|
0x6ea2e420, 0x6ee6e4a4, 0x2e28e4e6, 0x6e34e672,
|
|
0x6e62e420, 0x659229e2, 0x65903cb3, 0x65d03683,
|
|
0x65913163, 0x65d120df, 0x65d323c6, 0x25dd8ecd,
|
|
0x25d2063e, 0x258b0947, 0x2501358b, 0x25823032,
|
|
0x254181d6, 0x24a646a1, 0x24719e73, 0x24233cd8,
|
|
0x24adf4c2, 0xba5fd3e3, 0x3a5f03e5, 0xfa411be4,
|
|
0x7a42cbe2, 0x93df03ff, 0xc820ffff, 0x8822fc7f,
|
|
0xc8247cbf, 0x88267fff, 0x4e010fe0, 0x5e040420,
|
|
0x4e081fe1, 0x4e0c1fe1, 0x4e0a1fe1, 0x4e071fe1,
|
|
0x4e042c20, 0x4e062c20, 0x4e052c20, 0x4e083c20,
|
|
0x0e0c3c20, 0x0e0a3c20, 0x0e073c20, 0x9eae0020,
|
|
0x0f03f409, 0x6f03f40e, 0x4cc0ac3f, 0x0ea1b820,
|
|
0x0ef9b820, 0x4ef9b820, 0x4e21c862, 0x0e79c862,
|
|
0x4e79c862, 0x4e61b8a4, 0x0e79b8a4, 0x4e79b8a4,
|
|
0x05a08020, 0x05104fe0, 0x05505001, 0x05906fe2,
|
|
0x05d03005, 0x05101fea, 0x05901feb, 0x0590cc0b,
|
|
0x0590de0b, 0x04b0e3e0, 0x0470e7e1, 0x042f9c20,
|
|
0x043f9c35, 0x047f9c20, 0x04ff9c20, 0x04299420,
|
|
0x04319160, 0x0461943e, 0x04a19020, 0x04038100,
|
|
0x040381a0, 0x040387e1, 0x04438be2, 0x04c38fe3,
|
|
0x040181e0, 0x04018100, 0x04018621, 0x04418b22,
|
|
0x04418822, 0x04818c23, 0x040081e0, 0x04008120,
|
|
0x04008761, 0x04008621, 0x04408822, 0x04808c23,
|
|
0x042053ff, 0x047f5401, 0x25208028, 0x2538cfe0,
|
|
0x2578d001, 0x25b8efe2, 0x25f8f007, 0x2538dfea,
|
|
0x25b8dfeb, 0xa400a3e0, 0xa420a7e0, 0xa4484be0,
|
|
0xa467afe0, 0xa4a8a7ea, 0xa547a814, 0xa4084ffe,
|
|
0xa55c53e0, 0xa5e1540b, 0xe400fbf6, 0xe408ffff,
|
|
0xe420e7e0, 0xe4484be0, 0xe460efe0, 0xe547e400,
|
|
0xe4014be0, 0xe4a84fe0, 0xe5f15000, 0x858043e0,
|
|
0x85a043ff, 0xe59f5d08, 0x0420e3e9, 0x0460e3ea,
|
|
0x04a0e3eb, 0x04e0e3ec, 0x25104042, 0x25104871,
|
|
0x25904861, 0x25904c92, 0x05344020, 0x05744041,
|
|
0x05b44062, 0x05f44083, 0x252c8840, 0x253c1420,
|
|
0x25681572, 0x25a21ce3, 0x25ea1e34, 0x253c0421,
|
|
0x25680572, 0x25a20ce3, 0x25ea0e34, 0x0522c020,
|
|
0x05e6c0a4, 0x2401a001, 0x2443a051, 0x24858881,
|
|
0x24c78cd1, 0x24850891, 0x24c70cc1, 0x250f9001,
|
|
0x25508051, 0x25802491, 0x25df28c1, 0x25850c81,
|
|
0x251e10d1, 0x65816001, 0x65c36051, 0x65854891,
|
|
0x65c74cc1, 0x05733820, 0x05b238a4, 0x05f138e6,
|
|
0x0570396a, 0x65d0a001, 0x65d6a443, 0x65d4a826,
|
|
0x6594ac26, 0x6554ac26, 0x6556ac26, 0x6552ac26,
|
|
0x65cbac85, 0x65caac01, 0x6589ac85, 0x6588ac01,
|
|
0x65c9ac85, 0x65c8ac01, 0x65dea833, 0x659ca509,
|
|
0x65d8a801, 0x65dcac01, 0x655cb241, 0x0520a1e0,
|
|
0x0521a601, 0x052281e0, 0x05238601, 0x04a14026,
|
|
0x042244a6, 0x046344a6, 0x04a444a6, 0x04e544a7,
|
|
0x0568aca7, 0x05b23230, 0x05302a30, 0x05702a30,
|
|
0x05b02a30, 0x05f02a30, 0x853040af, 0xc5b040af,
|
|
0xe57080af, 0xe5b080af, 0x25034440, 0x254054c4,
|
|
0x25034640, 0x25415a05, 0x25834440, 0x25c54489,
|
|
0x250b5d3a, 0x2550dc20, 0x2518e3e1, 0x2518e021,
|
|
0x2518e0a1, 0x2518e121, 0x2518e1a1, 0x2558e3e2,
|
|
0x2558e042, 0x2558e0c2, 0x2558e142, 0x2598e3e3,
|
|
0x2598e063, 0x2598e0e3, 0x2598e163, 0x25d8e3e4,
|
|
0x25d8e084, 0x25d8e104, 0x25d8e184, 0x2518e407,
|
|
0x05214800, 0x05614800, 0x05a14800, 0x05e14800,
|
|
0x05214c00, 0x05614c00, 0x05a14c00, 0x05e14c00,
|
|
0x05304001, 0x05314001, 0x05a18610, 0x05e18610,
|
|
0x0420bc31, 0x05271e11, 0x6545e891, 0x6585e891,
|
|
0x65c5e891, 0x6545c891, 0x6585c891, 0x65c5c891,
|
|
0x052c8020, 0x056c8020, 0x05ac8020, 0x05ec8020,
|
|
0x45b0c210, 0x45f1c231, 0x1e601000, 0x1e603000,
|
|
0x1e621000, 0x1e623000, 0x1e641000, 0x1e643000,
|
|
0x1e661000, 0x1e663000, 0x1e681000, 0x1e683000,
|
|
0x1e6a1000, 0x1e6a3000, 0x1e6c1000, 0x1e6c3000,
|
|
0x1e6e1000, 0x1e6e3000, 0x1e701000, 0x1e703000,
|
|
0x1e721000, 0x1e723000, 0x1e741000, 0x1e743000,
|
|
0x1e761000, 0x1e763000, 0x1e781000, 0x1e783000,
|
|
0x1e7a1000, 0x1e7a3000, 0x1e7c1000, 0x1e7c3000,
|
|
0x1e7e1000, 0x1e7e3000, 0xf82c8114, 0xf8390274,
|
|
0xf820130b, 0xf82623f4, 0xf82e30d0, 0xf82051e7,
|
|
0xf833413a, 0xf82a72b7, 0xf836605c, 0xf8a3826f,
|
|
0xf8b40087, 0xf8bd1007, 0xf8a92290, 0xf8b73204,
|
|
0xf8aa5177, 0xf8b943e6, 0xf8b072ed, 0xf8ac61c1,
|
|
0xf8e98215, 0xf8fa008f, 0xf8e41110, 0xf8e6209e,
|
|
0xf8fd33b1, 0xf8fa51e9, 0xf8e243ab, 0xf8e37027,
|
|
0xf8fb61f5, 0xf86e81e8, 0xf87600b9, 0xf87411f5,
|
|
0xf87723d0, 0xf8743014, 0xf8645313, 0xf8644094,
|
|
0xf878727a, 0xf8626108, 0xb82e81f8, 0xb83f0096,
|
|
0xb83f1141, 0xb834200c, 0xb8293307, 0xb8305364,
|
|
0xb826436a, 0xb838720d, 0xb83f62d6, 0xb8b483bf,
|
|
0xb8a9028e, 0xb8a71394, 0xb8a921cb, 0xb8ac3034,
|
|
0xb8b85269, 0xb8ad41f3, 0xb8b07005, 0xb8a3610c,
|
|
0xb8ef820f, 0xb8e403cf, 0xb8e51140, 0xb8f6207b,
|
|
0xb8e03269, 0xb8fd530a, 0xb8e440f4, 0xb8f871dd,
|
|
0xb8f5636b, 0xb86d83f0, 0xb871006e, 0xb87e12d0,
|
|
0xb8742287, 0xb8633341, 0xb8735209, 0xb8714015,
|
|
0xb8647302, 0xb86e6166, 0xce3179d5, 0xce035c6c,
|
|
0xce788c69, 0xce93bc7c, 0xce758347, 0xce6884ae,
|
|
0xcec080ba, 0xce718a56, 0x2520c9e0, 0x2561c834,
|
|
0x05800d2c, 0x0540154b, 0x0500093f, 0x25e0d78f,
|
|
0x25a1c81c, 0x058026a8, 0x05401eca, 0x05008816,
|
|
0x25e0c5d7, 0x25e1d35a, 0x05800e11, 0x0540155e,
|
|
0x05026c22, 0x25e0ccf6, 0x2521c0a8, 0x0580000f,
|
|
0x054287b3, 0x0500b04d, 0x2560d481, 0x25a1d84c,
|
|
0x05800d38, 0x05407854, 0x050015d5, 0x25e0dabf,
|
|
0x25a1cf12, 0x0580158b, 0x05400e05, 0x05003682,
|
|
0x047a0093, 0x043e0462, 0x65d400b4, 0x658d09bd,
|
|
0x658107ce, 0x04e3107c, 0x04291b29, 0x042e155a,
|
|
0x04e71f54, 0x04d6b0d4, 0x044003ad, 0x041a0029,
|
|
0x041099fb, 0x04db1e24, 0x0419a302, 0x041abdba,
|
|
0x04d90e16, 0x04d38571, 0x04118210, 0x04d006fc,
|
|
0x0497b15c, 0x049ebcf1, 0x04580f04, 0x05278969,
|
|
0x05a496c4, 0x044801e4, 0x04ca1f44, 0x04491745,
|
|
0x040b033f, 0x04810468, 0x04dcbb07, 0x65809e38,
|
|
0x658d8fca, 0x65869ba8, 0x65c797ff, 0x65c294e0,
|
|
0x049dbadd, 0x6582ba9d, 0x6580b246, 0x6581b51a,
|
|
0x658dab93, 0x65c187d1, 0x65b19dd8, 0x65eb0b53,
|
|
0x65fc29e0, 0x65f7b797, 0x65bbd81d, 0x65a4ed97,
|
|
0x65b45aff, 0x65e07fa2, 0x04454097, 0x044d6e3c,
|
|
0x04283148, 0x04bd3013, 0x047731b0, 0x04ed33d7,
|
|
0x05606ad9, 0x056b6fd9, 0x658896ce, 0x4540b245,
|
|
0x45c3b449, 0x04243bae, 0x44d8948e, 0x449a8edb,
|
|
0x4499997f, 0x441b938c, 0x04da309c, 0x049821e6,
|
|
0x04993641, 0x04482882, 0x048a2b8b, 0x044937e3,
|
|
0x044b35f8, 0x65872d06, 0x65c63c95, 0x659834d8,
|
|
0x04c12924, 0x0e2c116a, 0x4e2710c5, 0x0e61101f,
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|
0x4e7812f6, 0x0ebb1359, 0x4eb1120f, 0x2e251083,
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0x6e341272, 0x2e7011ee, 0x6e6c116a, 0x2ea41062,
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0x6eac116a,
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|
};
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|
// END Generated code -- do not edit
|