mirror of
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202 lines
8.0 KiB
C++
202 lines
8.0 KiB
C++
/*
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* Copyright (c) 2019, Oracle and/or its affiliates. All rights reserved.
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* Copyright (c) 2019 SAP SE. All rights reserved.
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* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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*
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* This code is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 only, as
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* published by the Free Software Foundation.
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*
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* This code is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* version 2 for more details (a copy is included in the LICENSE file that
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* accompanied this code).
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*
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* You should have received a copy of the GNU General Public License version
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* 2 along with this work; if not, write to the Free Software Foundation,
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* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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*
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* Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
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* or visit www.oracle.com if you need additional information or have any
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* questions.
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*
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*/
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#include "asm/macroAssembler.inline.hpp"
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#include "code/codeCache.hpp"
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#include "compiler/disassembler.hpp"
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#include "depChecker_ppc.hpp"
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#include "gc/cms/concurrentMarkSweepGeneration.inline.hpp"
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#include "gc/cms/parOopClosures.inline.hpp"
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#include "gc/shared/collectedHeap.hpp"
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#include "gc/shared/cardTableBarrierSet.hpp"
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#include "gc/shared/genOopClosures.inline.hpp"
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#include "oops/oop.inline.hpp"
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#include "runtime/handles.inline.hpp"
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#include "runtime/stubCodeGenerator.hpp"
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#include "runtime/stubRoutines.hpp"
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// Macro to print instruction bits.
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// numbering of instruction bits on ppc64 is (highest) 0 1 ... 30 31 (lowest).
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#define print_instruction_bits(st, instruction, start_bit, end_bit) \
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{ assert((start_bit) <= (end_bit), "sanity check"); \
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for (int i=(31-(start_bit));i>=(31-(end_bit));i--) { \
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(st)->print("%d", ((instruction) >> i) & 0x1); \
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} \
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}
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// Macro to decode "bo" instruction bits.
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#define print_decoded_bo_bits(env, instruction, end_bit) \
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{ int bo_bits = (instruction >> (31 - (end_bit))) & 0x1f; \
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if ( ((bo_bits & 0x1c) == 0x4) || ((bo_bits & 0x1c) == 0xc) ) { \
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switch (bo_bits & 0x3) { \
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case (0 << 1) | (0 << 0): env->print("[no_hint]"); break; \
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case (0 << 1) | (1 << 0): env->print("[reserved]"); break; \
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case (1 << 1) | (0 << 0): env->print("[not_taken]"); break; \
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case (1 << 1) | (1 << 0): env->print("[taken]"); break; \
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default: break; \
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} \
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} else if ( ((bo_bits & 0x14) == 0x10) ) { \
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switch (bo_bits & 0x9) { \
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case (0 << 3) | (0 << 0): env->print("[no_hint]"); break; \
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case (0 << 3) | (1 << 0): env->print("[reserved]"); break; \
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case (1 << 3) | (0 << 0): env->print("[not_taken]"); break; \
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case (1 << 3) | (1 << 0): env->print("[taken]"); break; \
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default: break; \
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} \
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} \
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}
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// Macro to decode "bh" instruction bits.
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#define print_decoded_bh_bits(env, instruction, end_bit, is_bclr) \
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{ int bh_bits = (instruction >> (31 - (end_bit))) & 0x3; \
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if (is_bclr) { \
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switch (bh_bits) { \
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case (0 << 1) | (0 << 0): env->print("[subroutine_return]"); break; \
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case (0 << 1) | (1 << 0): env->print("[not_return_but_same]"); break; \
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case (1 << 1) | (0 << 0): env->print("[reserved]"); break; \
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case (1 << 1) | (1 << 0): env->print("[not_predictable]"); break; \
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default: break; \
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} \
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} else { \
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switch (bh_bits) { \
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case (0 << 1) | (0 << 0): env->print("[not_return_but_same]"); break; \
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case (0 << 1) | (1 << 0): env->print("[reserved]"); break; \
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case (1 << 1) | (0 << 0): env->print("[reserved]"); break; \
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case (1 << 1) | (1 << 0): env->print("[not_predictable]"); break; \
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default: break; \
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} \
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} \
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}
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address Disassembler::find_prev_instr(address here, int n_instr) {
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if (!os::is_readable_pointer(here)) return NULL; // obviously a bad location to decode
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// Find most distant possible starting point.
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// Narrow down because we don't want to SEGV while printing.
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address start = here - n_instr*Assembler::instr_maxlen(); // starting point can't be further away.
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while ((start < here) && !os::is_readable_range(start, here)) {
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start = align_down(start, os::min_page_size()) + os::min_page_size();
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}
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if (start >= here) {
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// Strange. Can only happen with here on page boundary.
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return NULL;
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}
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return start;
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}
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address Disassembler::decode_instruction0(address here, outputStream * st, address virtual_begin ) {
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if (is_abstract()) {
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// The disassembler library was not loaded (yet),
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// use AbstractDisassembler's decode method.
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return decode_instruction_abstract(here, st, Assembler::instr_len(here), Assembler::instr_maxlen());
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}
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// Currently, "special decoding" doesn't work when decoding error files.
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// When decoding an instruction from a hs_err file, the given
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// instruction address 'start' points to the instruction's virtual address
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// which is not equal to the address where the instruction is located.
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// Therefore, we will either crash or decode garbage.
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if (is_decode_error_file()) {
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return here;
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}
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//---< Decode some well-known "instructions" >---
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address next;
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uint32_t instruction = *(uint32_t*)here;
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// Align at next tab position.
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const uint tabspacing = 8;
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const uint pos = st->position();
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const uint aligned_pos = ((pos+tabspacing-1)/tabspacing)*tabspacing;
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st->fill_to(aligned_pos);
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if (instruction == 0x0) {
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st->print("illtrap .data 0x0");
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next = here + Assembler::instr_len(here);
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} else if (instruction == 0xbadbabe) {
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st->print(".data 0xbadbabe");
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next = here + Assembler::instr_len(here);
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} else if (Assembler::is_endgroup(instruction)) {
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st->print("endgroup");
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next = here + Assembler::instr_len(here);
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} else {
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next = here;
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}
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return next;
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}
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// print annotations (instruction control bits)
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void Disassembler::annotate(address here, outputStream* st) {
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// Currently, annotation doesn't work when decoding error files.
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// When decoding an instruction from a hs_err file, the given
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// instruction address 'start' points to the instruction's virtual address
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// which is not equal to the address where the instruction is located.
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// Therefore, we will either crash or decode garbage.
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if (is_decode_error_file()) {
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return;
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}
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uint32_t instruction = *(uint32_t*)here;
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// Align at next tab position.
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const uint tabspacing = 8;
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const uint pos = st->position();
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const uint aligned_pos = ((pos+tabspacing-1)/tabspacing)*tabspacing;
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if (MacroAssembler::is_bcxx(instruction)) {
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st->print(",bo=0b");
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print_instruction_bits(st, instruction, 6, 10);
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print_decoded_bo_bits(st, instruction, 10);
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} else if (MacroAssembler::is_bctr(instruction) ||
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MacroAssembler::is_bctrl(instruction) ||
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MacroAssembler::is_bclr(instruction)) {
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st->fill_to(aligned_pos);
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st->print("bo=0b");
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print_instruction_bits(st, instruction, 6, 10);
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print_decoded_bo_bits(st, instruction, 10);
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st->print(",bh=0b");
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print_instruction_bits(st, instruction, 19, 20);
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print_decoded_bh_bits(st, instruction, 20,
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!(MacroAssembler::is_bctr(instruction) ||
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MacroAssembler::is_bctrl(instruction)));
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} else if (MacroAssembler::is_trap_should_not_reach_here(instruction)) {
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st->fill_to(aligned_pos + tabspacing);
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st->print(";trap: should not reach here");
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} else if (MacroAssembler::is_trap_null_check(instruction)) {
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st->fill_to(aligned_pos + tabspacing);
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st->print(";trap: null check");
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} else if (MacroAssembler::is_trap_range_check(instruction)) {
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st->fill_to(aligned_pos + tabspacing);
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st->print(";trap: range check");
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} else if (MacroAssembler::is_trap_ic_miss_check(instruction)) {
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st->fill_to(aligned_pos + tabspacing);
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st->print(";trap: ic miss check");
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} else if (MacroAssembler::is_trap_zombie_not_entrant(instruction)) {
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st->fill_to(aligned_pos + tabspacing);
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st->print(";trap: zombie");
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}
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}
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