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48 lines
1.9 KiB
C++
48 lines
1.9 KiB
C++
/*
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* Copyright (c) 2002, 2023, Oracle and/or its affiliates. All rights reserved.
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* Copyright (c) 2012, 2019 SAP SE. All rights reserved.
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* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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*
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* This code is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 only, as
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* published by the Free Software Foundation.
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*
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* This code is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* version 2 for more details (a copy is included in the LICENSE file that
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* accompanied this code).
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*
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* You should have received a copy of the GNU General Public License version
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* 2 along with this work; if not, write to the Free Software Foundation,
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* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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*
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* Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
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* or visit www.oracle.com if you need additional information or have any
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* questions.
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*
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*/
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#ifndef CPU_PPC_DISASSEMBLER_PPC_HPP
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#define CPU_PPC_DISASSEMBLER_PPC_HPP
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static int pd_instruction_alignment() {
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return sizeof(int);
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}
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static const char* pd_cpu_opts() {
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return "ppc64";
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}
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// special-case instruction decoding.
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// There may be cases where the binutils disassembler doesn't do
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// the perfect job. In those cases, decode_instruction0 may kick in
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// and do it right.
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// If nothing had to be done, just return "here", otherwise return "here + instr_len(here)"
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static address decode_instruction0(address here, outputStream* st, address virtual_begin = nullptr);
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// platform-specific instruction annotations (like value of loaded constants)
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static void annotate(address pc, outputStream* st);
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#endif // CPU_PPC_DISASSEMBLER_PPC_HPP
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