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8353572: x86: AMD platforms miss the check for CLWB feature flag
Reviewed-by: vlivanov, kvn
This commit is contained in:
parent
76ff97811a
commit
3090e2187c
@ -3062,6 +3062,10 @@ uint64_t VM_Version::CpuidInfo::feature_flags() const {
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result |= CPU_TSCINV_BIT;
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if (std_cpuid1_ecx.bits.aes != 0)
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result |= CPU_AES;
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if (ext_cpuid1_ecx.bits.lzcnt != 0)
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result |= CPU_LZCNT;
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if (ext_cpuid1_ecx.bits.prefetchw != 0)
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result |= CPU_3DNOW_PREFETCH;
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if (sef_cpuid7_ebx.bits.erms != 0)
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result |= CPU_ERMS;
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if (sef_cpuid7_edx.bits.fast_short_rep_mov != 0)
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@ -3080,48 +3084,36 @@ uint64_t VM_Version::CpuidInfo::feature_flags() const {
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result |= CPU_FMA;
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if (sef_cpuid7_ebx.bits.clflushopt != 0)
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result |= CPU_FLUSHOPT;
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if (sef_cpuid7_ebx.bits.clwb != 0)
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result |= CPU_CLWB;
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if (ext_cpuid1_edx.bits.rdtscp != 0)
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result |= CPU_RDTSCP;
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if (sef_cpuid7_ecx.bits.rdpid != 0)
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result |= CPU_RDPID;
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// AMD|Hygon features.
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// AMD|Hygon additional features.
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if (is_amd_family()) {
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if ((ext_cpuid1_edx.bits.tdnow != 0) ||
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(ext_cpuid1_ecx.bits.prefetchw != 0))
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// PREFETCHW was checked above, check TDNOW here.
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if ((ext_cpuid1_edx.bits.tdnow != 0))
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result |= CPU_3DNOW_PREFETCH;
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if (ext_cpuid1_ecx.bits.lzcnt != 0)
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result |= CPU_LZCNT;
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if (ext_cpuid1_ecx.bits.sse4a != 0)
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result |= CPU_SSE4A;
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}
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// Intel features.
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// Intel additional features.
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if (is_intel()) {
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if (ext_cpuid1_ecx.bits.lzcnt != 0) {
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result |= CPU_LZCNT;
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}
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if (ext_cpuid1_ecx.bits.prefetchw != 0) {
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result |= CPU_3DNOW_PREFETCH;
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}
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if (sef_cpuid7_ebx.bits.clwb != 0) {
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result |= CPU_CLWB;
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}
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if (sef_cpuid7_edx.bits.serialize != 0)
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result |= CPU_SERIALIZE;
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if (_cpuid_info.sef_cpuid7_edx.bits.avx512_fp16 != 0)
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result |= CPU_AVX512_FP16;
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}
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// ZX features.
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// ZX additional features.
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if (is_zx()) {
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if (ext_cpuid1_ecx.bits.lzcnt != 0) {
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result |= CPU_LZCNT;
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}
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if (ext_cpuid1_ecx.bits.prefetchw != 0) {
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result |= CPU_3DNOW_PREFETCH;
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}
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// We do not know if these are supported by ZX, so we cannot trust
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// common CPUID bit for them.
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assert((result & CPU_CLWB) == 0, "Check if it is supported?");
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result &= ~CPU_CLWB;
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}
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// Protection key features.
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