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8284903: Fix typos in hotspot

Browse Source 
Reviewed-by: cjplummer, coleenp, kvn, lucy, stefank
This commit is contained in:
Magnus Ihse Bursie 2022-04-19 19:10:52 +00:00
parent 13fb1eed52
commit 4594696f54
446 changed files with 1196 additions and 1197 deletions
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12
src/hotspot/cpu/aarch64/aarch64.ad
View File

@ -28,7 +28,7 @@
//----------REGISTER DEFINITION BLOCK------------------------------------------
// This information is used by the matcher and the register allocator to
// describe individual registers and classes of registers within the target
// archtecture.
// architecture.
register %{
//----------Architecture Description Register Definitions----------------------
@ -488,7 +488,7 @@ reg_def R31_H ( NS, NS, Op_RegI, 31, r31_sp->as_VMReg()->next());
// Special Registers
// ----------------------------
// the AArch64 CSPR status flag register is not directly acessible as
// the AArch64 CSPR status flag register is not directly accessible as
// instruction operand. the FPSR status flag register is a system
// register which can be written/read using MSR/MRS but again does not
// appear as an operand (a code identifying the FSPR occurs as an
@ -1508,7 +1508,7 @@ source %{
// node sequence to a normal volatile get because of the
// introduction of some CPUOrder memory barriers to bracket the
// Load. However, but the same basic skeleton of a LoadX feeding a
// MemBarAcquire, possibly thorugh an optional DecodeN, is still
// MemBarAcquire, possibly through an optional DecodeN, is still
// present
//
// MemBarCPUOrder
@ -4117,10 +4117,10 @@ encode %{
// Region 6-7 is determined per call site.
// Note 2: If the calling convention leaves holes in the incoming argument
// area, those holes are owned by SELF. Holes in the outgoing area
// are owned by the CALLEE. Holes should not be nessecary in the
// are owned by the CALLEE. Holes should not be necessary in the
// incoming area, as the Java calling convention is completely under
// the control of the AD file. Doubles can be sorted and packed to
// avoid holes. Holes in the outgoing arguments may be nessecary for
// avoid holes. Holes in the outgoing arguments may be necessary for
// varargs C calling conventions.
// Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
// even aligned with pad0 as needed.
@ -17344,7 +17344,7 @@ instruct tlsLoadP(thread_RegP dst)
//
// // Change (inc mov) to lea
// peephole %{
// // increment preceeded by register-register move
// // increment preceded by register-register move
// peepmatch ( incI_iReg movI );
// // require that the destination register of the increment
// // match the destination register of the move

4
src/hotspot/cpu/aarch64/aarch64_neon.ad
View File

@ -5844,7 +5844,7 @@ instruct vmask_lasttrue8B(iRegINoSp dst, vecD src) %{
// bytes with 0x00/0x01 as element values.
//
// Computed by counting the leading zero bytes and
// substracting it by 7 (VLENGTH - 1).
// subtracting it by 7 (VLENGTH - 1).
__ fmovd($dst$$Register, as_FloatRegister($src$$reg));
__ clz($dst$$Register, $dst$$Register);
__ movw(rscratch1, 7);
@ -5876,7 +5876,7 @@ instruct vmask_lasttrue16B(iRegINoSp dst, vecX src) %{
__ fmovd($dst$$Register, as_FloatRegister($src$$reg));
__ movw(rscratch1, 8 - 1);
// Count the leading zero bytes and substract it by 15 (VLENGTH - 1).
// Count the leading zero bytes and subtract it by 15 (VLENGTH - 1).
__ bind(LAST_TRUE_INDEX);
__ clz($dst$$Register, $dst$$Register);
__ subw($dst$$Register, rscratch1, $dst$$Register, Assembler::LSR, 3);

4
src/hotspot/cpu/aarch64/aarch64_neon_ad.m4
View File

@ -2548,7 +2548,7 @@ instruct vmask_lasttrue8B(iRegINoSp dst, vecD src) %{
// bytes with 0x00/0x01 as element values.
//
// Computed by counting the leading zero bytes and
// substracting it by 7 (VLENGTH - 1).
// subtracting it by 7 (VLENGTH - 1).
__ fmovd($dst$$Register, as_FloatRegister($src$$reg));
__ clz($dst$$Register, $dst$$Register);
__ movw(rscratch1, 7);
@ -2580,7 +2580,7 @@ instruct vmask_lasttrue16B(iRegINoSp dst, vecX src) %{
__ fmovd($dst$$Register, as_FloatRegister($src$$reg));
__ movw(rscratch1, 8 - 1);
// Count the leading zero bytes and substract it by 15 (VLENGTH - 1).
// Count the leading zero bytes and subtract it by 15 (VLENGTH - 1).
__ bind(LAST_TRUE_INDEX);
__ clz($dst$$Register, $dst$$Register);
__ subw($dst$$Register, rscratch1, $dst$$Register, Assembler::LSR, 3);

4
src/hotspot/cpu/aarch64/abstractInterpreter_aarch64.cpp
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2003, 2020, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2003, 2022, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2014, Red Hat Inc. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
@ -86,7 +86,7 @@ int AbstractInterpreter::size_activation(int max_stack,
int overhead = frame::sender_sp_offset -
frame::interpreter_frame_initial_sp_offset;
// Our locals were accounted for by the caller (or last_frame_adjust
// on the transistion) Since the callee parameters already account
// on the transition) Since the callee parameters already account
// for the callee's params we only need to account for the extra
// locals.
int size = overhead +

4
src/hotspot/cpu/aarch64/assembler_aarch64.hpp
View File

@ -36,7 +36,7 @@
#elif defined(_MSC_VER)
// Use MSVC instrinsic: https://docs.microsoft.com/en-us/cpp/intrinsics/arm64-intrinsics?view=vs-2019#I
// Use MSVC intrinsic: https://docs.microsoft.com/en-us/cpp/intrinsics/arm64-intrinsics?view=vs-2019#I
#define NOP() __nop();
#endif
@ -593,7 +593,7 @@ class Address {
}
};
// Convience classes
// Convenience classes
class RuntimeAddress: public Address {
public:

2
src/hotspot/cpu/aarch64/c1_LIRAssembler_aarch64.cpp
View File

@ -433,7 +433,7 @@ int LIR_Assembler::emit_unwind_handler() {
__ mov(r19, r0); // Preserve the exception
}
// Preform needed unlocking
// Perform needed unlocking
MonitorExitStub* stub = NULL;
if (method()->is_synchronized()) {
monitor_address(0, FrameMap::r0_opr);

2
src/hotspot/cpu/aarch64/c1_Runtime1_aarch64.cpp
View File

@ -692,7 +692,7 @@ OopMapSet* Runtime1::generate_code_for(StubID id, StubAssembler* sasm) {
}
#endif // ASSERT
// get the instance size (size is postive so movl is fine for 64bit)
// get the instance size (size is positive so movl is fine for 64bit)
__ ldrw(obj_size, Address(klass, Klass::layout_helper_offset()));
__ eden_allocate(obj, obj_size, 0, t1, slow_path);

4
src/hotspot/cpu/aarch64/c2_MacroAssembler_aarch64.cpp
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2020, 2021, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2020, 2022, Oracle and/or its affiliates. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
@ -80,7 +80,7 @@ void C2_MacroAssembler::string_indexof(Register str2, Register str1,
// if (substr.count == 0) return 0;
// We have two strings, a source string in str2, cnt2 and a pattern string
// in str1, cnt1. Find the 1st occurence of pattern in source or return -1.
// in str1, cnt1. Find the 1st occurrence of pattern in source or return -1.
// For larger pattern and source we use a simplified Boyer Moore algorithm.
// With a small pattern and source we use linear scan.

2
src/hotspot/cpu/aarch64/gc/shenandoah/shenandoahBarrierSetAssembler_aarch64.cpp
View File

@ -186,7 +186,7 @@ void ShenandoahBarrierSetAssembler::resolve_forward_pointer(MacroAssembler* masm
__ bind(is_null);
}
// IMPORTANT: This must preserve all registers, even rscratch1 and rscratch2, except those explicitely
// IMPORTANT: This must preserve all registers, even rscratch1 and rscratch2, except those explicitly
// passed in.
void ShenandoahBarrierSetAssembler::resolve_forward_pointer_not_null(MacroAssembler* masm, Register dst, Register tmp) {
assert(ShenandoahLoadRefBarrier || ShenandoahCASBarrier, "Should be enabled");

2
src/hotspot/cpu/aarch64/gc/z/zBarrierSetAssembler_aarch64.cpp
View File

@ -237,7 +237,7 @@ void ZBarrierSetAssembler::generate_c1_load_barrier_stub(LIR_Assembler* ce,
assert_different_registers(ref, ref_addr, noreg);
// Save r0 unless it is the result or tmp register
// Set up SP to accomodate parameters and maybe r0..
// Set up SP to accommodate parameters and maybe r0..
if (ref != r0 && tmp != r0) {
__ sub(sp, sp, 32);
__ str(r0, Address(sp, 16));

6
src/hotspot/cpu/aarch64/gc/z/zGlobals_aarch64.cpp
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2017, 2021, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2017, 2022, Oracle and/or its affiliates. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
@ -154,12 +154,12 @@ static size_t probe_valid_max_address_bit() {
for (size_t i = DEFAULT_MAX_ADDRESS_BIT; i > MINIMUM_MAX_ADDRESS_BIT; --i) {
const uintptr_t base_addr = ((uintptr_t) 1U) << i;
if (msync((void*)base_addr, page_size, MS_ASYNC) == 0) {
// msync suceeded, the address is valid, and maybe even already mapped.
// msync succeeded, the address is valid, and maybe even already mapped.
max_address_bit = i;
break;
}
if (errno != ENOMEM) {
// Some error occured. This should never happen, but msync
// Some error occurred. This should never happen, but msync
// has some undefined behavior, hence ignore this bit.
#ifdef ASSERT
fatal("Received '%s' while probing the address space for the highest valid bit", os::errno_name(errno));

2
src/hotspot/cpu/aarch64/globals_aarch64.hpp
View File

@ -91,7 +91,7 @@ define_pd_global(intx, InlineSmallCode, 1000);
product(bool, UseSIMDForArrayEquals, true, \
"Use SIMD instructions in generated array equals code") \
product(bool, UseSimpleArrayEquals, false, \
"Use simpliest and shortest implementation for array equals") \
"Use simplest and shortest implementation for array equals") \
product(bool, UseSIMDForBigIntegerShiftIntrinsics, true, \
"Use SIMD instructions for left/right shift of BigInteger") \
product(bool, AvoidUnalignedAccesses, false, \

2
src/hotspot/cpu/aarch64/immediate_aarch64.cpp
View File

@ -257,7 +257,7 @@ int expandLogicalImmediate(uint32_t immN, uint32_t immr,
// constructor to initialise the lookup tables
static void initLITables();
// Use an empty struct with a construtor as MSVC doesn't support `__attribute__ ((constructor))`
// Use an empty struct with a constructor as MSVC doesn't support `__attribute__ ((constructor))`
// See https://stackoverflow.com/questions/1113409/attribute-constructor-equivalent-in-vc
static struct initLITables_t { initLITables_t(void) { initLITables(); } } _initLITables;
static void initLITables()

6
src/hotspot/cpu/aarch64/interp_masm_aarch64.cpp
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2003, 2021, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2003, 2022, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2014, 2020, Red Hat Inc. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
@ -523,7 +523,7 @@ void InterpreterMacroAssembler::dispatch_via(TosState state, address* table) {
//
// Apply stack watermark barrier.
// Unlock the receiver if this is a synchronized method.
// Unlock any Java monitors from syncronized blocks.
// Unlock any Java monitors from synchronized blocks.
// Remove the activation from the stack.
//
// If there are locked Java monitors
@ -1748,7 +1748,7 @@ void InterpreterMacroAssembler::profile_return_type(Register mdp, Register ret,
// If we don't profile all invoke bytecodes we must make sure
// it's a bytecode we indeed profile. We can't go back to the
// begining of the ProfileData we intend to update to check its
// beginning of the ProfileData we intend to update to check its
// type because we're right after it and we don't known its
// length
Label do_profile;

4
src/hotspot/cpu/aarch64/interp_masm_aarch64.hpp
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2003, 2019, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2003, 2022, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2014, 2015, Red Hat Inc. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
@ -30,7 +30,7 @@
#include "interpreter/invocationCounter.hpp"
#include "runtime/frame.hpp"
// This file specializes the assember with interpreter-specific macros
// This file specializes the assembler with interpreter-specific macros
typedef ByteSize (*OffsetFunction)(uint);

26
src/hotspot/cpu/aarch64/macroAssembler_aarch64.cpp
View File

@ -196,7 +196,7 @@ int MacroAssembler::patch_oop(address insn_addr, address o) {
}
int MacroAssembler::patch_narrow_klass(address insn_addr, narrowKlass n) {
// Metatdata pointers are either narrow (32 bits) or wide (48 bits).
// Metadata pointers are either narrow (32 bits) or wide (48 bits).
// We encode narrow ones by setting the upper 16 bits in the first
// instruction.
NativeInstruction *insn = nativeInstruction_at(insn_addr);
@ -993,7 +993,7 @@ void MacroAssembler::check_klass_subtype_fast_path(Register sub_klass,
// These two are taken from x86, but they look generally useful
// scans count pointer sized words at [addr] for occurence of value,
// scans count pointer sized words at [addr] for occurrence of value,
// generic
void MacroAssembler::repne_scan(Register addr, Register value, Register count,
Register scratch) {
@ -1008,7 +1008,7 @@ void MacroAssembler::repne_scan(Register addr, Register value, Register count,
bind(Lexit);
}
// scans count 4 byte words at [addr] for occurence of value,
// scans count 4 byte words at [addr] for occurrence of value,
// generic
void MacroAssembler::repne_scanw(Register addr, Register value, Register count,
Register scratch) {
@ -1581,7 +1581,7 @@ void MacroAssembler::atomic_incw(Register counter_addr, Register tmp, Register t
// flush and load exclusive from the memory location
ldxrw(tmp, counter_addr);
addw(tmp, tmp, 1);
// if we store+flush with no intervening write tmp wil be zero
// if we store+flush with no intervening write tmp will be zero
stxrw(tmp2, tmp, counter_addr);
cbnzw(tmp2, retry_load);
}
@ -1889,7 +1889,7 @@ int MacroAssembler::push(unsigned int bitset, Register stack) {
bitset >>= 1;
}
regs[count++] = zr->encoding_nocheck();
count &= ~1; // Only push an even nuber of regs
count &= ~1; // Only push an even number of regs
if (count) {
stp(as_Register(regs[0]), as_Register(regs[1]),
@ -2210,7 +2210,7 @@ void MacroAssembler::wrap_add_sub_imm_insn(Register Rd, Register Rn, unsigned im
}
}
// Seperate vsn which sets the flags. Optimisations are more restricted
// Separate vsn which sets the flags. Optimisations are more restricted
// because we must set the flags correctly.
void MacroAssembler::wrap_adds_subs_imm_insn(Register Rd, Register Rn, unsigned imm,
add_sub_imm_insn insn1,
@ -2305,7 +2305,7 @@ void MacroAssembler::cmpxchgptr(Register oldv, Register newv, Register addr, Reg
ldaxr(tmp, addr);
cmp(tmp, oldv);
br(Assembler::NE, nope);
// if we store+flush with no intervening write tmp wil be zero
// if we store+flush with no intervening write tmp will be zero
stlxr(tmp, newv, addr);
cbzw(tmp, succeed);
// retry so we only ever return after a load fails to compare
@ -2348,7 +2348,7 @@ void MacroAssembler::cmpxchgw(Register oldv, Register newv, Register addr, Regis
ldaxrw(tmp, addr);
cmp(tmp, oldv);
br(Assembler::NE, nope);
// if we store+flush with no intervening write tmp wil be zero
// if we store+flush with no intervening write tmp will be zero
stlxrw(tmp, newv, addr);
cbzw(tmp, succeed);
// retry so we only ever return after a load fails to compare
@ -3024,7 +3024,7 @@ void MacroAssembler::multiply_128_x_128_loop(Register y, Register z,
}
/**
* Code for BigInteger::multiplyToLen() instrinsic.
* Code for BigInteger::multiplyToLen() intrinsic.
*
* r0: x
* r1: xlen
@ -3159,7 +3159,7 @@ void MacroAssembler::multiply_to_len(Register x, Register xlen, Register y, Regi
bind(L_done);
}
// Code for BigInteger::mulAdd instrinsic
// Code for BigInteger::mulAdd intrinsic
// out = r0
// in = r1
// offset = r2 (already out.length-offset)
@ -4835,7 +4835,7 @@ void MacroAssembler::zero_words(Register base, uint64_t cnt)
// Zero blocks of memory by using DC ZVA.
//
// Aligns the base address first sufficently for DC ZVA, then uses
// Aligns the base address first sufficiently for DC ZVA, then uses
// DC ZVA repeatedly for every full block. cnt is the size to be
// zeroed in HeapWords. Returns the count of words left to be zeroed
// in cnt.
@ -5332,7 +5332,7 @@ void MacroAssembler::protect_return_address() {
}
}
// Sign the return value in the given register. Use before updating the LR in the exisiting stack
// Sign the return value in the given register. Use before updating the LR in the existing stack
// frame for the current function.
// Uses the FP from the start of the function as the modifier - which is stored at the address of
// the current FP.
@ -5355,7 +5355,7 @@ void MacroAssembler::authenticate_return_address(Register return_reg) {
}
}
// Authenticate the return value in the given register. Use before updating the LR in the exisiting
// Authenticate the return value in the given register. Use before updating the LR in the existing
// stack frame for the current function.
// Uses the FP from the start of the function as the modifier - which is stored at the address of
// the current FP.

18
src/hotspot/cpu/aarch64/macroAssembler_aarch64.hpp
View File

@ -476,7 +476,7 @@ public:
// Push and pop everything that might be clobbered by a native
// runtime call except rscratch1 and rscratch2. (They are always
// scratch, so we don't have to protect them.) Only save the lower
// 64 bits of each vector register. Additonal registers can be excluded
// 64 bits of each vector register. Additional registers can be excluded
// in a passed RegSet.
void push_call_clobbered_registers_except(RegSet exclude);
void pop_call_clobbered_registers_except(RegSet exclude);
@ -657,7 +657,7 @@ public:
// incrementl/decrementl
// for aarch64 the proper convention would be to use
// increment/decrement for 64 bit operatons and
// increment/decrement for 64 bit operations and
// incrementw/decrementw for 32 bit operations. so when porting
// x86_64 code we can leave calls to increment/decrement as is,
// replace incrementq/decrementq with increment/decrement and
@ -1011,12 +1011,12 @@ public:
// Various forms of CAS
void cmpxchg_obj_header(Register oldv, Register newv, Register obj, Register tmp,
Label &suceed, Label *fail);
Label &succeed, Label *fail);
void cmpxchgptr(Register oldv, Register newv, Register addr, Register tmp,
Label &suceed, Label *fail);
Label &succeed, Label *fail);
void cmpxchgw(Register oldv, Register newv, Register addr, Register tmp,
Label &suceed, Label *fail);
Label &succeed, Label *fail);
void atomic_add(Register prev, RegisterOrConstant incr, Register addr);
void atomic_addw(Register prev, RegisterOrConstant incr, Register addr);
@ -1103,11 +1103,11 @@ public:
void movoop(Register dst, jobject obj, bool immediate = false);
// CRC32 code for java.util.zip.CRC32::updateBytes() instrinsic.
// CRC32 code for java.util.zip.CRC32::updateBytes() intrinsic.
void kernel_crc32(Register crc, Register buf, Register len,
Register table0, Register table1, Register table2, Register table3,
Register tmp, Register tmp2, Register tmp3);
// CRC32 code for java.util.zip.CRC32C::updateBytes() instrinsic.
// CRC32 code for java.util.zip.CRC32C::updateBytes() intrinsic.
void kernel_crc32c(Register crc, Register buf, Register len,
Register table0, Register table1, Register table2, Register table3,
Register tmp, Register tmp2, Register tmp3);
@ -1129,7 +1129,7 @@ public:
void wrap_add_sub_imm_insn(Register Rd, Register Rn, unsigned imm,
add_sub_imm_insn insn1,
add_sub_reg_insn insn2);
// Seperate vsn which sets the flags
// Separate vsn which sets the flags
void wrap_adds_subs_imm_insn(Register Rd, Register Rn, unsigned imm,
add_sub_imm_insn insn1,
add_sub_reg_insn insn2);
@ -1233,7 +1233,7 @@ public:
address read_polling_page(Register r, relocInfo::relocType rtype);
void get_polling_page(Register dest, relocInfo::relocType rtype);
// CRC32 code for java.util.zip.CRC32::updateBytes() instrinsic.
// CRC32 code for java.util.zip.CRC32::updateBytes() intrinsic.
void update_byte_crc32(Register crc, Register val, Register table);
void update_word_crc32(Register crc, Register v, Register tmp,
Register table0, Register table1, Register table2, Register table3,

8
src/hotspot/cpu/aarch64/macroAssembler_aarch64_aes.cpp
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2003, 2021, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2003, 2022, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2014, 2021, Red Hat Inc. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
@ -359,7 +359,7 @@ public:
FloatRegister b,
/* non-offsetted (shared) registers */
FloatRegister a, FloatRegister a1_xor_a0, FloatRegister p, FloatRegister vzr,
/* offseted (temp) registers */
/* offsetted (temp) registers */
FloatRegister tmp1, FloatRegister tmp2, FloatRegister tmp3)
: KernelGenerator(as, unrolls),
_result_lo(result_lo), _result_hi(result_hi), _b(b),
@ -436,7 +436,7 @@ public:
FloatRegister result, FloatRegister lo, FloatRegister hi,
/* non-offsetted (shared) registers */
FloatRegister p, FloatRegister vzr, FloatRegister data,
/* offseted (temp) registers */
/* offsetted (temp) registers */
FloatRegister t1)
: KernelGenerator(as, unrolls),
_result(result), _lo(lo), _hi(hi),
@ -521,7 +521,7 @@ void MacroAssembler::ghash_processBlocks_wide(address field_polynomial, Register
// everything big-endian or reverse the bits in each byte and do
// it little-endian. On AArch64 it's more idiomatic to reverse
// the bits in each byte (we have an instruction, RBIT, to do
// that) and keep the data in little-endian bit order throught the
// that) and keep the data in little-endian bit order through the
// calculation, bit-reversing the inputs and outputs.
assert(unrolls * register_stride < 32, "out of registers");

14
src/hotspot/cpu/aarch64/macroAssembler_aarch64_trig.cpp
View File

@ -1,4 +1,4 @@
/* Copyright (c) 2018, 2020, Oracle and/or its affiliates. All rights reserved.
/* Copyright (c) 2018, 2022, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2018, Cavium. All rights reserved. (By BELLSOFT)
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
@ -431,7 +431,7 @@ void MacroAssembler::generate__ieee754_rem_pio2(address npio2_hw,
// * z = (z-x[i])*2**24
// *
// *
// * y[] ouput result in an array of double precision numbers.
// * y[] output result in an array of double precision numbers.
// * The dimension of y[] is:
// * 24-bit precision 1
// * 53-bit precision 2
@ -450,7 +450,7 @@ void MacroAssembler::generate__ieee754_rem_pio2(address npio2_hw,
// *
// * nx dimension of x[]
// *
// * prec an interger indicating the precision:
// * prec an integer indicating the precision:
// * 0 24 bits (single)
// * 1 53 bits (double)
// * 2 64 bits (extended)
@ -667,7 +667,7 @@ void MacroAssembler::generate__ieee754_rem_pio2(address npio2_hw,
// Changes between fdlibm and intrinsic:
// 1. One loop is unrolled and vectorized (see comments in code)
// 2. One loop is split into 2 loops (see comments in code)
// 3. Non-double code is removed(last switch). Sevaral variables became
// 3. Non-double code is removed(last switch). Several variables became
// constants because of that (see comments in code)
// 4. Use of jx, which is nx-1 instead of nx
// Assumptions:
@ -999,7 +999,7 @@ void MacroAssembler::generate__kernel_rem_pio2(address two_over_pi, address pio2
block_comment("else block of if(z==0.0) {"); {
bind(RECOMP_CHECK_DONE_NOT_ZERO);
fmuld(v18, v18, v22);
fcmpd(v18, v24); // v24 is stil two24A
fcmpd(v18, v24); // v24 is still two24A
br(LT, Z_IS_LESS_THAN_TWO24B);
fmuld(v1, v18, v17); // twon24*z
frintzd(v1, v1); // v1 = (double)(int)(v1)
@ -1180,7 +1180,7 @@ void MacroAssembler::generate__kernel_rem_pio2(address two_over_pi, address pio2
// 3. C code parameter "int iy" was modified to "bool iyIsOne", because
// iy is always 0 or 1. Also, iyIsOne branch was moved into
// generation phase instead of taking it during code execution
// Input ans output:
// Input and output:
// 1. Input for generated function: X argument = x
// 2. Input for generator: x = register to read argument from, iyIsOne
// = flag to use low argument low part or not, dsin_coef = coefficients
@ -1405,7 +1405,7 @@ void MacroAssembler::generate_kernel_cos(FloatRegister x, address dcos_coef) {
// Changes between fdlibm and intrinsic:
// 1. Moved ix < 2**27 from kernel_sin/kernel_cos into dsin/dcos
// 2. Final switch use equivalent bit checks(tbz/tbnz)
// Input ans output:
// Input and output:
// 1. Input for generated function: X = r0
// 2. Input for generator: isCos = generate sin or cos, npio2_hw = address
// of npio2_hw table, two_over_pi = address of two_over_pi table,

4
src/hotspot/cpu/aarch64/matcher_aarch64.hpp
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2021, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2021, 2022, Oracle and/or its affiliates. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
@ -154,7 +154,7 @@
return UseSVE > 0;
}
// true means we have fast l2f convers
// true means we have fast l2f conversion
// false means that conversion is done by runtime call
static constexpr bool convL2FSupported(void) {
return true;

4
src/hotspot/cpu/aarch64/registerMap_aarch64.hpp
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 1998, 2021, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 1998, 2022, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2014, Red Hat Inc. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
@ -26,7 +26,7 @@
#ifndef CPU_AARCH64_REGISTERMAP_AARCH64_HPP
#define CPU_AARCH64_REGISTERMAP_AARCH64_HPP
// machine-dependent implemention for register maps
// machine-dependent implementation for register maps
friend class frame;
private:

6
src/hotspot/cpu/aarch64/sharedRuntime_aarch64.cpp
View File

@ -762,7 +762,7 @@ AdapterHandlerEntry* SharedRuntime::generate_i2c2i_adapters(MacroAssembler *masm
// require some stack space. We grow the current (compiled) stack, then repack
// the args. We finally end in a jump to the generic interpreter entry point.
// On exit from the interpreter, the interpreter will restore our SP (lest the
// compiled code, which relys solely on SP and not FP, get sick).
// compiled code, which relies solely on SP and not FP, get sick).
{
__ block_comment("c2i_unverified_entry {");
@ -2628,7 +2628,7 @@ SafepointBlob* SharedRuntime::generate_handler_blob(address call_ptr, int poll_t
bool cause_return = (poll_type == POLL_AT_RETURN);
RegisterSaver reg_save(poll_type == POLL_AT_VECTOR_LOOP /* save_vectors */);
// When the signal occured, the LR was either signed and stored on the stack (in which
// When the signal occurred, the LR was either signed and stored on the stack (in which
// case it will be restored from the stack before being used) or unsigned and not stored
// on the stack. Stipping ensures we get the right value.
__ strip_return_address();
@ -2638,7 +2638,7 @@ SafepointBlob* SharedRuntime::generate_handler_blob(address call_ptr, int poll_t
// The following is basically a call_VM. However, we need the precise
// address of the call in order to generate an oopmap. Hence, we do all the
// work outselves.
// work ourselves.
Label retaddr;
__ set_last_Java_frame(sp, noreg, retaddr, rscratch1);

22
src/hotspot/cpu/aarch64/stubGenerator_aarch64.cpp
View File

@ -453,7 +453,7 @@ class StubGenerator: public StubCodeGenerator {
// NOTE: At entry of this stub, exception-pc must be in LR !!
// NOTE: this is always used as a jump target within generated code
// so it just needs to be generated code wiht no x86 prolog
// so it just needs to be generated code with no x86 prolog
address generate_forward_exception() {
StubCodeMark mark(this, "StubRoutines", "forward exception");
@ -859,7 +859,7 @@ class StubGenerator: public StubCodeGenerator {
// or -1.
//
// when forward copying we need to store 1 word, 3 pairs and
// then 1 word at offsets {0, 1, 3, 5, 7}. Rather thna use a
// then 1 word at offsets {0, 1, 3, 5, 7}. Rather than use a
// zero offset We adjust the destination by -1 which means we
// have to use offsets { 1, 2, 4, 6, 8} * unit for the stores.
//
@ -985,13 +985,13 @@ class StubGenerator: public StubCodeGenerator {
}
// now we need to copy any remaining part block which may
// include a 4 word block subblock and/or a 2 word subblock.
// bits 2 and 1 in the count are the tell-tale for whetehr we
// bits 2 and 1 in the count are the tell-tale for whether we
// have each such subblock
{
Label L1, L2;
__ tbz(count, exact_log2(4), L1);
// this is the same as above but copying only 4 longs hence
// with ony one intervening stp between the str instructions
// with only one intervening stp between the str instructions
// but note that the offsets and registers still follow the
// same pattern
__ ldp(t0, t1, Address(s, 2 * unit));
@ -3994,7 +3994,7 @@ class StubGenerator: public StubCodeGenerator {
* c_rarg1 - byte* buf
* c_rarg2 - int length
*
* Ouput:
* Output:
* rax - int crc result
*/
address generate_updateBytesCRC32() {
@ -4035,7 +4035,7 @@ class StubGenerator: public StubCodeGenerator {
* c_rarg2 - int length
* c_rarg3 - int* table
*
* Ouput:
* Output:
* r0 - int crc result
*/
address generate_updateBytesCRC32C() {
@ -4296,7 +4296,7 @@ class StubGenerator: public StubCodeGenerator {
* c_rarg0 - x address
* c_rarg1 - x length
* c_rarg2 - y address
* c_rarg3 - y lenth
* c_rarg3 - y length
* c_rarg4 - z address
* c_rarg5 - z length
*/
@ -5695,7 +5695,7 @@ class StubGenerator: public StubCodeGenerator {
// everything big-endian or reverse the bits in each byte and do
// it little-endian. On AArch64 it's more idiomatic to reverse
// the bits in each byte (we have an instruction, RBIT, to do
// that) and keep the data in little-endian bit order throught the
// that) and keep the data in little-endian bit order through the
// calculation, bit-reversing the inputs and outputs.
StubCodeMark mark(this, "StubRoutines", "ghash_processBlocks");
@ -5883,7 +5883,7 @@ class StubGenerator: public StubCodeGenerator {
Register send = c_rarg2; // source end offset
Register dst = c_rarg3; // dest array
Register doff = c_rarg4; // position for writing to dest array
Register isURL = c_rarg5; // Base64 or URL chracter set
Register isURL = c_rarg5; // Base64 or URL character set
// c_rarg6 and c_rarg7 are free to use as temps
Register codec = c_rarg6;
@ -5969,7 +5969,7 @@ class StubGenerator: public StubCodeGenerator {
__ ld4(in0, in1, in2, in3, arrangement, __ post(src, 4 * size));
// we need unsigned saturating substract, to make sure all input values
// we need unsigned saturating subtract, to make sure all input values
// in range [0, 63] will have 0U value in the higher half lookup
__ uqsubv(decH0, __ T16B, in0, v27);
__ uqsubv(decH1, __ T16B, in1, v27);
@ -6073,7 +6073,7 @@ class StubGenerator: public StubCodeGenerator {
// titled "Base64 decoding".
// Non-SIMD lookup tables are mostly dumped from fromBase64 array used in java.util.Base64,
// except the trailing character '=' is also treated illegal value in this instrinsic. That
// except the trailing character '=' is also treated illegal value in this intrinsic. That
// is java.util.Base64.fromBase64['='] = -2, while fromBase(URL)64ForNoSIMD['='] = 255 here.
static const uint8_t fromBase64ForNoSIMD[256] = {
255u, 255u, 255u, 255u, 255u, 255u, 255u, 255u, 255u, 255u, 255u, 255u, 255u, 255u, 255u, 255u,

4
src/hotspot/cpu/aarch64/stubRoutines_aarch64.cpp
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2003, 2020, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2003, 2022, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2014, Red Hat Inc. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
@ -300,7 +300,7 @@ ATTRIBUTE_ALIGNED(64) jubyte StubRoutines::aarch64::_adler_table[] = {
ATTRIBUTE_ALIGNED(64) juint StubRoutines::aarch64::_npio2_hw[] = {
// first, various coefficient values: 0.5, invpio2, pio2_1, pio2_1t, pio2_2,
// pio2_2t, pio2_3, pio2_3t
// This is a small optimization wich keeping double[8] values in int[] table
// This is a small optimization which keeping double[8] values in int[] table
// to have less address calculation instructions
//
// invpio2: 53 bits of 2/pi (enough for cases when trigonometric argument is small)

8
src/hotspot/cpu/aarch64/templateTable_aarch64.cpp
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2003, 2021, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2003, 2022, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2014, Red Hat Inc. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
@ -137,7 +137,7 @@ static Assembler::Condition j_not(TemplateTable::Condition cc) {
}
// Miscelaneous helper routines
// Miscellaneous helper routines
// Store an oop (or NULL) at the Address described by obj.
// If val == noreg this means store a NULL
static void do_oop_store(InterpreterMacroAssembler* _masm,
@ -2230,7 +2230,7 @@ void TemplateTable::_return(TosState state)
//
// According to the new Java Memory Model (JMM):
// (1) All volatiles are serialized wrt to each other. ALSO reads &
// writes act as aquire & release, so:
// writes act as acquire & release, so:
// (2) A read cannot let unrelated NON-volatile memory refs that
// happen after the read float up to before the read. It's OK for
// non-volatile memory refs that happen before the volatile read to
@ -3854,7 +3854,7 @@ void TemplateTable::monitorenter()
// Increment bcp to point to the next bytecode, so exception
// handling for async. exceptions work correctly.
// The object has already been poped from the stack, so the
// The object has already been popped from the stack, so the
// expression stack looks correct.
__ increment(rbcp);

4
src/hotspot/cpu/arm/abstractInterpreter_arm.cpp
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2008, 2017, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2008, 2022, Oracle and/or its affiliates. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
@ -86,7 +86,7 @@ int AbstractInterpreter::size_activation(int max_stack,
// fixed size of an interpreter frame:
int overhead = frame::sender_sp_offset - frame::interpreter_frame_initial_sp_offset;
// Our locals were accounted for by the caller (or last_frame_adjust on the transistion)
// Our locals were accounted for by the caller (or last_frame_adjust on the transition)
// Since the callee parameters already account for the callee's params we only need to account for
// the extra locals.

12
src/hotspot/cpu/arm/arm.ad
View File

@ -1569,10 +1569,10 @@ encode %{
// Region 6-7 is determined per call site.
// Note 2: If the calling convention leaves holes in the incoming argument
// area, those holes are owned by SELF. Holes in the outgoing area
// are owned by the CALLEE. Holes should not be nessecary in the
// are owned by the CALLEE. Holes should not be necessary in the
// incoming area, as the Java calling convention is completely under
// the control of the AD file. Doubles can be sorted and packed to
// avoid holes. Holes in the outgoing arguments may be nessecary for
// avoid holes. Holes in the outgoing arguments may be necessary for
// varargs C calling conventions.
// Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
// even aligned with pad0 as needed.
@ -2776,7 +2776,7 @@ pipe_class ialu_reg_reg_2_dep(iRegL dst, iRegL src1, iRegL src2, flagsReg cr) %{
IALU : R(2);
%}
// Integer ALU reg-imm operaion
// Integer ALU reg-imm operation
pipe_class ialu_reg_imm(iRegI dst, iRegI src1) %{
single_instruction;
dst : E(write);
@ -9063,7 +9063,7 @@ instruct CallLeafDirect(method meth) %{
effect(USE meth);
ins_cost(CALL_COST);
format %{ "CALL,runtime leaf" %}
// TODO: ned save_last_PC here?
// TODO: need save_last_PC here?
ins_encode( Java_To_Runtime( meth ),
call_epilog );
ins_pipe(simple_call);
@ -9075,7 +9075,7 @@ instruct CallLeafNoFPDirect(method meth) %{
effect(USE meth);
ins_cost(CALL_COST);
format %{ "CALL,runtime leaf nofp" %}
// TODO: ned save_last_PC here?
// TODO: need save_last_PC here?
ins_encode( Java_To_Runtime( meth ),
call_epilog );
ins_pipe(simple_call);
@ -11798,7 +11798,7 @@ instruct vxorX(vecX dst, vecX src1, vecX src2) %{
//
// // Change (inc mov) to lea
// peephole %{
// // increment preceeded by register-register move
// // increment preceded by register-register move
// peepmatch ( incI_eReg movI );
// // require that the destination register of the increment
// // match the destination register of the move

4
src/hotspot/cpu/arm/arm_32.ad
View File

@ -1,5 +1,5 @@
//
// Copyright (c) 2008, 2013, Oracle and/or its affiliates. All rights reserved.
// Copyright (c) 2008, 2022, Oracle and/or its affiliates. All rights reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
//
// This code is free software; you can redistribute it and/or modify it
@ -26,7 +26,7 @@
//----------REGISTER DEFINITION BLOCK------------------------------------------
// This information is used by the matcher and the register allocator to
// describe individual registers and classes of registers within the target
// archtecture.
// architecture.
register %{
//----------Architecture Description Register Definitions----------------------
// General Registers

4
src/hotspot/cpu/arm/c1_LIRAssembler_arm.cpp
View File

@ -242,7 +242,7 @@ int LIR_Assembler::emit_unwind_handler() {
__ bind(_unwind_handler_entry);
__ verify_not_null_oop(Rexception_obj);
// Preform needed unlocking
// Perform needed unlocking
MonitorExitStub* stub = NULL;
if (method()->is_synchronized()) {
monitor_address(0, FrameMap::R0_opr);
@ -641,7 +641,7 @@ void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
case T_ARRAY:
case T_ADDRESS:
case T_METADATA: __ ldr(dest->as_register(), addr); break;
case T_FLOAT: // used in floatToRawIntBits intrinsic implemenation
case T_FLOAT: // used in floatToRawIntBits intrinsic implementation
case T_INT: __ ldr_u32(dest->as_register(), addr); break;
default:
ShouldNotReachHere();

6
src/hotspot/cpu/arm/c1_MacroAssembler_arm.cpp
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2008, 2021, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2008, 2022, Oracle and/or its affiliates. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
@ -189,7 +189,7 @@ int C1_MacroAssembler::lock_object(Register hdr, Register obj, Register disp_hdr
const Register tmp2 = Rtemp; // Rtemp should be free at c1 LIR level
assert_different_registers(hdr, obj, disp_hdr, tmp2);
assert(BasicObjectLock::lock_offset_in_bytes() == 0, "ajust this code");
assert(BasicObjectLock::lock_offset_in_bytes() == 0, "adjust this code");
const int obj_offset = BasicObjectLock::obj_offset_in_bytes();
const int mark_offset = BasicLock::displaced_header_offset_in_bytes();
@ -247,7 +247,7 @@ void C1_MacroAssembler::unlock_object(Register hdr, Register obj, Register disp_
assert_different_registers(hdr, obj, disp_hdr, Rtemp);
Register tmp2 = Rtemp;
assert(BasicObjectLock::lock_offset_in_bytes() == 0, "ajust this code");
assert(BasicObjectLock::lock_offset_in_bytes() == 0, "adjust this code");
const int obj_offset = BasicObjectLock::obj_offset_in_bytes();
const int mark_offset = BasicLock::displaced_header_offset_in_bytes();

4
src/hotspot/cpu/arm/c1_Runtime1_arm.cpp
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2008, 2021, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2008, 2022, Oracle and/or its affiliates. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
@ -336,7 +336,7 @@ OopMapSet* Runtime1::generate_handle_exception(StubID id, StubAssembler* sasm) {
// Note: the restore live registers includes the jump to LR (patched to R0)
break;
case handle_exception_from_callee_id:
restore_live_registers_without_return(sasm); // must not jump immediatly to handler
restore_live_registers_without_return(sasm); // must not jump immediately to handler
restore_sp_for_method_handle(sasm);
__ ret();
break;

4
src/hotspot/cpu/arm/c2_MacroAssembler_arm.cpp
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2021, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2021, 2022, Oracle and/or its affiliates. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
@ -57,7 +57,7 @@ void C2_MacroAssembler::char_arrays_equals(Register ary1, Register ary2,
mov(result, 1, eq);
b(Ldone, eq);
// word by word compare, dont't need alignment check
// word by word compare, don't need alignment check
bind(Lvector);
// Shift ary1 and ary2 to the end of the arrays, negate limit

4
src/hotspot/cpu/arm/compiledIC_arm.cpp
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 1997, 2021, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 1997, 2022, Oracle and/or its affiliates. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
@ -96,7 +96,7 @@ int CompiledStaticCall::to_trampoline_stub_size() {
return 0;
}
// size of C2 call stub, compiled java to interpretor
// size of C2 call stub, compiled java to interpreter
int CompiledStaticCall::to_interp_stub_size() {
return 8 * NativeInstruction::instruction_size;
}

4
src/hotspot/cpu/arm/interp_masm_arm.cpp
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2008, 2021, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2008, 2022, Oracle and/or its affiliates. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
@ -682,7 +682,7 @@ void InterpreterMacroAssembler::narrow(Register result) {
// remove activation
//
// Unlock the receiver if this is a synchronized method.
// Unlock any Java monitors from syncronized blocks.
// Unlock any Java monitors from synchronized blocks.
// Remove the activation from the stack.
//
// If there are locked Java monitors

4
src/hotspot/cpu/arm/interp_masm_arm.hpp
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2008, 2021, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2008, 2022, Oracle and/or its affiliates. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
@ -31,7 +31,7 @@
#include "runtime/frame.hpp"
#include "prims/jvmtiExport.hpp"
// This file specializes the assember with interpreter-specific macros
// This file specializes the assembler with interpreter-specific macros
class InterpreterMacroAssembler: public MacroAssembler {

6
src/hotspot/cpu/arm/macroAssembler_arm.cpp
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2008, 2021, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2008, 2022, Oracle and/or its affiliates. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
@ -1144,7 +1144,7 @@ FixedSizeCodeBlock::~FixedSizeCodeBlock() {
// Serializes memory. Potentially blows flags and reg.
// tmp is a scratch for v6 co-processor write op (could be noreg for other architecure versions)
// tmp is a scratch for v6 co-processor write op (could be noreg for other architecture versions)
// preserve_flags takes a longer path in LoadStore case (dmb rather then control dependency) to preserve status flags. Optional.
// load_tgt is an ordered load target in a LoadStore case only, to create dependency between the load operation and conditional branch. Optional.
void MacroAssembler::membar(Membar_mask_bits order_constraint,
@ -1254,7 +1254,7 @@ void MacroAssembler::cas_for_lock_release(Register oldval, Register newval,
#ifndef PRODUCT
// Preserves flags and all registers.
// On SMP the updated value might not be visible to external observers without a sychronization barrier
// On SMP the updated value might not be visible to external observers without a synchronization barrier
void MacroAssembler::cond_atomic_inc32(AsmCondition cond, int* counter_addr) {
if (counter_addr != NULL) {
InlinedAddress counter_addr_literal((address)counter_addr);

4
src/hotspot/cpu/arm/macroAssembler_arm.hpp
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2008, 2021, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2008, 2022, Oracle and/or its affiliates. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
@ -998,7 +998,7 @@ public:
#ifndef PRODUCT
// Preserves flags and all registers.
// On SMP the updated value might not be visible to external observers without a sychronization barrier
// On SMP the updated value might not be visible to external observers without a synchronization barrier
void cond_atomic_inc32(AsmCondition cond, int* counter_addr);
#endif // !PRODUCT

4
src/hotspot/cpu/arm/matcher_arm.hpp
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2021, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2021, 2022, Oracle and/or its affiliates. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
@ -146,7 +146,7 @@
return false;
}
// true means we have fast l2f convers
// true means we have fast l2f conversion
// false means that conversion is done by runtime call
static constexpr bool convL2FSupported(void) {
return false;

4
src/hotspot/cpu/arm/registerMap_arm.hpp
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2008, 2021, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2008, 2022, Oracle and/or its affiliates. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
@ -25,7 +25,7 @@
#ifndef CPU_ARM_REGISTERMAP_ARM_HPP
#define CPU_ARM_REGISTERMAP_ARM_HPP
// machine-dependent implemention for register maps
// machine-dependent implementation for register maps
friend class frame;
private:

6
src/hotspot/cpu/arm/sharedRuntime_arm.cpp
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2008, 2021, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2008, 2022, Oracle and/or its affiliates. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
@ -102,11 +102,11 @@ public:
};
// all regs but Rthread (R10), FP (R7 or R11), SP and PC
// (altFP_7_11 is the one amoung R7 and R11 which is not FP)
// (altFP_7_11 is the one among R7 and R11 which is not FP)
#define SAVED_BASE_REGS (RegisterSet(R0, R6) | RegisterSet(R8, R9) | RegisterSet(R12) | R14 | altFP_7_11)
// When LR may be live in the nmethod from which we are comming
// When LR may be live in the nmethod from which we are coming
// then lr_saved is true, the return address is saved before the
// call to save_live_register by the caller and LR contains the
// live value.

6
src/hotspot/cpu/arm/stubGenerator_arm.cpp
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2008, 2021, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2008, 2022, Oracle and/or its affiliates. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
@ -138,7 +138,7 @@ static arraycopy_platform_config arraycopy_configurations[] = {
// - prefetch after gives 40% gain on backward copies on tegra2-4,
// resulting in better number than the operating system
// copy. However, this can lead to a 300% loss on nv-tegra and has
// more impact on the cache (fetches futher than what is
// more impact on the cache (fetches further than what is
// copied). Use this configuration with care, in case it improves
// reference benchmarks.
{-256, true, true }, // forward aligned
@ -1773,7 +1773,7 @@ class StubGenerator: public StubCodeGenerator {
}
}
// Aligns 'to' by reading one word from 'from' and writting its part to 'to'.
// Aligns 'to' by reading one word from 'from' and writing its part to 'to'.
//
// Arguments:
// to: beginning (if forward) or upper bound (if !forward) of the region to be written

14
src/hotspot/cpu/arm/stubRoutinesCrypto_arm.cpp
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2008, 2016, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2008, 2022, Oracle and/or its affiliates. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
@ -33,8 +33,8 @@
// Only the first table reference is passed to AES methods below. The other 3 tables
// in ecryption and decryption are calculated in runtime by rotating the T1 result accordingly.
// It is a free operation on ARM with embedded register-shifted-register EOR capability.
// The table reference is passed in a form of a last argument on the parametes list.
// The tables lookup method proves to perform better then a runtime Galois Field caclulation,
// The table reference is passed in a form of a last argument on the parameters list.
// The tables lookup method proves to perform better than a runtime Galois Field calculation,
// due to a lack of HW acceleration for the later.
unsigned char * SBox;
@ -372,7 +372,7 @@ address generate_aescrypt_decryptBlock() {
Label round;
__ bind(round);
// each sub-block is treated similary:
// each sub-block is treated similarly:
// combine SubBytes|ShiftRows|MixColumn through a precalculated set of tables
// Utilize a Transposition Box lookup along with subsequent shift and EOR with a round key.
@ -592,7 +592,7 @@ address generate_cipherBlockChaining_encryptAESCrypt() {
// The CBC decryption could benefit from parallel processing as the blocks could be
// decrypted separatly from each other.
// decrypted separately from each other.
// NEON is utilized (if available) to perform parallel execution on 8 blocks at a time.
// Since Transposition Box (tbox) is used the parallel execution will only apply to an
// Initial Round and the last round. It's not practical to use NEON for a table lookup
@ -642,7 +642,7 @@ address generate_cipherBlockChaining_decryptAESCrypt() {
// near call is sufficient as the method is part of the StubGenerator
__ bl((address)StubRoutines::_aescrypt_decryptBlock);
// check remainig cipher size (for individual block processing)
// check remaining cipher size (for individual block processing)
__ subs(R4, R4, 16);
if (VM_Version::has_simd()) {
__ tst(R4, 0x7f);
@ -756,7 +756,7 @@ address generate_cipherBlockChaining_decryptAESCrypt() {
// Local frame map:
// sp+20 - ouput buffer pointer
// sp+20 - output buffer pointer
// sp+28 - key pointer
// sp+32 - original source
// sp+36 - block counter

6
src/hotspot/cpu/arm/templateInterpreterGenerator_arm.cpp
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2008, 2021, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2008, 2022, Oracle and/or its affiliates. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
@ -929,7 +929,7 @@ address TemplateInterpreterGenerator::generate_native_entry(bool synchronized) {
__ sub(SP, SP, AsmOperand(Rsize_of_params, lsl, LogBytesPerLong));
#ifdef __ABI_HARD__
// Allocate more stack space to accomodate all GP as well as FP registers:
// Allocate more stack space to accommodate all GP as well as FP registers:
// 4 * wordSize
// 8 * BytesPerLong
int reg_arguments = align_up((4*wordSize) + (8*BytesPerLong), StackAlignmentInBytes);
@ -1456,7 +1456,7 @@ void TemplateInterpreterGenerator::generate_throw_exception() {
// restore exception
__ get_vm_result(Rexception_obj, Rtemp);
// Inbetween activations - previous activation type unknown yet
// In between activations - previous activation type unknown yet
// compute continuation point - the continuation point expects
// the following registers set up:
//

10
src/hotspot/cpu/arm/templateTable_arm.cpp
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2008, 2021, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2008, 2022, Oracle and/or its affiliates. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
@ -164,7 +164,7 @@ AsmCondition convNegCond(TemplateTable::Condition cc) {
}
//----------------------------------------------------------------------------------------------------
// Miscelaneous helper routines
// Miscellaneous helper routines
// Store an oop (or NULL) at the address described by obj.
// Blows all volatile registers R0-R3, Rtemp, LR).
@ -2041,7 +2041,7 @@ void TemplateTable::branch(bool is_jsr, bool is_wide) {
// Handle all the JSR stuff here, then exit.
// It's much shorter and cleaner than intermingling with the
// non-JSR normal-branch stuff occuring below.
// non-JSR normal-branch stuff occurring below.
if (is_jsr) {
// compute return address as bci in R1
const Register Rret_addr = R1_tmp;
@ -2525,7 +2525,7 @@ void TemplateTable::_return(TosState state) {
//
// According to the new Java Memory Model (JMM):
// (1) All volatiles are serialized wrt to each other.
// ALSO reads & writes act as aquire & release, so:
// ALSO reads & writes act as acquire & release, so:
// (2) A read cannot let unrelated NON-volatile memory refs that happen after
// the read float up to before the read. It's OK for non-volatile memory refs
// that happen before the volatile read to float down below it.
@ -4330,7 +4330,7 @@ void TemplateTable::monitorenter() {
__ bind(allocated);
// Increment bcp to point to the next bytecode, so exception handling for async. exceptions work correctly.
// The object has already been poped from the stack, so the expression stack looks correct.
// The object has already been popped from the stack, so the expression stack looks correct.
__ add(Rbcp, Rbcp, 1);
__ str(Robj, Address(Rentry, BasicObjectLock::obj_offset_in_bytes())); // store object

4
src/hotspot/cpu/ppc/assembler_ppc.cpp
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 1997, 2021, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 1997, 2022, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2012, 2015 SAP SE. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
@ -343,7 +343,7 @@ void Assembler::load_const(Register d, long x, Register tmp) {
}
}
// Load a 64 bit constant, optimized, not identifyable.
// Load a 64 bit constant, optimized, not identifiable.
// Tmp can be used to increase ILP. Set return_simm16_rest=true to get a
// 16 bit immediate offset.
int Assembler::load_const_optimized(Register d, long x, Register tmp, bool return_simm16_rest) {

8
src/hotspot/cpu/ppc/assembler_ppc.hpp
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2002, 2021, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2002, 2022, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2012, 2021 SAP SE. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
@ -1585,7 +1585,7 @@ class Assembler : public AbstractAssembler {
inline void xoris( Register a, Register s, int ui16);
inline void andr( Register a, Register s, Register b); // suffixed by 'r' as 'and' is C++ keyword
inline void and_( Register a, Register s, Register b);
// Turn or0(rx,rx,rx) into a nop and avoid that we accidently emit a
// Turn or0(rx,rx,rx) into a nop and avoid that we accidentally emit a
// SMT-priority change instruction (see SMT instructions below).
inline void or_unchecked(Register a, Register s, Register b);
inline void orr( Register a, Register s, Register b); // suffixed by 'r' as 'or' is C++ keyword
@ -2531,7 +2531,7 @@ class Assembler : public AbstractAssembler {
inline void lvsl( VectorRegister d, Register s2);
inline void lvsr( VectorRegister d, Register s2);
// Endianess specific concatenation of 2 loaded vectors.
// Endianness specific concatenation of 2 loaded vectors.
inline void load_perm(VectorRegister perm, Register addr);
inline void vec_perm(VectorRegister first_dest, VectorRegister second, VectorRegister perm);
inline void vec_perm(VectorRegister dest, VectorRegister first, VectorRegister second, VectorRegister perm);
@ -2570,7 +2570,7 @@ class Assembler : public AbstractAssembler {
inline void load_const(Register d, AddressLiteral& a, Register tmp = noreg);
inline void load_const32(Register d, int i); // load signed int (patchable)
// Load a 64 bit constant, optimized, not identifyable.
// Load a 64 bit constant, optimized, not identifiable.
// Tmp can be used to increase ILP. Set return_simm16_rest = true to get a
// 16 bit immediate offset. This is useful if the offset can be encoded in
// a succeeding instruction.

2
src/hotspot/cpu/ppc/c1_LIRAssembler_ppc.cpp
View File

@ -3097,7 +3097,7 @@ void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) {
} else {
__ cmpdi(CCR0, obj, 0);
__ bne(CCR0, Lupdate);
__ stop("unexpect null obj");
__ stop("unexpected null obj");
#endif
}

4
src/hotspot/cpu/ppc/c1_LIRAssembler_ppc.hpp
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2000, 2021, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2000, 2022, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2012, 2015 SAP SE. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
@ -31,7 +31,7 @@
//////////////////////////////////////////////////////////////////////////////
// PPC64 load/store emission
//
// The PPC ld/st instructions cannot accomodate displacements > 16 bits long.
// The PPC ld/st instructions cannot accommodate displacements > 16 bits long.
// The following "pseudo" instructions (load/store) make it easier to
// use the indexed addressing mode by allowing 32 bit displacements:
//

6
src/hotspot/cpu/ppc/gc/z/zBarrierSetAssembler_ppc.cpp
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2021, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2021, 2022, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2021 SAP SE. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
@ -270,7 +270,7 @@ void ZBarrierSetAssembler::try_resolve_jobject_in_native(MacroAssembler* masm, R
assert_different_registers(jni_env, obj, tmp);
// Resolve the pointer using the standard implementation for weak tag handling and pointer verfication.
// Resolve the pointer using the standard implementation for weak tag handling and pointer verification.
BarrierSetAssembler::try_resolve_jobject_in_native(masm, dst, jni_env, obj, tmp, slowpath);
// Check whether pointer is dirty.
@ -526,7 +526,7 @@ class ZSetupArguments {
__ mr_if_needed(R3_ARG1, _ref);
} else if (_ref_addr.base() != R3_ARG1) {
__ mr(R3_ARG1, _ref);
__ add(R4_ARG2, (intptr_t) _ref_addr.disp(), _ref_addr.base()); // Cloberring _ref
__ add(R4_ARG2, (intptr_t) _ref_addr.disp(), _ref_addr.base()); // Clobbering _ref
} else {
// Arguments are provided in inverse order (i.e. _ref == R4_ARG2, _ref_addr == R3_ARG1)
__ mr(R0, _ref);

4
src/hotspot/cpu/ppc/gc/z/zGlobals_ppc.cpp
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2021, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2021, 2022, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2021 SAP SE. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
@ -42,7 +42,7 @@
// addressable heap address space are adjusted accordingly.
//
// The following memory schema shows an exemplary layout in which bit '45' is the highest addressable bit.
// It is assumed that this virtual memroy address space layout is predominant on the power platform.
// It is assumed that this virtual memory address space layout is predominant on the power platform.
//
// Standard Address Space & Pointer Layout
// ---------------------------------------

4
src/hotspot/cpu/ppc/interp_masm_ppc_64.cpp
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2003, 2021, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2003, 2022, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2012, 2021 SAP SE. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
@ -1838,7 +1838,7 @@ void InterpreterMacroAssembler::profile_return_type(Register ret, Register tmp1,
if (MethodData::profile_return_jsr292_only()) {
// If we don't profile all invoke bytecodes we must make sure
// it's a bytecode we indeed profile. We can't go back to the
// begining of the ProfileData we intend to update to check its
// beginning of the ProfileData we intend to update to check its
// type because we're right after it and we don't known its
// length.
lbz(tmp1, 0, R14_bcp);

10
src/hotspot/cpu/ppc/macroAssembler_ppc.cpp
View File

@ -1460,7 +1460,7 @@ void MacroAssembler::atomic_get_and_modify_generic(Register dest_current_value,
modval = tmp1;
shift_amount = tmp2;
val32 = tmp3;
// Need some preperation: Compute shift amount, align address. Note: shorts must be 2 byte aligned.
// Need some preparation: Compute shift amount, align address. Note: shorts must be 2 byte aligned.
#ifdef VM_LITTLE_ENDIAN
rldic(shift_amount, addr_base, 3, 64-5); // (dest & 3) * 8;
clrrdi(addr_base, addr_base, 2);
@ -1537,7 +1537,7 @@ void MacroAssembler::cmpxchg_loop_body(ConditionRegister flag, Register dest_cur
shift_amount = tmp1;
val32 = tmp2;
modval = tmp2;
// Need some preperation: Compute shift amount, align address. Note: shorts must be 2 byte aligned.
// Need some preparation: Compute shift amount, align address. Note: shorts must be 2 byte aligned.
#ifdef VM_LITTLE_ENDIAN
rldic(shift_amount, addr_base, 3, 64-5); // (dest & 3) * 8;
clrrdi(addr_base, addr_base, 2);
@ -1669,7 +1669,7 @@ void MacroAssembler::cmpxchg_generic(ConditionRegister flag, Register dest_curre
// (flag == eq) => (dest_current_value == compare_value), ( swapped)
}
// Preforms atomic compare exchange:
// Performs atomic compare exchange:
// if (compare_value == *addr_base)
// *addr_base = exchange_value
// int_flag_success = 1;
@ -2275,7 +2275,7 @@ void MacroAssembler::rtm_counters_update(Register abort_status, Register rtm_cou
if (failure_bit[nbit] == tm_transaction_level) {
// Don't check outer transaction, TL = 1 (bit 63). Hence only
// 11 bits in the TL field are checked to find out if failure
// occured in a nested transaction. This check also matches
// occurred in a nested transaction. This check also matches
// the case when nesting_of = 1 (nesting overflow).
rldicr_(temp_Reg, abort_status_R0, failure_bit[nbit], 10);
} else if (failure_bit[nbit] == tm_failure_code) {
@ -2414,7 +2414,7 @@ void MacroAssembler::rtm_retry_lock_on_abort(Register retry_count_Reg, Register
// transactional state, like for instance trying to write the TFHAR after a
// transaction is started; or when there is (B) a Nesting Overflow (too many
// nested transactions); or when (C) the Footprint overflows (too many
// addressess touched in TM state so there is no more space in the footprint
// addresses touched in TM state so there is no more space in the footprint
// area to track them); or in case of (D) a Self-Induced Conflict, i.e. a
// store is performed to a given address in TM state, then once in suspended
// state the same address is accessed. Failure (A) is very unlikely to occur

4
src/hotspot/cpu/ppc/macroAssembler_ppc.hpp
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2002, 2021, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2002, 2022, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2012, 2021 SAP SE. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
@ -908,7 +908,7 @@ class MacroAssembler: public Assembler {
void _verify_klass_ptr(Register reg, const char * msg, const char * file, int line) {}
// Convenience method returning function entry. For the ELFv1 case
// creates function descriptor at the current address and returs
// creates function descriptor at the current address and returns
// the pointer to it. For the ELFv2 case returns the current address.
inline address function_entry();

4
src/hotspot/cpu/ppc/macroAssembler_ppc.inline.hpp
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2002, 2021, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2002, 2022, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2012, 2021 SAP SE. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
@ -241,7 +241,7 @@ inline bool MacroAssembler::is_bc_far_variant3_at(address instruction_addr) {
// if CCR0bi is "equal", dst is set to 0, otherwise it's set to -1.
inline void MacroAssembler::set_cmp3(Register dst) {
assert_different_registers(dst, R0);
// P10, prefer using setbc intructions
// P10, prefer using setbc instructions
if (VM_Version::has_brw()) {
setbc(R0, CCR0, Assembler::greater); // Set 1 to R0 if CCR0bi is "greater than", otherwise 0
setnbc(dst, CCR0, Assembler::less); // Set -1 to dst if CCR0bi is "less than", otherwise 0

4
src/hotspot/cpu/ppc/macroAssembler_ppc_sha.cpp
View File

@ -468,7 +468,7 @@ void MacroAssembler::sha256(bool multi_block) {
#endif
// Load 16 elements from w out of the loop.
// Order of the int values is Endianess specific.
// Order of the int values is Endianness specific.
VectorRegister w0 = VR17;
VectorRegister w1 = VR18;
VectorRegister w2 = VR19;
@ -1021,7 +1021,7 @@ void MacroAssembler::sha512(bool multi_block) {
}
// Load 16 elements from w out of the loop.
// Order of the long values is Endianess specific.
// Order of the long values is Endianness specific.
VectorRegister w0 = VR10;
VectorRegister w1 = VR11;
VectorRegister w2 = VR12;

4
src/hotspot/cpu/ppc/matcher_ppc.hpp
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2021, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2021, 2022, Oracle and/or its affiliates. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
@ -153,7 +153,7 @@
return false;
}
// true means we have fast l2f convers
// true means we have fast l2f conversion
// false means that conversion is done by runtime call
static const bool convL2FSupported(void) {
// fcfids can do the conversion (>= Power7).

4
src/hotspot/cpu/ppc/methodHandles_ppc.cpp
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 1997, 2021, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 1997, 2022, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2012, 2021 SAP SE. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
@ -534,7 +534,7 @@ void trace_method_handle_stub(const char* adaptername,
// Current C frame
frame cur_frame = os::current_frame();
// Robust search of trace_calling_frame (independant of inlining).
// Robust search of trace_calling_frame (independent of inlining).
assert(cur_frame.sp() <= saved_regs, "registers not saved on stack ?");
frame trace_calling_frame = os::get_sender_for_C_frame(&cur_frame);
while (trace_calling_frame.fp() < saved_regs) {

20
src/hotspot/cpu/ppc/ppc.ad
View File

@ -1,5 +1,5 @@
//
// Copyright (c) 2011, 2021, Oracle and/or its affiliates. All rights reserved.
// Copyright (c) 2011, 2022, Oracle and/or its affiliates. All rights reserved.
// Copyright (c) 2012, 2021 SAP SE. All rights reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
//
@ -4136,7 +4136,7 @@ operand immP_NM() %{
interface(CONST_INTER);
%}
// costant 'pointer 0'.
// constant 'pointer 0'.
operand immP_0() %{
predicate(n->get_ptr() == 0);
match(ConP);
@ -4911,7 +4911,7 @@ operand cmpOp() %{
//----------OPERAND CLASSES----------------------------------------------------
// Operand Classes are groups of operands that are used to simplify
// instruction definitions by not requiring the AD writer to specify
// seperate instructions for every form of operand when the
// separate instructions for every form of operand when the
// instruction accepts multiple operand types with the same basic
// encoding and format. The classic case of this is memory operands.
// Indirect is not included since its use is limited to Compare & Swap.
@ -12133,7 +12133,7 @@ instruct cmpFastLock(flagsReg crx, iRegPdst oop, iRegPdst box, iRegPdst tmp1, iR
ins_encode %{
__ compiler_fast_lock_object($crx$$CondRegister, $oop$$Register, $box$$Register,
$tmp1$$Register, $tmp2$$Register, /*tmp3*/ R0);
// If locking was successfull, crx should indicate 'EQ'.
// If locking was successful, crx should indicate 'EQ'.
// The compiler generates a branch to the runtime call to
// _complete_monitor_locking_Java for the case where crx is 'NE'.
%}
@ -12153,7 +12153,7 @@ instruct cmpFastLock_tm(flagsReg crx, iRegPdst oop, rarg2RegP box, iRegPdst tmp1
_rtm_counters, _stack_rtm_counters,
((Method*)(ra_->C->method()->constant_encoding()))->method_data(),
/*RTM*/ true, ra_->C->profile_rtm());
// If locking was successfull, crx should indicate 'EQ'.
// If locking was successful, crx should indicate 'EQ'.
// The compiler generates a branch to the runtime call to
// _complete_monitor_locking_Java for the case where crx is 'NE'.
%}
@ -12170,7 +12170,7 @@ instruct cmpFastUnlock(flagsReg crx, iRegPdst oop, iRegPdst box, iRegPdst tmp1,
__ compiler_fast_unlock_object($crx$$CondRegister, $oop$$Register, $box$$Register,
$tmp1$$Register, $tmp2$$Register, $tmp3$$Register,
false);
// If unlocking was successfull, crx should indicate 'EQ'.
// If unlocking was successful, crx should indicate 'EQ'.
// The compiler generates a branch to the runtime call to
// _complete_monitor_unlocking_Java for the case where crx is 'NE'.
%}
@ -12187,7 +12187,7 @@ instruct cmpFastUnlock_tm(flagsReg crx, iRegPdst oop, iRegPdst box, iRegPdst tmp
__ compiler_fast_unlock_object($crx$$CondRegister, $oop$$Register, $box$$Register,
$tmp1$$Register, $tmp2$$Register, $tmp3$$Register,
/*RTM*/ true);
// If unlocking was successfull, crx should indicate 'EQ'.
// If unlocking was successful, crx should indicate 'EQ'.
// The compiler generates a branch to the runtime call to
// _complete_monitor_unlocking_Java for the case where crx is 'NE'.
%}
@ -14474,7 +14474,7 @@ instruct CallLeafDirect(method meth) %{
%}
// postalloc expand of CallLeafDirect.
// Load adress to call from TOC, then bl to it.
// Load address to call from TOC, then bl to it.
instruct CallLeafDirect_Ex(method meth) %{
match(CallLeaf);
effect(USE meth);
@ -14490,7 +14490,7 @@ instruct CallLeafDirect_Ex(method meth) %{
// Call runtime without safepoint - same as CallLeaf.
// postalloc expand of CallLeafNoFPDirect.
// Load adress to call from TOC, then bl to it.
// Load address to call from TOC, then bl to it.
instruct CallLeafNoFPDirect_Ex(method meth) %{
match(CallLeafNoFP);
effect(USE meth);
@ -14790,7 +14790,7 @@ instruct cacheWBPostSync()
//
// // Change (inc mov) to lea
// peephole %{
// // increment preceeded by register-register move
// // increment preceded by register-register move
// peepmatch ( incI_eReg movI );
// // require that the destination register of the increment
// // match the destination register of the move

4
src/hotspot/cpu/ppc/registerMap_ppc.hpp
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2000, 2021, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2000, 2022, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2012, 2013 SAP SE. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
@ -26,7 +26,7 @@
#ifndef CPU_PPC_REGISTERMAP_PPC_HPP
#define CPU_PPC_REGISTERMAP_PPC_HPP
// machine-dependent implemention for register maps
// machine-dependent implementation for register maps
friend class frame;
private:

6
src/hotspot/cpu/ppc/sharedRuntime_ppc.cpp
View File

@ -260,7 +260,7 @@ OopMap* RegisterSaver::push_frame_reg_args_and_save_live_registers(MacroAssemble
// If return_pc_adjustment != 0 adjust the return pc by return_pc_adjustment.
// Updated return pc is returned in R31 (if not return_pc_is_pre_saved).
// calcualte frame size
// calculate frame size
const int regstosave_num = sizeof(RegisterSaver_LiveRegs) /
sizeof(RegisterSaver::LiveRegType);
const int vsregstosave_num = save_vectors ? (sizeof(RegisterSaver_LiveVSRegs) /
@ -1852,7 +1852,7 @@ nmethod *SharedRuntime::generate_native_wrapper(MacroAssembler *masm,
__ verify_thread();
// Native nmethod wrappers never take possesion of the oop arguments.
// Native nmethod wrappers never take possession of the oop arguments.
// So the caller will gc the arguments.
// The only thing we need an oopMap for is if the call is static.
//
@ -2870,7 +2870,7 @@ SafepointBlob* SharedRuntime::generate_handler_blob(address call_ptr, int poll_t
// The following is basically a call_VM. However, we need the precise
// address of the call in order to generate an oopmap. Hence, we do all the
// work outselves.
// work ourselves.
__ set_last_Java_frame(/*sp=*/R1_SP, /*pc=*/noreg);
// The return address must always be correct so that the frame constructor

4
src/hotspot/cpu/ppc/stubGenerator_ppc.cpp
View File

@ -3510,7 +3510,7 @@ class StubGenerator: public StubCodeGenerator {
* scratch:
* R2, R6-R12
*
* Ouput:
* Output:
* R3_RET - int crc result
*/
// Compute CRC32 function.
@ -3958,7 +3958,7 @@ class StubGenerator: public StubCodeGenerator {
// Each element of non_match correspond to one each of the 16 input
// characters. Those elements that become 0x00 after the xxland
// instuction are invalid Base64 characters.
// instruction are invalid Base64 characters.
__ xxland(non_match->to_vsr(), M, bit);
// Compare each element to zero

6
src/hotspot/cpu/ppc/templateInterpreterGenerator_ppc.cpp
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2014, 2021, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2014, 2022, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2015, 2021 SAP SE. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
@ -81,7 +81,7 @@ address TemplateInterpreterGenerator::generate_slow_signature_handler() {
// first C-argument and to return the result_handler in
// R3_RET. Since native_entry will copy the jni-pointer to the
// first C-argument slot later on, it is OK to occupy this slot
// temporarilly. Then we copy the argument list on the java
// temporarily. Then we copy the argument list on the java
// expression stack into native varargs format on the native stack
// and load arguments into argument registers. Integer arguments in
// the varargs vector will be sign-extended to 8 bytes.
@ -2030,7 +2030,7 @@ void TemplateInterpreterGenerator::generate_throw_exception() {
__ stw(R11_scratch1, in_bytes(JavaThread::popframe_condition_offset()), R16_thread);
// Return from the current method into the deoptimization blob. Will eventually
// end up in the deopt interpeter entry, deoptimization prepared everything that
// end up in the deopt interpreter entry, deoptimization prepared everything that
// we will reexecute the call that called us.
__ merge_frames(/*top_frame_sp*/ R21_sender_SP, /*reload return_pc*/ return_pc, R11_scratch1, R12_scratch2);
__ mtlr(return_pc);

10
src/hotspot/cpu/ppc/templateTable_ppc_64.cpp
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2014, 2021, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2014, 2022, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2013, 2021 SAP SE. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
@ -1456,7 +1456,7 @@ void TemplateTable::wide_iinc() {
}
void TemplateTable::convert() {
// %%%%% Factor this first part accross platforms
// %%%%% Factor this first part across platforms
#ifdef ASSERT
TosState tos_in = ilgl;
TosState tos_out = ilgl;
@ -2334,7 +2334,7 @@ void TemplateTable::load_invoke_cp_cache_entry(int byte_no,
//
// According to the new Java Memory Model (JMM):
// (1) All volatiles are serialized wrt to each other. ALSO reads &
// writes act as aquire & release, so:
// writes act as acquire & release, so:
// (2) A read cannot let unrelated NON-volatile memory refs that
// happen after the read float up to before the read. It's OK for
// non-volatile memory refs that happen before the volatile read to
@ -4033,7 +4033,7 @@ void TemplateTable::athrow() {
// =============================================================================
// Synchronization
// Searches the basic object lock list on the stack for a free slot
// and uses it to lock the obect in tos.
// and uses it to lock the object in tos.
//
// Recursive locking is enabled by exiting the search if the same
// object is already found in the list. Thus, a new basic lock obj lock
@ -4120,7 +4120,7 @@ void TemplateTable::monitorenter() {
__ bind(Lfound);
// Increment bcp to point to the next bytecode, so exception handling for async. exceptions work correctly.
// The object has already been poped from the stack, so the expression stack looks correct.
// The object has already been popped from the stack, so the expression stack looks correct.
__ addi(R14_bcp, R14_bcp, 1);
__ std(Robj_to_lock, 0, Rcurrent_obj_addr);

6
src/hotspot/cpu/ppc/vmreg_ppc.inline.hpp
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2002, 2019, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2002, 2022, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2012, 2018 SAP SE. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
@ -28,12 +28,12 @@
inline VMReg RegisterImpl::as_VMReg() {
if (this == noreg) return VMRegImpl::Bad();
// Two halfs, multiply by 2.
// Two halves, multiply by 2.
return VMRegImpl::as_VMReg(encoding() << 1);
}
inline VMReg FloatRegisterImpl::as_VMReg() {
// Two halfs, multiply by 2.
// Two halves, multiply by 2.
return VMRegImpl::as_VMReg((encoding() << 1) + ConcreteRegisterImpl::max_gpr);
}

4
src/hotspot/cpu/riscv/abstractInterpreter_riscv.cpp
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2003, 2017, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2003, 2022, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2014, Red Hat Inc. All rights reserved.
* Copyright (c) 2020, 2022, Huawei Technologies Co., Ltd. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
@ -87,7 +87,7 @@ int AbstractInterpreter::size_activation(int max_stack,
int overhead = frame::sender_sp_offset -
frame::interpreter_frame_initial_sp_offset;
// Our locals were accounted for by the caller (or last_frame_adjust
// on the transistion) Since the callee parameters already account
// on the transition) Since the callee parameters already account
// for the callee's params we only need to account for the extra
// locals.
int size = overhead +

4
src/hotspot/cpu/riscv/assembler_riscv.hpp
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 1997, 2020, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 1997, 2022, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2014, 2020, Red Hat Inc. All rights reserved.
* Copyright (c) 2020, 2022, Huawei Technologies Co., Ltd. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
@ -222,7 +222,7 @@ class Address {
}
};
// Convience classes
// Convenience classes
class RuntimeAddress: public Address {
public:

8
src/hotspot/cpu/riscv/c1_LIRAssembler_riscv.cpp
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2000, 2020, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2000, 2022, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2014, 2020, Red Hat Inc. All rights reserved.
* Copyright (c) 2020, 2022, Huawei Technologies Co., Ltd. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
@ -359,10 +359,10 @@ int LIR_Assembler::emit_unwind_handler() {
__ bind(_unwind_handler_entry);
__ verify_not_null_oop(x10);
if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
__ mv(x9, x10); // Perserve the exception
__ mv(x9, x10); // Preserve the exception
}
// Preform needed unlocking
// Perform needed unlocking
MonitorExitStub* stub = NULL;
if (method()->is_synchronized()) {
monitor_address(0, FrameMap::r10_opr);
@ -399,7 +399,7 @@ int LIR_Assembler::emit_unwind_handler() {
}
int LIR_Assembler::emit_deopt_handler() {
// if the last instruciton is a call (typically to do a throw which
// if the last instruction is a call (typically to do a throw which
// is coming at the end after block reordering) the return address
// must still point into the code area in order to avoid assertion
// failures when searching for the corresponding bck => add a nop

6
src/hotspot/cpu/riscv/c1_MacroAssembler_riscv.cpp
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 1999, 2020, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 1999, 2022, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2014, Red Hat Inc. All rights reserved.
* Copyright (c) 2020, 2022, Huawei Technologies Co., Ltd. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
@ -205,7 +205,7 @@ void C1_MacroAssembler::initialize_object(Register obj, Register klass, Register
if (!(UseTLAB && ZeroTLAB && is_tlab_allocated)) {
// clear rest of allocated space
const Register index = tmp2;
// 16: multipler for threshold
// 16: multiplier for threshold
const int threshold = 16 * BytesPerWord; // approximate break even point for code size (see comments below)
if (var_size_in_bytes != noreg) {
mv(index, var_size_in_bytes);
@ -213,7 +213,7 @@ void C1_MacroAssembler::initialize_object(Register obj, Register klass, Register
} else if (con_size_in_bytes <= threshold) {
// use explicit null stores
int i = hdr_size_in_bytes;
if (i < con_size_in_bytes && (con_size_in_bytes % (2 * BytesPerWord))) { // 2: multipler for BytesPerWord
if (i < con_size_in_bytes && (con_size_in_bytes % (2 * BytesPerWord))) { // 2: multiplier for BytesPerWord
sd(zr, Address(obj, i));
i += BytesPerWord;
}

6
src/hotspot/cpu/riscv/c2_MacroAssembler_riscv.cpp
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2020, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2020, 2022, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2020, 2022, Huawei Technologies Co., Ltd. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
@ -284,7 +284,7 @@ void C2_MacroAssembler::string_indexof(Register haystack, Register needle,
// if (pattern.count == 0) return 0;
// We have two strings, a source string in haystack, haystack_len and a pattern string
// in needle, needle_len. Find the first occurence of pattern in source or return -1.
// in needle, needle_len. Find the first occurrence of pattern in source or return -1.
// For larger pattern and source we use a simplified Boyer Moore algorithm.
// With a small pattern and source we use linear scan.
@ -1430,7 +1430,7 @@ void C2_MacroAssembler::string_compare_v(Register str1, Register str2, Register
BLOCK_COMMENT("string_compare {");
// for Lating strings, 1 byte for 1 character
// for Latin strings, 1 byte for 1 character
// for UTF16 strings, 2 bytes for 1 character
if (!str1_isL)
sraiw(cnt1, cnt1, 1);

4
src/hotspot/cpu/riscv/gc/shenandoah/shenandoahBarrierSetAssembler_riscv.cpp
View File

@ -187,7 +187,7 @@ void ShenandoahBarrierSetAssembler::resolve_forward_pointer(MacroAssembler* masm
__ bind(is_null);
}
// IMPORTANT: This must preserve all registers, even t0 and t1, except those explicitely
// IMPORTANT: This must preserve all registers, even t0 and t1, except those explicitly
// passed in.
void ShenandoahBarrierSetAssembler::resolve_forward_pointer_not_null(MacroAssembler* masm, Register dst, Register tmp) {
assert(ShenandoahLoadRefBarrier || ShenandoahCASBarrier, "Should be enabled");
@ -499,7 +499,7 @@ void ShenandoahBarrierSetAssembler::cmpxchg_oop(MacroAssembler* masm,
// If success, then we are done.
__ beq(expected, t1, success);
// Step2: CAS failed, check the forwared pointer.
// Step2: CAS failed, check the forwarded pointer.
__ mv(t0, t1);
if (is_narrow) {

4
src/hotspot/cpu/riscv/gc/z/zBarrierSetAssembler_riscv.cpp
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2019, 2020, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2019, 2022, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2020, 2022, Huawei Technologies Co., Ltd. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
@ -382,7 +382,7 @@ void ZBarrierSetAssembler::generate_c1_load_barrier_stub(LIR_Assembler* ce,
assert_different_registers(ref, ref_addr, noreg);
// Save x10 unless it is the result or tmp register
// Set up SP to accomodate parameters and maybe x10.
// Set up SP to accommodate parameters and maybe x10.
if (ref != x10 && tmp != x10) {
__ sub(sp, sp, 32);
__ sd(x10, Address(sp, 16));

6
src/hotspot/cpu/riscv/gc/z/zGlobals_riscv.cpp
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2017, 2021, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2017, 2022, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2020, 2021, Huawei Technologies Co., Ltd. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
@ -156,12 +156,12 @@ static size_t probe_valid_max_address_bit() {
for (size_t i = DEFAULT_MAX_ADDRESS_BIT; i > MINIMUM_MAX_ADDRESS_BIT; --i) {
const uintptr_t base_addr = ((uintptr_t) 1U) << i;
if (msync((void*)base_addr, page_size, MS_ASYNC) == 0) {
// msync suceeded, the address is valid, and maybe even already mapped.
// msync succeeded, the address is valid, and maybe even already mapped.
max_address_bit = i;
break;
}
if (errno != ENOMEM) {
// Some error occured. This should never happen, but msync
// Some error occurred. This should never happen, but msync
// has some undefined behavior, hence ignore this bit.
#ifdef ASSERT
fatal("Received '%s' while probing the address space for the highest valid bit", os::errno_name(errno));

6
src/hotspot/cpu/riscv/interp_masm_riscv.cpp
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2003, 2020, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2003, 2022, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2014, 2020, Red Hat Inc. All rights reserved.
* Copyright (c) 2020, 2022, Huawei Technologies Co., Ltd. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
@ -572,7 +572,7 @@ void InterpreterMacroAssembler::dispatch_via(TosState state, address* table) {
//
// Apply stack watermark barrier.
// Unlock the receiver if this is a synchronized method.
// Unlock any Java monitors from syncronized blocks.
// Unlock any Java monitors from synchronized blocks.
// Remove the activation from the stack.
//
// If there are locked Java monitors
@ -1827,7 +1827,7 @@ void InterpreterMacroAssembler::profile_return_type(Register mdp, Register ret,
// If we don't profile all invoke bytecodes we must make sure
// it's a bytecode we indeed profile. We can't go back to the
// begining of the ProfileData we intend to update to check its
// beginning of the ProfileData we intend to update to check its
// type because we're right after it and we don't known its
// length
Label do_profile;

4
src/hotspot/cpu/riscv/interp_masm_riscv.hpp
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2003, 2019, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2003, 2022, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2014, 2015, Red Hat Inc. All rights reserved.
* Copyright (c) 2020, 2021, Huawei Technologies Co., Ltd. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
@ -31,7 +31,7 @@
#include "interpreter/invocationCounter.hpp"
#include "runtime/frame.hpp"
// This file specializes the assember with interpreter-specific macros
// This file specializes the assembler with interpreter-specific macros
typedef ByteSize (*OffsetFunction)(uint);

26
src/hotspot/cpu/riscv/macroAssembler_riscv.cpp
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 1997, 2020, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 1997, 2022, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2014, 2020, Red Hat Inc. All rights reserved.
* Copyright (c) 2020, 2022, Huawei Technologies Co., Ltd. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
@ -1391,7 +1391,7 @@ void MacroAssembler::mv(Register Rd, Address dest) {
}
void MacroAssembler::mv(Register Rd, address addr) {
// Here in case of use with relocation, use fix length instruciton
// Here in case of use with relocation, use fix length instruction
// movptr instead of li
movptr(Rd, addr);
}
@ -2107,7 +2107,7 @@ void MacroAssembler::lookup_interface_method(Register recv_klass,
beq(intf_klass, method_result, found_method);
bind(search);
// Check that the previous entry is non-null. A null entry means that
// the receiver class doens't implement the interface, and wasn't the
// the receiver class doesn't implement the interface, and wasn't the
// same as when the caller was compiled.
beqz(method_result, L_no_such_interface, /* is_far */ true);
addi(scan_tmp, scan_tmp, scan_step);
@ -2163,9 +2163,9 @@ void MacroAssembler::membar(uint32_t order_constraint) {
}
}
// Form an addres from base + offset in Rd. Rd my or may not
// Form an address from base + offset in Rd. Rd my or may not
// actually be used: you must use the Address that is returned. It
// is up to you to ensure that the shift provided mathces the size
// is up to you to ensure that the shift provided matches the size
// of your data.
Address MacroAssembler::form_address(Register Rd, Register base, long byte_offset) {
if (is_offset_in_range(byte_offset, 12)) { // 12: imm in range 2^12
@ -2551,7 +2551,7 @@ void MacroAssembler::check_klass_subtype_fast_path(Register sub_klass,
// This self-check enables sharing of secondary supertype arrays among
// non-primary types such as array-of-interface. Otherwise, each such
// type would need its own customized SSA.
// We move this check to the front fo the fast path because many
// We move this check to the front of the fast path because many
// type checks are in fact trivially successful in this manner,
// so we get a nicely predicted branch right at the start of the check.
beq(sub_klass, super_klass, *L_success);
@ -2565,11 +2565,11 @@ void MacroAssembler::check_klass_subtype_fast_path(Register sub_klass,
Address super_check_addr(t0);
ld(t0, super_check_addr); // load displayed supertype
// Ths check has worked decisively for primary supers.
// This check has worked decisively for primary supers.
// Secondary supers are sought in the super_cache ('super_cache_addr').
// (Secondary supers are interfaces and very deeply nested subtypes.)
// This works in the same check above because of a tricky aliasing
// between the super_Cache and the primary super dispaly elements.
// between the super_Cache and the primary super display elements.
// (The 'super_check_addr' can address either, as the case requires.)
// Note that the cache is updated below if it does not help us find
// what we need immediately.
@ -2590,7 +2590,7 @@ void MacroAssembler::check_klass_subtype_fast_path(Register sub_klass,
#undef final_jmp
}
// Scans count pointer sized words at [addr] for occurence of value,
// Scans count pointer sized words at [addr] for occurrence of value,
// generic
void MacroAssembler::repne_scan(Register addr, Register value, Register count,
Register tmp) {
@ -2624,7 +2624,7 @@ void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass,
assert(label_nulls <= 1, "at most one NULL in the batch");
// A couple of usefule fields in sub_klass:
// A couple of useful fields in sub_klass:
int ss_offset = in_bytes(Klass::secondary_supers_offset());
int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
Address secondary_supers_addr(sub_klass, ss_offset);
@ -2635,7 +2635,7 @@ void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass,
// Do a linear scan of the secondary super-klass chain.
// This code is rarely used, so simplicity is a virtue here.
// The repne_scan instruction uses fixed registers, which we must spill.
// Don't worry too much about pre-existing connecitons with the input regs.
// Don't worry too much about pre-existing connections with the input regs.
assert(sub_klass != x10, "killed reg"); // killed by mv(x10, super)
assert(sub_klass != x12, "killed reg"); // killed by la(x12, &pst_counter)
@ -2941,7 +2941,7 @@ address MacroAssembler::emit_trampoline_stub(int insts_call_instruction_offset,
// instructions code-section.
// make sure 4 byte aligned here, so that the destination address would be
// 8 byte aligned after 3 intructions
// 8 byte aligned after 3 instructions
// when we reach here we may get a 2-byte alignment so need to align it
align(wordSize, NativeCallTrampolineStub::data_offset);
@ -3053,7 +3053,7 @@ void MacroAssembler::compute_match_mask(Register src, Register pattern, Register
}
#ifdef COMPILER2
// Code for BigInteger::mulAdd instrinsic
// Code for BigInteger::mulAdd intrinsic
// out = x10
// in = x11
// offset = x12 (already out.length-offset)

12
src/hotspot/cpu/riscv/macroAssembler_riscv.hpp
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 1997, 2020, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 1997, 2022, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2014, 2020, Red Hat Inc. All rights reserved.
* Copyright (c) 2020, 2022, Huawei Technologies Co., Ltd. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
@ -225,7 +225,7 @@ class MacroAssembler: public Assembler {
void store_heap_oop_null(Address dst);
// This dummy is to prevent a call to store_heap_oop from
// converting a zero (linke NULL) into a Register by giving
// converting a zero (linked NULL) into a Register by giving
// the compiler two choices it can't resolve
void store_heap_oop(Address dst, void* dummy);
@ -262,9 +262,9 @@ class MacroAssembler: public Assembler {
RegisterOrConstant vtable_index,
Register method_result);
// Form an addres from base + offset in Rd. Rd my or may not
// Form an address from base + offset in Rd. Rd my or may not
// actually be used: you must use the Address that is returned. It
// is up to you to ensure that the shift provided mathces the size
// is up to you to ensure that the shift provided matches the size
// of your data.
Address form_address(Register Rd, Register base, long byte_offset);
@ -302,9 +302,9 @@ class MacroAssembler: public Assembler {
Label* L_slow_path,
Register super_check_offset = noreg);
// The reset of the type cehck; must be wired to a corresponding fast path.
// The reset of the type check; must be wired to a corresponding fast path.
// It does not repeat the fast path logic, so don't use it standalone.
// The tmp1_reg and tmp2_reg can be noreg, if no temps are avaliable.
// The tmp1_reg and tmp2_reg can be noreg, if no temps are available.
// Updates the sub's secondary super cache as necessary.
void check_klass_subtype_slow_path(Register sub_klass,
Register super_klass,

4
src/hotspot/cpu/riscv/matcher_riscv.hpp
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2021, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2021, 2022, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2021, 2022, Huawei Technologies Co., Ltd. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
@ -152,7 +152,7 @@
return false;
}
// true means we have fast l2f convers
// true means we have fast l2f conversion
// false means that conversion is done by runtime call
static constexpr bool convL2FSupported(void) {
return true;

4
src/hotspot/cpu/riscv/registerMap_riscv.hpp
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 1998, 2020, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 1998, 2022, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2020, 2021, Huawei Technologies Co., Ltd. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
@ -26,7 +26,7 @@
#ifndef CPU_RISCV_REGISTERMAP_RISCV_HPP
#define CPU_RISCV_REGISTERMAP_RISCV_HPP
// machine-dependent implemention for register maps
// machine-dependent implementation for register maps
friend class frame;
private:

8
src/hotspot/cpu/riscv/riscv.ad
View File

@ -1,5 +1,5 @@
//
// Copyright (c) 2003, 2020, Oracle and/or its affiliates. All rights reserved.
// Copyright (c) 2003, 2022, Oracle and/or its affiliates. All rights reserved.
// Copyright (c) 2014, 2020, Red Hat Inc. All rights reserved.
// Copyright (c) 2020, 2022, Huawei Technologies Co., Ltd. All rights reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
@ -29,7 +29,7 @@
//----------REGISTER DEFINITION BLOCK------------------------------------------
// This information is used by the matcher and the register allocator to
// describe individual registers and classes of registers within the target
// archtecture.
// architecture.
register %{
//----------Architecture Description Register Definitions----------------------
@ -2591,10 +2591,10 @@ encode %{
// Region 6-7 is determined per call site.
// Note 2: If the calling convention leaves holes in the incoming argument
// area, those holes are owned by SELF. Holes in the outgoing area
// are owned by the CALLEE. Holes should not be nessecary in the
// are owned by the CALLEE. Holes should not be necessary in the
// incoming area, as the Java calling convention is completely under
// the control of the AD file. Doubles can be sorted and packed to
// avoid holes. Holes in the outgoing arguments may be nessecary for
// avoid holes. Holes in the outgoing arguments may be necessary for
// varargs C calling conventions.
// Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
// even aligned with pad0 as needed.

8
src/hotspot/cpu/riscv/sharedRuntime_riscv.cpp
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2003, 2020, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2003, 2022, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2014, 2020, Red Hat Inc. All rights reserved.
* Copyright (c) 2020, 2022, Huawei Technologies Co., Ltd. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
@ -624,7 +624,7 @@ AdapterHandlerEntry* SharedRuntime::generate_i2c2i_adapters(MacroAssembler *masm
// require some stack space. We grow the current (compiled) stack, then repack
// the args. We finally end in a jump to the generic interpreter entry point.
// On exit from the interpreter, the interpreter will restore our SP (lest the
// compiled code, which relys solely on SP and not FP, get sick).
// compiled code, which relies solely on SP and not FP, get sick).
{
__ block_comment("c2i_unverified_entry {");
@ -1129,7 +1129,7 @@ static void gen_special_dispatch(MacroAssembler* masm,
// They are roughly structured like this:
// if (GCLocker::needs_gc()) SharedRuntime::block_for_jni_critical()
// tranistion to thread_in_native
// unpack arrray arguments and call native entry point
// unpack array arguments and call native entry point
// check for safepoint in progress
// check if any thread suspend flags are set
// call into JVM and possible unlock the JNI critical
@ -2430,7 +2430,7 @@ SafepointBlob* SharedRuntime::generate_handler_blob(address call_ptr, int poll_t
// The following is basically a call_VM. However, we need the precise
// address of the call in order to generate an oopmap. Hence, we do all the
// work outselves.
// work ourselves.
Label retaddr;
__ set_last_Java_frame(sp, noreg, retaddr, t0);

10
src/hotspot/cpu/riscv/stubGenerator_riscv.cpp
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2003, 2020, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2003, 2022, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2014, 2020, Red Hat Inc. All rights reserved.
* Copyright (c) 2020, 2022, Huawei Technologies Co., Ltd. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
@ -1022,7 +1022,7 @@ class StubGenerator: public StubCodeGenerator {
//
// If 'from' and/or 'to' are aligned on 4-byte boundaries, we let
// the hardware handle it. The two dwords within qwords that span
// cache line boundaries will still be loaded and stored atomicly.
// cache line boundaries will still be loaded and stored atomically.
//
// Side Effects:
// disjoint_int_copy_entry is set to the no-overlap entry point
@ -1094,7 +1094,7 @@ class StubGenerator: public StubCodeGenerator {
//
// If 'from' and/or 'to' are aligned on 4-byte boundaries, we let
// the hardware handle it. The two dwords within qwords that span
// cache line boundaries will still be loaded and stored atomicly.
// cache line boundaries will still be loaded and stored atomically.
//
address generate_conjoint_copy(size_t size, bool aligned, bool is_oop, address nooverlap_target,
address* entry, const char* name,
@ -1262,7 +1262,7 @@ class StubGenerator: public StubCodeGenerator {
//
// If 'from' and/or 'to' are aligned on 4-byte boundaries, we let
// the hardware handle it. The two dwords within qwords that span
// cache line boundaries will still be loaded and stored atomicly.
// cache line boundaries will still be loaded and stored atomically.
//
// Side Effects:
// disjoint_int_copy_entry is set to the no-overlap entry point
@ -1286,7 +1286,7 @@ class StubGenerator: public StubCodeGenerator {
//
// If 'from' and/or 'to' are aligned on 4-byte boundaries, we let
// the hardware handle it. The two dwords within qwords that span
// cache line boundaries will still be loaded and stored atomicly.
// cache line boundaries will still be loaded and stored atomically.
//
address generate_conjoint_int_copy(bool aligned, address nooverlap_target,
address* entry, const char* name,

18
src/hotspot/cpu/riscv/templateTable_riscv.cpp
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2003, 2020, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2003, 2022, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2014, Red Hat Inc. All rights reserved.
* Copyright (c) 2020, 2022, Huawei Technologies Co., Ltd. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
@ -126,7 +126,7 @@ static inline Address at_tos_p5() {
return Address(esp, Interpreter::expr_offset_in_bytes(5));
}
// Miscelaneous helper routines
// Miscellaneous helper routines
// Store an oop (or NULL) at the Address described by obj.
// If val == noreg this means store a NULL
static void do_oop_store(InterpreterMacroAssembler* _masm,
@ -2221,7 +2221,7 @@ void TemplateTable::_return(TosState state)
//
// According to the new Java Memory Model (JMM):
// (1) All volatiles are serialized wrt to each other. ALSO reads &
// writes act as aquire & release, so:
// writes act as acquire & release, so:
// (2) A read cannot let unrelated NON-volatile memory refs that
// happen after the read float up to before the read. It's OK for
// non-volatile memory refs that happen before the volatile read to
@ -2352,7 +2352,7 @@ void TemplateTable::load_invoke_cp_cache_entry(int byte_no,
void TemplateTable::jvmti_post_field_access(Register cache, Register index,
bool is_static, bool has_tos) {
// do the JVMTI work here to avoid disturbing the register state below
// We use c_rarg registers here beacause we want to use the register used in
// We use c_rarg registers here because we want to use the register used in
// the call to the VM
if (JvmtiExport::can_post_field_access()) {
// Check to see if a field access watch has been set before we
@ -2424,7 +2424,7 @@ void TemplateTable::getfield_or_static(int byte_no, bool is_static, RewriteContr
assert(btos == 0, "change code, btos != 0");
__ bnez(flags, notByte);
// Dont't rewrite getstatic, only getfield
// Don't rewrite getstatic, only getfield
if (is_static) {
rc = may_not_rewrite;
}
@ -2445,7 +2445,7 @@ void TemplateTable::getfield_or_static(int byte_no, bool is_static, RewriteContr
// ztos (same code as btos)
__ access_load_at(T_BOOLEAN, IN_HEAP, x10, field, noreg, noreg);
__ push(ztos);
// Rewirte bytecode to be faster
// Rewrite bytecode to be faster
if (rc == may_rewrite) {
// uses btos rewriting, no truncating to t/f bit is needed for getfield
patch_bytecode(Bytecodes::_fast_bgetfield, bc, x11);
@ -3287,7 +3287,7 @@ void TemplateTable::invokespecial(int byte_no)
void TemplateTable::invokestatic(int byte_no)
{
transition(vtos, vtos);
assert(byte_no == f1_byte, "use this arugment");
assert(byte_no == f1_byte, "use this argument");
prepare_invoke(byte_no, xmethod); // get f1 Method*
// do the call
@ -3546,7 +3546,7 @@ void TemplateTable::_new() {
__ sub(x13, x13, sizeof(oopDesc));
__ beqz(x13, initialize_header);
// Initialize obejct fields
// Initialize object fields
{
__ add(x12, x10, sizeof(oopDesc));
Label loop;
@ -3859,7 +3859,7 @@ void TemplateTable::monitorenter()
// Increment bcp to point to the next bytecode, so exception
// handling for async. exceptions work correctly.
// The object has already been poped from the stack, so the
// The object has already been popped from the stack, so the
// expression stack looks correct.
__ addi(xbcp, xbcp, 1);

4
src/hotspot/cpu/s390/c1_LIRAssembler_s390.cpp
View File

@ -219,7 +219,7 @@ int LIR_Assembler::emit_unwind_handler() {
__ lgr_if_needed(exception_oop_callee_saved, Z_EXC_OOP); // Preserve the exception.
}
// Preform needed unlocking.
// Perform needed unlocking.
MonitorExitStub* stub = NULL;
if (method()->is_synchronized()) {
// Runtime1::monitorexit_id expects lock address in Z_R1_scratch.
@ -2992,7 +2992,7 @@ void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) {
__ z_bru(next);
}
} else {
__ asm_assert_ne("unexpect null obj", __LINE__);
__ asm_assert_ne("unexpected null obj", __LINE__);
}
__ bind(update);

6
src/hotspot/cpu/s390/c1_LIRGenerator_s390.cpp
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2016, 2021, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2016, 2022, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2016, 2017 SAP SE. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
@ -339,7 +339,7 @@ void LIRGenerator::do_ArithmeticOp_FPU(ArithmeticOp* x) {
// for _ladd, _lmul, _lsub, _ldiv, _lrem
void LIRGenerator::do_ArithmeticOp_Long(ArithmeticOp* x) {
if (x->op() == Bytecodes::_ldiv || x->op() == Bytecodes::_lrem) {
// Use shifts if divisior is a power of 2 otherwise use DSGR instruction.
// Use shifts if divisor is a power of 2 otherwise use DSGR instruction.
// Instruction: DSGR R1, R2
// input : R1+1: dividend (R1, R1+1 designate a register pair, R1 must be even)
// R2: divisor
@ -415,7 +415,7 @@ void LIRGenerator::do_ArithmeticOp_Long(ArithmeticOp* x) {
// for: _iadd, _imul, _isub, _idiv, _irem
void LIRGenerator::do_ArithmeticOp_Int(ArithmeticOp* x) {
if (x->op() == Bytecodes::_idiv || x->op() == Bytecodes::_irem) {
// Use shifts if divisior is a power of 2 otherwise use DSGFR instruction.
// Use shifts if divisor is a power of 2 otherwise use DSGFR instruction.
// Instruction: DSGFR R1, R2
// input : R1+1: dividend (R1, R1+1 designate a register pair, R1 must be even)
// R2: divisor

4
src/hotspot/cpu/s390/frame_s390.inline.hpp
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2016, 2019, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2016, 2022, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2016 SAP SE. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
@ -93,7 +93,7 @@ inline BasicObjectLock** frame::interpreter_frame_monitors_addr() const {
return (BasicObjectLock**) &(ijava_state()->monitors);
}
// The next two funcions read and write z_ijava_state.monitors.
// The next two functions read and write z_ijava_state.monitors.
inline BasicObjectLock* frame::interpreter_frame_monitors() const {
return *interpreter_frame_monitors_addr();
}

6
src/hotspot/cpu/s390/interp_masm_s390.cpp
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2016, 2021, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2016, 2022, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2016, 2020 SAP SE. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
@ -750,7 +750,7 @@ void InterpreterMacroAssembler::get_cpool_and_tags(Register Rcpool, Register Rta
// Unlock if synchronized method.
//
// Unlock the receiver if this is a synchronized method.
// Unlock any Java monitors from syncronized blocks.
// Unlock any Java monitors from synchronized blocks.
//
// If there are locked Java monitors
// If throw_monitor_exception
@ -910,7 +910,7 @@ void InterpreterMacroAssembler::narrow(Register result, Register ret_type) {
// remove activation
//
// Unlock the receiver if this is a synchronized method.
// Unlock any Java monitors from syncronized blocks.
// Unlock any Java monitors from synchronized blocks.
// Remove the activation from the stack.
//
// If there are locked Java monitors

6
src/hotspot/cpu/s390/interp_masm_s390.hpp
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2016, 2019, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2016, 2022, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2016, 2017 SAP SE. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
@ -29,7 +29,7 @@
#include "asm/macroAssembler.hpp"
#include "interpreter/invocationCounter.hpp"
// This file specializes the assember with interpreter-specific macros.
// This file specializes the assembler with interpreter-specific macros.
class InterpreterMacroAssembler: public MacroAssembler {
@ -72,7 +72,7 @@ class InterpreterMacroAssembler: public MacroAssembler {
// Helper routine for frame allocation/deallocation.
// Compute the delta by which the caller's SP has to
// be adjusted to accomodate for the non-argument locals.
// be adjusted to accommodate for the non-argument locals.
void compute_extra_locals_size_in_bytes(Register args_size, Register locals_size, Register delta);
// dispatch routines

20
src/hotspot/cpu/s390/macroAssembler_s390.cpp
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2016, 2021, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2016, 2022, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2016, 2019 SAP SE. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
@ -1241,7 +1241,7 @@ bool MacroAssembler::is_compare_immediate_narrow_klass(address pos) {
// patch the load_constant
//-----------------------------------
// CPU-version dependend patching of load_const.
// CPU-version dependent patching of load_const.
void MacroAssembler::patch_const(address a, long x) {
assert(is_load_const(a), "not a load of a constant");
// Note: Right shift is only cleanly defined for unsigned types
@ -1427,7 +1427,7 @@ int MacroAssembler::store_const(const Address &dest, long imm,
//=== N O T P A T CH A B L E C O N S T A N T S ===
//===================================================================
// Load constant x into register t with a fast instrcution sequence
// Load constant x into register t with a fast instruction sequence
// depending on the bits in x. Preserves CC under all circumstances.
int MacroAssembler::load_const_optimized_rtn_len(Register t, long x, bool emit) {
if (x == 0) {
@ -2423,7 +2423,7 @@ bool MacroAssembler::is_call_far_patchable_variant2_at(address instruction_addr)
//
// A call_far_patchable comes in different flavors:
// - LARL(CP) / LG(CP) / BR (address in constant pool, access via CP register)
// - LGRL(CP) / BR (address in constant pool, pc-relative accesss)
// - LGRL(CP) / BR (address in constant pool, pc-relative access)
// - BRASL (relative address of call target coded in instruction)
// All flavors occupy the same amount of space. Length differences are compensated
// by leading nops, such that the instruction sequence always ends at the same
@ -2844,7 +2844,7 @@ void MacroAssembler::lookup_virtual_method(Register recv_klass,
// trapMarker - Marking byte for the generated illtrap instructions (if any).
// Any value except 0x00 is supported.
// = 0x00 - do not generate illtrap instructions.
// use nops to fill ununsed space.
// use nops to fill unused space.
// requiredSize - required size of the generated code. If the actually
// generated code is smaller, use padding instructions to fill up.
// = 0 - no size requirement, no padding.
@ -3009,7 +3009,7 @@ void MacroAssembler::check_klass_subtype_slow_path(Register Rsubklass,
Label* L_success,
Label* L_failure) {
// Input registers must not overlap.
// Also check for R1 which is explicitely used here.
// Also check for R1 which is explicitly used here.
assert_different_registers(Z_R1, Rsubklass, Rsuperklass, Rarray_ptr, Rlength);
NearLabel L_fallthrough;
int label_nulls = 0;
@ -3417,7 +3417,7 @@ void MacroAssembler::encode_klass_not_null(Register dst, Register src) {
z_tmll(current, KlassAlignmentInBytes-1); // Check alignment.
z_brc(Assembler::bcondAllZero, ok);
// The plain disassembler does not recognize illtrap. It instead displays
// a 32-bit value. Issueing two illtraps assures the disassembler finds
// a 32-bit value. Issuing two illtraps assures the disassembler finds
// the proper beginning of the next instruction.
z_illtrap(0xee);
z_illtrap(0xee);
@ -3561,7 +3561,7 @@ void MacroAssembler::decode_klass_not_null(Register dst) {
z_tmll(dst, KlassAlignmentInBytes-1); // Check alignment.
z_brc(Assembler::bcondAllZero, ok);
// The plain disassembler does not recognize illtrap. It instead displays
// a 32-bit value. Issueing two illtraps assures the disassembler finds
// a 32-bit value. Issuing two illtraps assures the disassembler finds
// the proper beginning of the next instruction.
z_illtrap(0xd1);
z_illtrap(0xd1);
@ -3608,7 +3608,7 @@ void MacroAssembler::decode_klass_not_null(Register dst, Register src) {
z_tmll(dst, KlassAlignmentInBytes-1); // Check alignment.
z_brc(Assembler::bcondAllZero, ok);
// The plain disassembler does not recognize illtrap. It instead displays
// a 32-bit value. Issueing two illtraps assures the disassembler finds
// a 32-bit value. Issuing two illtraps assures the disassembler finds
// the proper beginning of the next instruction.
z_illtrap(0xd2);
z_illtrap(0xd2);
@ -5493,7 +5493,7 @@ void MacroAssembler::stop(int type, const char* msg, int id) {
push_frame_abi160(0);
call_VM_leaf(CAST_FROM_FN_PTR(address, stop_on_request), Z_ARG1, Z_ARG2);
// The plain disassembler does not recognize illtrap. It instead displays
// a 32-bit value. Issueing two illtraps assures the disassembler finds
// a 32-bit value. Issuing two illtraps assures the disassembler finds
// the proper beginning of the next instruction.
z_illtrap(); // Illegal instruction.
z_illtrap(); // Illegal instruction.

2
src/hotspot/cpu/s390/matcher_s390.hpp
View File

@ -144,7 +144,7 @@
return false;
}
// true means we have fast l2f convers
// true means we have fast l2f conversion
// false means that conversion is done by runtime call
static constexpr bool convL2FSupported(void) {
return true;

4
src/hotspot/cpu/s390/methodHandles_s390.cpp
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2016, 2021, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2016, 2022, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2016, 2017 SAP SE. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
@ -591,7 +591,7 @@ void trace_method_handle_stub(const char* adaptername,
intptr_t *dump_sp = cur_frame.sender_sp();
intptr_t *dump_fp = cur_frame.link();
bool walkable = has_mh; // Whether the traced frame shoud be walkable.
bool walkable = has_mh; // Whether the traced frame should be walkable.
// The sender for cur_frame is the caller of trace_method_handle.
if (walkable) {

6
src/hotspot/cpu/s390/nativeInst_s390.cpp
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2016, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2016, 2022, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2016 SAP SE. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
@ -277,7 +277,7 @@ void NativeFarCall::set_destination(address dest, int toc_offset) {
// Here, we have a pc-relative call (brasl).
// Be aware: dest may have moved in this case, so really patch the displacement,
// when necessary!
// This while loop will also consume the nop which always preceeds a call_far_pcrelative.
// This while loop will also consume the nop which always precedes a call_far_pcrelative.
// We need to revert this after the loop. Pc-relative calls are always assumed to have a leading nop.
unsigned int nop_sz = MacroAssembler::nop_size();
unsigned int nop_bytes = 0;
@ -306,7 +306,7 @@ void NativeFarCall::set_destination(address dest, int toc_offset) {
void NativeMovConstReg::verify() {
address loc = addr_at(0);
// This while loop will also consume the nop which always preceeds a
// This while loop will also consume the nop which always precedes a
// call_far_pcrelative. We need to revert this after the
// loop. Pc-relative calls are always assumed to have a leading nop.
unsigned int nop_sz = MacroAssembler::nop_size();

10
src/hotspot/cpu/s390/s390.ad
View File

@ -39,7 +39,7 @@
// On more recent models (from z9 on), I-fetch is done on a Octoword
// (32 bytes at a time) basis. To avoid I-fetching unnecessary
// instructions, branch targets should be 32-byte aligend. If this
// exact alingment cannot be achieved, having the branch target in
// exact alignment cannot be achieved, having the branch target in
// the first doubleword still provides some benefit.
// - Avoid branch targets at the end of cache lines (> 64 bytes distance).
// Sequential instruction prefetching after the branch target starts
@ -47,7 +47,7 @@
// branch target. When I-fetching crosses a cache line, there may be
// a small stall. The worst case: the branch target (at the end of
// a cache line) is a L1 I-cache miss and the next line as well.
// Then, the entire target line must be filled first (to contine at the
// Then, the entire target line must be filled first (to continue at the
// branch target). Only then can the next sequential line be filled.
// - Avoid multiple poorly predicted branches in a row.
//
@ -3663,7 +3663,7 @@ operand cmpOp() %{
//----------OPERAND CLASSES----------------------------------------------------
// Operand Classes are groups of operands that are used to simplify
// instruction definitions by not requiring the AD writer to specify
// seperate instructions for every form of operand when the
// separate instructions for every form of operand when the
// instruction accepts multiple operand types with the same basic
// encoding and format. The classic case of this is memory operands.
// Indirect is not included since its use is limited to Compare & Swap
@ -10339,7 +10339,7 @@ instruct encode_ascii_array(iRegP src, iRegP dst, iRegI result, iRegI len, iRegI
//
// // Change (inc mov) to lea
// peephole %{
// // increment preceeded by register-register move
// // increment preceded by register-register move
// peepmatch (incI_eReg movI);
// // require that the destination register of the increment
// // match the destination register of the move
@ -10755,7 +10755,7 @@ instruct bytes_reverse_long(iRegL dst, iRegL src) %{
// returns the bit position of the leftmost 1 in the 64bit source register.
// As the bits are numbered from left to right (0..63), the returned
// position index is equivalent to the number of leading zeroes.
// If no 1-bit is found (i.e. the regsiter contains zero), the instruction
// If no 1-bit is found (i.e. the register contains zero), the instruction
// returns position 64. That's exactly what we need.
instruct countLeadingZerosI(revenRegI dst, iRegI src, roddRegI tmp, flagsReg cr) %{

4
src/hotspot/cpu/s390/sharedRuntime_s390.cpp
View File

@ -1266,7 +1266,7 @@ static void move32_64(MacroAssembler *masm,
if (src.first()->is_stack()) {
Address memaddr(Z_SP, reg2offset(src.first()) + frame_offset);
if (dst.first()->is_stack()) {
// stack -> stack. MVC not posible due to sign extension.
// stack -> stack. MVC not possible due to sign extension.
Address firstaddr(Z_SP, reg2offset(dst.first()));
__ mem2reg_signed_opt(Z_R0_scratch, memaddr);
__ reg2mem_opt(Z_R0_scratch, firstaddr);
@ -2881,7 +2881,7 @@ SafepointBlob* SharedRuntime::generate_handler_blob(address call_ptr, int poll_t
// The following is basically a call_VM. However, we need the precise
// address of the call in order to generate an oopmap. Hence, we do all the
// work outselves.
// work ourselves.
__ set_last_Java_frame(Z_SP, noreg);
// call into the runtime to handle the safepoint poll

6
src/hotspot/cpu/s390/stubGenerator_s390.cpp
View File

@ -1924,7 +1924,7 @@ class StubGenerator: public StubCodeGenerator {
if (multiBlock) { // Process everything from offset to limit.
// The following description is valid if we get a raw (unpimped) source data buffer,
// spanning the range between [srcOff(Z_ARG3), srcLimit(Z_ARG4)). As detailled above,
// spanning the range between [srcOff(Z_ARG3), srcLimit(Z_ARG4)). As detailed above,
// the calling convention for these stubs is different. We leave the description in
// to inform the reader what must be happening hidden in the calling code.
//
@ -2004,7 +2004,7 @@ class StubGenerator: public StubCodeGenerator {
if (multiBlock) { // Process everything from offset to limit.
// The following description is valid if we get a raw (unpimped) source data buffer,
// spanning the range between [srcOff(Z_ARG3), srcLimit(Z_ARG4)). As detailled above,
// spanning the range between [srcOff(Z_ARG3), srcLimit(Z_ARG4)). As detailed above,
// the calling convention for these stubs is different. We leave the description in
// to inform the reader what must be happening hidden in the calling code.
//
@ -2084,7 +2084,7 @@ class StubGenerator: public StubCodeGenerator {
if (multiBlock) { // Process everything from offset to limit.
// The following description is valid if we get a raw (unpimped) source data buffer,
// spanning the range between [srcOff(Z_ARG3), srcLimit(Z_ARG4)). As detailled above,
// spanning the range between [srcOff(Z_ARG3), srcLimit(Z_ARG4)). As detailed above,
// the calling convention for these stubs is different. We leave the description in
// to inform the reader what must be happening hidden in the calling code.
//

4
src/hotspot/cpu/s390/templateInterpreterGenerator_s390.cpp
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2016, 2021, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2016, 2022, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2016, 2020 SAP SE. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
@ -342,7 +342,7 @@ address TemplateInterpreterGenerator::generate_slow_signature_handler() {
__ add2reg(arg_c, BytesPerWord);
__ z_bru(loop_start);
// Method exit, all arguments proocessed.
// Method exit, all arguments processed.
__ bind(loop_end);
__ z_lmg(Z_R10, Z_R13, frame::z_abi_160_size, Z_SP); // restore registers before frame is popped.
__ pop_frame();

4
src/hotspot/cpu/s390/templateTable_s390.cpp
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2016, 2021, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2016, 2022, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2016, 2020 SAP SE. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
@ -4152,7 +4152,7 @@ void TemplateTable::monitorenter() {
// Increment bcp to point to the next bytecode, so exception
// handling for async. exceptions work correctly.
// The object has already been poped from the stack, so the
// The object has already been popped from the stack, so the
// expression stack looks correct.
__ add2reg(Z_bcp, 1, Z_bcp);

4
src/hotspot/cpu/x86/abstractInterpreter_x86.cpp
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 1997, 2017, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 1997, 2022, Oracle and/or its affiliates. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
@ -44,7 +44,7 @@ int AbstractInterpreter::size_activation(int max_stack,
int overhead = frame::sender_sp_offset -
frame::interpreter_frame_initial_sp_offset;
// Our locals were accounted for by the caller (or last_frame_adjust
// on the transistion) Since the callee parameters already account
// on the transition) Since the callee parameters already account
// for the callee's params we only need to account for the extra
// locals.
int size = overhead +

16
src/hotspot/cpu/x86/assembler_x86.cpp
View File

@ -359,7 +359,7 @@ bool Assembler::query_compressed_disp_byte(int disp, bool is_evex_inst, int vect
int cur_tuple_type, int in_size_in_bits, int cur_encoding) {
int mod_idx = 0;
// We will test if the displacement fits the compressed format and if so
// apply the compression to the displacment iff the result is8bit.
// apply the compression to the displacement iff the result is8bit.
if (VM_Version::supports_evex() && is_evex_inst) {
switch (cur_tuple_type) {
case EVEX_FV:
@ -444,7 +444,7 @@ bool Assembler::query_compressed_disp_byte(int disp, bool is_evex_inst, int vect
bool Assembler::emit_compressed_disp_byte(int &disp) {
int mod_idx = 0;
// We will test if the displacement fits the compressed format and if so
// apply the compression to the displacment iff the result is8bit.
// apply the compression to the displacement iff the result is8bit.
if (VM_Version::supports_evex() && _attributes && _attributes->is_evex_instruction()) {
int evex_encoding = _attributes->get_evex_encoding();
int tuple_type = _attributes->get_tuple_type();
@ -1047,7 +1047,7 @@ address Assembler::locate_operand(address inst, WhichOperand which) {
assert(ip == inst+1, "no prefixes allowed");
// no EVEX collisions, all instructions that have 0x62 opcodes
// have EVEX versions and are subopcodes of 0x66
ip++; // skip P0 and exmaine W in P1
ip++; // skip P0 and examine W in P1
is_64bit = ((VEX_W & *ip) == VEX_W);
ip++; // move to P2
ip++; // skip P2, move to opcode
@ -1765,7 +1765,7 @@ void Assembler::cmpxchgb(Register reg, Address adr) { // cmpxchg
void Assembler::comisd(XMMRegister dst, Address src) {
// NOTE: dbx seems to decode this as comiss even though the
// 0x66 is there. Strangly ucomisd comes out correct
// 0x66 is there. Strangely ucomisd comes out correct
NOT_LP64(assert(VM_Version::supports_sse2(), ""));
InstructionMark im(this);
InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);;
@ -3592,7 +3592,7 @@ void Assembler::nop(int i) {
// 15: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
while(i >= 15) {
// For Intel don't generate consecutive addess nops (mix with regular nops)
// For Intel don't generate consecutive address nops (mix with regular nops)
i -= 15;
emit_int24(0x66, 0x66, 0x66);
addr_nop_8();
@ -3762,7 +3762,7 @@ void Assembler::nop(int i) {
// 15: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
while (i >= 15) {
// For ZX don't generate consecutive addess nops (mix with regular nops)
// For ZX don't generate consecutive address nops (mix with regular nops)
i -= 15;
emit_int24(0x66, 0x66, 0x66);
addr_nop_8();
@ -5298,7 +5298,7 @@ void Assembler::rep_stos() {
NOT_LP64( emit_int16((unsigned char)0xF3, (unsigned char)0xAB);)
}
// scans rcx pointer sized words at [edi] for occurance of rax,
// scans rcx pointer sized words at [edi] for occurrence of rax,
// generic
void Assembler::repne_scan() { // repne_scan
// SCASQ
@ -5307,7 +5307,7 @@ void Assembler::repne_scan() { // repne_scan
}
#ifdef _LP64
// scans rcx 4 byte words at [edi] for occurance of rax,
// scans rcx 4 byte words at [edi] for occurrence of rax,
// generic
void Assembler::repne_scanl() { // repne_scan
// SCASL

10
src/hotspot/cpu/x86/assembler_x86.hpp
View File

@ -136,7 +136,7 @@ REGISTER_DECLARATION(Register, r12_heapbase, r12); // callee-saved
REGISTER_DECLARATION(Register, r15_thread, r15); // callee-saved
#else
// rscratch1 will apear in 32bit code that is dead but of course must compile
// rscratch1 will appear in 32bit code that is dead but of course must compile
// Using noreg ensures if the dead code is incorrectly live and executed it
// will cause an assertion failure
#define rscratch1 noreg
@ -388,7 +388,7 @@ class AddressLiteral {
friend class LIR_Assembler;
};
// Convience classes
// Convenience classes
class RuntimeAddress: public AddressLiteral {
public:
@ -442,7 +442,7 @@ class ArrayAddress {
class InstructionAttr;
// 64-bit refect the fxsave size which is 512 bytes and the new xsave area on EVEX which is another 2176 bytes
// 64-bit reflect the fxsave size which is 512 bytes and the new xsave area on EVEX which is another 2176 bytes
// See fxsave and xsave(EVEX enabled) documentation for layout
const int FPUStateSizeInWords = NOT_LP64(27) LP64_ONLY(2688 / wordSize);
@ -2818,7 +2818,7 @@ public:
// Set the instruction to be encoded in AVX mode
void set_is_legacy_mode(void) { _legacy_mode = true; }
// Set the current instuction to be encoded as an EVEX instuction
// Set the current instruction to be encoded as an EVEX instruction
void set_is_evex_instruction(void) { _is_evex_instruction = true; }
// Internal encoding data used in compressed immediate offset programming
@ -2828,7 +2828,7 @@ public:
// This method unsets it so that merge semantics are used instead.
void reset_is_clear_context(void) { _is_clear_context = false; }
// Map back to current asembler so that we can manage object level assocation
// Map back to current assembler so that we can manage object level association
void set_current_assembler(Assembler *current_assembler) { _current_assembler = current_assembler; }
// Address modifiers used for compressed displacement calculation

6
src/hotspot/cpu/x86/c1_LIRAssembler_x86.cpp
View File

@ -456,7 +456,7 @@ int LIR_Assembler::emit_unwind_handler() {
__ mov(rbx, rax); // Preserve the exception (rbx is always callee-saved)
}
// Preform needed unlocking
// Perform needed unlocking
MonitorExitStub* stub = NULL;
if (method()->is_synchronized()) {
monitor_address(0, FrameMap::rax_opr);
@ -2271,7 +2271,7 @@ void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr
raddr = frame_map()->address_for_slot(right->single_stack_ix());
} else if (right->is_constant()) {
address const_addr = float_constant(right->as_jfloat());
assert(const_addr != NULL, "incorrect float/double constant maintainance");
assert(const_addr != NULL, "incorrect float/double constant maintenance");
// hack for now
raddr = __ as_Address(InternalAddress(const_addr));
} else {
@ -3654,7 +3654,7 @@ void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) {
} else {
__ testptr(tmp, tmp);
__ jcc(Assembler::notZero, update);
__ stop("unexpect null obj");
__ stop("unexpected null obj");
#endif
}

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