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8332533: RISC-V: Enable vector variable shift instructions for machines with RVV

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Reviewed-by: fyang, mli
This commit is contained in:
Gui Cao 2024-05-22 06:56:40 +00:00 committed by Fei Yang
parent 5f804b2ec1
commit 67f03f2a4f
1 changed files with 2 additions and 2 deletions
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4
src/hotspot/cpu/riscv/matcher_riscv.hpp
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@ -128,8 +128,8 @@
static const bool int_in_long = true;
// Does the CPU supports vector variable shift instructions?
static constexpr bool supports_vector_variable_shifts(void) {
return false;
static bool supports_vector_variable_shifts(void) {
return UseRVV;
}
// Does target support predicated operation emulation.