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8351033: RISC-V: TestFloat16ScalarOperations asserts with offset (4210) is too large to be patched in one beq/bge/bgeu/blt/bltu/bne instruction!
Reviewed-by: fyang
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bb70896e35
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79880e5637
@ -2287,7 +2287,7 @@ void C2_MacroAssembler::float16_to_float(FloatRegister dst, Register src, Regist
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mv(t0, 0x7c00);
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andr(tmp, src, t0);
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// jump to stub processing NaN and Inf cases.
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beq(t0, tmp, stub->entry());
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beq(t0, tmp, stub->entry(), true);
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// non-NaN or non-Inf cases, just use built-in instructions.
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fmv_h_x(dst, src);
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@ -2330,7 +2330,7 @@ void C2_MacroAssembler::float_to_float16(Register dst, FloatRegister src, FloatR
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// replace fclass with feq as performance optimization.
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feq_s(t0, src, src);
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// jump to stub processing NaN cases.
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beqz(t0, stub->entry());
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beqz(t0, stub->entry(), true);
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// non-NaN cases, just use built-in instructions.
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fcvt_h_s(ftmp, src);
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@ -2391,7 +2391,7 @@ void C2_MacroAssembler::float16_to_float_v(VectorRegister dst, VectorRegister sr
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vfwcvt_f_f_v(dst, src);
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// jump to stub processing NaN and Inf cases if there is any of them in the vector-wide.
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bnez(t0, stub->entry());
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bnez(t0, stub->entry(), true);
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bind(stub->continuation());
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}
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@ -2445,7 +2445,7 @@ void C2_MacroAssembler::float_to_float16_v(VectorRegister dst, VectorRegister sr
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vfncvt_f_f_w(dst, src);
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// jump to stub processing NaN cases.
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bnez(t0, stub->entry());
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bnez(t0, stub->entry(), true);
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bind(stub->continuation());
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}
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